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Change-Id: Id7634099e40c0bf97944be124b494c41d6335ad7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Clang does not recognize comments to indicate falltrough is intended
behavior.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Idcf7a24fc763b80863902702172b4ea950e132b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77431
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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x86 assembly code uses a lot of nested macros so increase the default
value from 20 to 1000.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic23c452514de7dc1aa420541b756c443180b8b37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77430
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the schematic, karis does not have a UWB, remove
related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I8a442518c2007cde883183871cef96db416850c0
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77437
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The tool 'toada' which converts the Kconfig output to ada syntax keeps
running even when it can't parse something. Change that behavior to
halt, and update the error message to show where the error is coming
from.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I29807a054581060d04b9ecbe02f2ba666c46bcf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Any builds using ADA were getting a message saying:
`couldn't parse value '-1' for 'SEABIOS_DEBUG_LEVEL'`
This change allows toada to parse negative integers.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6507c54976b67f1ad70846b6bd6c54c861130d3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77421
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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- Change all links to wikipedia to https.
- Update some links to wikipedia that were incomplete.
- Update a few links that are now broken.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If780e15997c499d1df975b436fd9af530f324eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77488
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both mainboards have the same documentation. Instead of having two list
items referring to the same document, just merge the two items.
This fixes the following Sphinx warning:
WARNING: duplicated entry found in toctree: mainboard/lenovo/w530
Change-Id: I4140b34db01b1d5f47a39b9c1e33405e7789de63
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77503
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The document for northbridge/intel/i440bx doesn't exist and it didn't
exist at the time of introduction of these two mainboard documents. So
replace the reference with just the northbridge name.
This fixes the following Sphinx warning:
WARNING: unknown document: '../../northbridge/intel/i440bx/index'
Change-Id: Iaa67399f9d0e62d5d54ae08f5ebb8c70073c601f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Add new documentation generated by util/util_readme/util_readme.sh.
This also fixes the following Sphinx warning:
util/abuild/index.md: WARNING: document isn't included in any toctree
Change-Id: I26c33af3c5a5853f6bcce23e982a6b192b01f1d7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Sections may not start with transitions. Remove them.
This fixes the following Sphinx error:
ERROR: Document or section may not begin with a transition.
Change-Id: I519af83df14e44b0709dee7e338dba1ee6413f0a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77440
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iabbb637c797a361a2cbc55505002774ff4f774e1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77526
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clevo started using OZ711LV2 for the SD card reader around the time of
making its TGL boards. Without the driver, CPUs don't go to power states
lower than C2 due to LTR not being programmed. After enabling the driver
the CPU will go to C8 while the system is idle, giving significant power
savings if the system is left on battery power.
There is another issue with RPL where it only goes to C6 instead of C8.
This may be due to the intel_idle driver in Linux (as of 6.5-rc6
mainline and 6.4.6 stable) not supporting RPL C-states.
- tgl: Started being used with the Gazelle 3060 variant
- adl: Used on all models
- rpl: bonw15 does not have an SD card reader
Change-Id: I85c60feb6dcae7d877e70a6c6f2d3a7b3296fa0e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The psp_transfer.h file was the same under all SoCs, and is really
tied to the file common/vboot/transfer.c, not the SOC.
This patch makes an include directory under vboot to put the header into
and sets it to be included for all SoCs using SOC_AMD_COMMON. This makes
the header file available to all platforms, so that new chips that don't
use the psp_verstage don't have to make a psp_transfer.h file just to
satisfy the compiler.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b9f2adee3a1d4d8d32813ec0a850344b7d717b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77303
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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License classifiers are much better about classifying files with SPDX
headers than they are at classifying the general text licenses due to
minor variations in the text. To help with classification, add the
SPDX headers to the files.
To see the current state of coreboot's licensing, see:
https://coreboot.org/fossology/
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If490f6705e7862d9ad02c925104113b355434101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add new block for handling overclocking watchdog. The watchdog is
present since Skylake or maybe even earlier so it is safe to use with
most of the microarchitectures utilizing intelblocks.
The patch adds the common block for initializing and feeding the
watchdog. Timeout is defined statically in Kconfig and should be set
high enough by the board or SoC Kconfig to let the board boot with
full memory training and avoid reset loops. Full training of 128GB
DDR5 DIMM memory on AlderLake takes about 5 minutes. Newer SoCs
with newer memory technologies and higher RAM capacity may take more.
The default has been set to 10 minutes.
The patch also adds support for feeding watchdog in driverless mode,
i.e. it utilizies periodic SMI to reload the timeout value and restart
the watchdog timer. This is optional and selectable by Kconfig option
as well. If the option is not enabled, payload and/or software must
ensure to keep feeding the watchdog, otherwise the platform will
reset.
TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets
after some time. Enable the watchdog in driverless mode and see the
platform no longer resets and periodic SMI keeps feeding the watchdog.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68944
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new memory part in the mem_parts_used.txt and generate the
SPD ID.
1. MICRON MT62F512M32D2DR-031 WT:B
BUG=b:291018417
TEST=emerge-rex coreboot
Change-Id: I6e05c0d41a4899ed64dbab7efd8904cd361cb50e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77426
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:297276380
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot
chromeos-bootimage
Cq-Depend: chrome-internal:6373154
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
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According to the schematic, karis does not have a WWAN module, remove
related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This patch changes the SAR table selection logic to use FW_CONFIG which
will eventually help to support different WiFi SAR tables.
TEST=Able to build and boot google/rex.
Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de
Signed-off-by: YH Lin <yueherngl@google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These Kconfig options were being used basically as #define statements,
which is unnecessary. This isn't a good use of Kconfig options and would
be better just as #defines if actually needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This patch moves the line adding hwlib to the include path to the inner
makefile so that it doesn't get added to every build, but only when
CONFIG_USE_SIEMENS_HWILIB=y
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id668b76366a554efff560cec746e637487ebdbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77417
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This keeps the vc/amd/pi & pi/00670F00 Makefiles from getting pulled
into the build when they aren't needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If600c78c2ba74dd03cf493586dae037b96b7d623
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This change tells the build to only pull vc/eltan/security/Makefile.inc
into the overall build when USE_VENDORCODE_ELTAN is enabled in Kconfig.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1e462d8cc21c44716463c41cab598588cf4a22c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77418
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage.
BUG=b:296511904, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified by EE
Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Scaleway Tagada was removed with commit c013fa6234 and Intel Galileo was
removed with commit 037c25d4dd. So remove their configs.
Change-Id: I1c491f437b8a1104bdf31a34e3c7d2c4e5794301
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77415
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add two missing mapping for GPIO GPE routes
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3f0d13cf7c07201856e934f22efc4cc8c4ea5bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77423
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This compiler argument only exists on gcc.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I10902517c86daedc9853e6f6cac8fcf513211bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77436
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This fixes compilation with clang.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I675056c8a15fe446bba81a144bfea64d106df293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77435
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is necessary with clang.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Icc197fbd48b49bfa8770caf01727669b0ac59090
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Tweak a few sentences noticed when reading this.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0a072c83402bc551a6bbdb7cd7c55fc3505784b2
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77464
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: Patrick Georgi <patrick@coreboot.org>
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This is a useful feature, so add a note about it.
Change-Id: If29f6480f878bdaf877dc208cc4861b884e10840
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77465
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Update the U-Boot version to the latest release. Also switch to github
since it is typically much faster to download than the existing URL.
Drop the 'experimental' tag since this payload is pretty stable. It is
also tested regularly in U-Boot's CI.
Change-Id: I082130539c3474593a82e4b21cb995380f4db168
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77463
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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We only checked that the resource fits below the given `limit` in
memranges_find_entry(), but then accidentally placed it at the top
of the found memrange. As most resources have only a coarse limit,
e.g. the 4G barrier of 32-bit space, this became only visible when
artificially setting an unusual, lower limit on a resource.
So, for the final placement, use `MIN(limit, range end)` instead
of the range's end alone.
Change-Id: I3cc62ac3d427683c00ba0ac9f991fca62e99ce44
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Set customized_leds value for RTL8111K to fix led can't work.
BUG=b:297093096
BRANCH=firmware-brya-14505.B
TEST=Verified RTL8125 and RTL8111K led can work normally.
Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the nokris variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:285838647
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOKRIS
Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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In order to support logging of events for PSR data backup command
status during CSE firmware downgrade, add support for
ELOG_TYPE_PSR_DATA_BACKUP and ELOG_TYPE_PSR_DATA_LOST types.
BRANCH=None
BUG=b:273207144
TEST=Verify event shows in eventlog after CSE firmware downgrade
Change-Id: Ibb78ac8d420bb7a64328ce009ddcb99030519ec6
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77005
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
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Add new eventlog types to support logging of Platform Service Record
(PSR) backup related messages. Eventlog entries are added on PSR data
backup success/failure and also when PSR data is lost.
BRANCH=None
BUG=b:273207144
TEST=Verify elog event added after PSR data backup command is sent
cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent
...
ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC
Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:271491845
TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08
Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The `use_8254` should be flipped, the same as the other Intel
SOCs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Joxer will have SKUs with no type-c on daughter board, add fw_config
for EC control it.
BUG=b:297131468
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idd3acd204c0809753b6f5534790e1dc81c10b761
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71859
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command
00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0
00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1
Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Fix regression introduced in I25e757108e0dd473969fe5a192ad0733f1fe6286
"payloads/external/LinuxBoot: Clean up".
Include the initrd into the payload. Allows to actually use LinuxBoot.
Change-Id: I5ab6b1a43a4100e83f4c188b9ea3451ab7b4ffe5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77412
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile
SoCs have, so add the additional 3 SMN base address definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When LZMA compression is selected, then it's not needed to check if LZ4
compression is selected in addition. So instead of handling both cases
separately, check for LZ4 only if LZMA is not selected.
This applies to the cases of both, FSP-M and FSP-S.
Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage
gpio table.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of
GPP_F14, GPP_F15 and GPP_F16 GPIOs.
BUG=none
TEST=none
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I124e7d68198050616795a67df23b6481f6fe1276
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77407
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To avoid redundancy about how to call into `Makefile.sphinx`,
only do that from the `Documentation/Makefile` and call into
that from the top level.
Change-Id: I99c462cdaf83d711e4b7c07b713d304274db8cb4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie910f654abdb8d79c686363d2bd8af4ceeea4087
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76436
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Internal flashing possible
- Fix link
- Link here from the list of mainboards
- More consistent naming
Change-Id: Iaf6448c1e9f0dae9480fa9785a12f09d42f8cf7d
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77377
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with a Kingston UV500.
It works the same (3Gb/s) as with vendor FW.
According to smartctl -a /dev/sda:
SATA Version is: SATA 3.1, 6.0 Gb/s (current: 3.0 Gb/s)
Change-Id: I5c714351586e6084029ce4c54fb47cbae4d3405b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77376
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Delete this RTC from the configuration as fa_ehl mainboard
uses a different real time clock.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
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The mainboard currently does not make use of a dedicated TPM.
Although it has one assembled. This TPM is not connected
via LPC hence it is turned off in the devicetree.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
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fa_ehl mainboard does not make use of the SIEMENS NC_FPGA
as it is not placed on this board.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
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This patch saves the output of the IWYU build into $(obj)/iwyu.txt. It
will also automatically adds -k to the MAKEFLAFGS when IWYU is selected,
so that the build doesn't halt after the first operation.
When IWYU is not selected, there is no change to the build.
This will allow us to create an automated IWYU build on jenkins.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0ea300d4c64bb923e9f7cc0e595885c3006ec3ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77192
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Enable bit 9 for 100M mode green LED blink.
Reference:
- RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration
BUG=b:293983804
TEST=emerge-dedede coreboot and verify LAN LED behavior
Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko.
BUG=b:294928078, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Icb952c0716d446d5feb5580f357120a27193284e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For libflashrom we need the delay functions but when including the whole
libpayload.h it has conflicting symbols.
Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Those values need to match with the ones defined in PMC PWRM
GPIO CFG register.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I8e84df83caab794e2fe7186e89e78343c2b55fd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add a new mainboard called fa_ehl which is based on Siemens's
'mc_ehl2'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Moreover a variants
scheme is provided for possible alternative implementations. Follow-up
commits will introduce the needed changes for the new mainboard.
Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
|
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a pmc.h file, which is needed for OC watchdog compilation. The PMC
definitions from pm.h are moved to pmc.h.
TEST=Build UP Squared and Intel GLKRVP sucessfully.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Change-Id: I8308ac1d2f3c9a34b55c788797bccd4e7fcefd5c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77348
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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GPT timer init is no longer needed after DRAM blob is switching to ARM
arch timer.
BUG=b:229800119
TEST=boot to kernel
Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 0c11187c:
2023-08-07 11:41:45 +0000 - (vboot_reference: Rename Cr50 to GSC when applicable)
to commit id 24cb127a:
2023-08-22 00:19:10 +0000 - (sign_uefi_unittest.py: Fix long-line lint)
This brings in 24 new commits:
24cb127a sign_uefi_unittest.py: Fix long-line lint
52ac0c71 dump_fmap: Rename format name from 'pretty' to 'parser'
068376d9 dump_fmap: Add description about formats
f67ae949 crossystem: stop supporting legacy chromeos_acpi driver
e6bd72f7 Revert "futility/cmd_vpd: Add vpd listing subcommand"
c7593acc futility: updater: fix build warning 'incompatible function pointer'
394fbfad crossystem: Binary search RW_NVRAM to find the active entry
a5b80353 keygeneration: drop ec_{data,root}_key
1c9b603d futility: updater: Refactor manifest generation
0a4be4a0 futility: updater: Use signer_config for all boards by default
f9d1f0b0 futility: Fix closing file in error path
4dbadfb3 vboot_reference: Remove VB2_RECOVERY_CR50_BOOT_MODE
11bdc1f5 futility: updater: Enable keyset in signer_config based manifest
35e69bcd futility: Change FLMSTR values set by --unlock_me
0ca8212b futility: updater: Use signer_config manifest instead of setvars
0e24a8ef scripts: use new fw updater pack/repack commands
4378179b futility/cmd_vpd: Add vpd listing subcommand
2fc252d8 futility: updater: Remove deprecated Glados platform quirks
3119182d x86/crossystem: Fix snprintf error for hostlib
06a0b9d0 sign_uefi: Remove exception catching
bcfd831e sign_uefi: Clarify comment for removing signatures
4cb7b0e5 crossystem: support new chromeos_acpi driver
eb37f19d vboot: remove trailing newline from sysfs
ec173ee4 vboot: rename ReadFileString() to ReadFileFirstLine()
Change-Id: I6c92791404dc1c6a3efc8bb9046fe5017ba794fb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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According to the schematic, karis does not have a SPI touchscreen,
remove related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The SPDX license header for this file did not match the license text
in the file.
Update the SPDX header and remove the license text.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc0db79e43df6d14b80b0ad3061fe42de17ed90f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77379
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19a69ffdf2c248223569153c00fbc76d5ceb7921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: If3c2e5bd9ee7e0f77d0c39ffe2ca9ad17b77d9bd
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Program the EC GPIOs to enable the DT or M.2 SSD1
PCIe slots based on the config option selected.
Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Set EnforceDdrMemoryFreqPor to 0 for RMT builds. This is needed
for proper functioning when EnforcePopulationPor is set to 1.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Icf4fe01ac9b546830334717dbfa53782d2a85ba1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx",
MT8188G used in ChromeOS project does not support clock hardware
monitor. Thus, we can simplify the initialization flow by removing the
hardware default value check.
BUG=b:292866009
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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When the script is run, it fetches a new copy of the repo, then creates
a tag, signed by GPG. When this signing step runs, a window pops up for
the user to enter their PGP key's passphrase. This window prevents the
user from doing anything else on their desktop, like looking up the
passphrase. It also times out after a while, and causes the script to
fail at that point.
To prevent this annoyance, pause right before the step asking for the
passphrase until the user is ready.
Because the submodules aren't tagged, we can delay their update until
after the tag is created to lower the amount of time needed before the
tag & signing step.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I414dfc0f8944b4408881392278a2bce2a364992b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77366
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This script allows any user with abandon rights to abandon patches that
haven't been touched (reviewed, commented on, rebased, etc) in over a
year.
As a part of the release process, we're now going to run the script to
abandon all of those patches so that we don't get to the point of
needing to abandon 1300 patches again in the future.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4a07c09edf02d9c1858a58322095eefbceb529d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Create the quandiso variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_QUANDISO
Change-Id: I846c39260e2db504d7bec6e81a8317b6824c17f4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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According to the schematic, karis does not have a WWAN temperature
sensor, remove related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ic82c6cfec067faa37d452bed5c4977402a2139a5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77284
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This change are added fine-tuned USB2 PHY parameters to improve the
USB2 eye diagram result.
BUG=b:296493887
BRANCH=firmware-dedede-13606.B
TEST=Local build bios successfully.
And verified the USB2 eye diagram test result.
Change-Id: I915fe689883267901e8faba28632345d8c227c28
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 6f36ebd:
2023-06-13 16:09:19 -0600 - (microcode-20230613 Release)
to commit id 6788bb0:
2023-08-08 12:04:21 -0600 - (microcode-20230808 Release)
This brings in 1 new commits:
6788bb0 microcode-20230808 Release
https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20230808
Change-Id: I2885b0189c4b6e68dc5ae6b2a3f809280ed4507a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77132
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I05c84cae5a050cc69f4d9eecaa0f82caacc85c2d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77345
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Separate constitution and intrepid wifi sar table in variant.c
BUG=b:291859402
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I0f89b3d5f5252a2b55bad4d91ad4ab9ec7519c50
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When using the Windows fast startup mechanism which is enabled by
default, Windows will use a cached version of the ACPI tables during
normal boots after a clean shutdown. Since I've run into this issue and
spent quite a bit of time debugging the wrong issue due to this, better
document this possibly unexpected behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia9e65f6a3aff13fa54abe68c8f5fcbf9bc6efc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add some HDMI-related gpios that are needed for early sign-of-life
to the early_graphics_gpio_table array so that SOL will show up on
HDMI ports.
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds
without error.
Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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