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authorCliff Huang <cliff.huang@intel.com>2023-07-14 17:25:50 -0700
committerFelix Held <felix-coreboot@felixheld.de>2023-08-24 13:33:50 +0000
commit711f84d177db1f05054e5524f2492e9881a4eab6 (patch)
tree26d430f517ba2f7ccbf57af1f236cf60e3132e52
parent377153d58d726d6e8b3d3fc388bc50598a769bb4 (diff)
soc/intel/metorlake: Fix PMC GPIO group assignment
Those values need to match with the ones defined in PMC PWRM GPIO CFG register. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I8e84df83caab794e2fe7186e89e78343c2b55fd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
-rw-r--r--src/soc/intel/meteorlake/include/soc/pmc.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/meteorlake/include/soc/pmc.h b/src/soc/intel/meteorlake/include/soc/pmc.h
index 9a7aabfb1a..6c40b4a5ee 100644
--- a/src/soc/intel/meteorlake/include/soc/pmc.h
+++ b/src/soc/intel/meteorlake/include/soc/pmc.h
@@ -118,9 +118,11 @@ extern struct device_operations ioe_pmc_ops;
#define PMC_GPP_E 0x3
#define PMC_GPP_H 0x4
#define PMC_GPP_F 0x5
-#define PMC_GPP_S 0x6
-#define PMC_GPP_B 0x7
-#define PMC_GPP_D 0x8
+#define PMC_GPP_VGPIO3 0x6
+#define PMC_GPP_VGPIO 0x7
+#define PMC_GPP_S 0x8
+#define PMC_GPP_B 0x9
+#define PMC_GPP_D 0xa
#define GBLRST_CAUSE0 0x1924
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)