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2023-11-13mb/51nb/x210: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I0f069f02e4f0957cbff05d1bc9aa499fb51b6a02 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-13soc/amd/genoa: Hook up MCA codeArthur Heymans
This patch uses AMD SoC common code for MCA and adds MCA bank information as per Genoa Processor Programming Reference (PPR) version 0.25 (#55901) and uses AMD SoC common code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If728d803d600f7e86507cd1b35b40022bf4d379e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76524 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13soc/amd/genoa: Hook SMP and SMM initArthur Heymans
All CPUs properly come out of reset and relocate SMM. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I8c2d976addacd5a2ba70eb629510128853b9f847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-13soc/amd/genoa: Double HEAP_SIZE to 0x200000Varshit Pandya
Default value of HEAP_SIZE is 0x100000, since genoa has a lot of CPU increase the HEAP_SIZE to 0x200000 Change-Id: Idd707200fe72730849267cd3cafc40e44f1f8c5d Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-13security/vboot: Die if vb2api_reinit() failedYu-Ping Wu
In vboot_get_context(), vb2api_reinit() is called to restore the vboot context from the previous stage. We use assert() for the return value of vb2api_reinit() because there shouldn't be runtime errors, except for one edge case: vb2_shared_data struct version mismatch. More precisely, when RW firmware's VB2_SHARED_DATA_VERSION_MINOR is greater than RO's, vb2api_reinit() will return VB2_ERROR_SHARED_DATA_VERSION. To avoid using an invalid vb2_context pointer (when FATAL_ASSERTS is disabled), change assert() to die() on vb2api_reinit() failure. For the vb2api_init() case the assertion is unchanged because there shouldn't be any runtime error for that. Also move the vb2api_init() call outside the assert() argument, as assert() may be a no-op macro depending on the implementation. Change-Id: I4ff5ef1202bba2384c71634ec5ba12db1b784607 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-13mb/google: Remove obsolete Kconfig symbol VBT_DATA_SIZE_KBMartin Roth
The symbol VBT_DATA_SIZE_KB was removed in commit 8bde652241 - "drivers/intel/gma/opregion: Use CBFS cache to load VBT" CB:77886, however that patch only removed the Kconfig option from the Intel chipsets, leaving it unused in the mainboards. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia29d8d6ec17b172e662ff591849f1668d65f1ff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78967 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13fmap: Map less space in fallback path without CBFS verificationJulius Werner
This is a fixup to CB:78914 which inadvertently broke the RK3288 SoC. Unfortunately we can only accommodate very little PRERAM_CBFS_CACHE in the tiny SRAM for that chip, so we would not be able to map an entire FMAP. Solve this problem for now by mapping less space when CBFS verification is disabled, and disallowing CBFS verification on that SoC. Change-Id: I2e419d157dc26bb70a6dd62e44dc6607e51cf791 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-13drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksumBill XIE
Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2023-11-13security/tpm/: turn tis_{init,open} into tis_probeSergii Dmytruk
init() was always followed by open() and after successful initialization we only need send-receive function which is now returned by tis_probe() on success, thus further reducing number of functions to export from drivers. This also removes check for opening TIS twice that seems to have no value. Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76954 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13arch/x86/riscv: Use 'all' target to include files in all stagesArthur Heymans
This adds a few new files to romstage, that will be needed in follow-up patches. Change-Id: I2ba84e0becee883b5becf12e51f40734cad83d7d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68839 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-11-13Update genoa_poc/opensil submodule to upstream mainMartin Roth
Updating from commit id d81517e: 2023-09-28 14:13:56 -0600 - (Improper bit field offset calculation) to commit id 0411c75: 2023-11-10 23:59:34 +0000 - (Minor changes to fix issues compiling with clang) This brings in 1 new commits: 0411c75 Minor changes to fix issues compiling with clang Change-Id: Ib3adfd7bccd45dfd76ede462677dcfb294baa15d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-13util/lint/kconfig_lint: Ignore C preprocessor macros in codeMartin Roth
To see which Kconfig symbols are actually used, and to verify that they're used correctly, kconfig_lint scans the C code. It gives an error if it sees a CONFIG(symbol) where the symbol doesn't exist. This creates a problem when a C preprocessor macro is created to match multiple Kconfig symbols. The simple solution here is to just ignore those C preprocessor macro definitions as beyond the scope of this linter. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5a20e8bb5a3e19e380802cba712d6dd3ff2f4dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78681 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-13acpi/acpigen: point out what acpigen_write_len_f doesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf2f54f2f428f4438ef22b7f9d205db10e144db Reviewed-on: https://review.coreboot.org/c/coreboot/+/79001 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-13MAINTAINERS: Add Felix, Martin, Varshit for soc/amd/genoaVarshit Pandya
Change-Id: Ia368f390901424ef427eaefaa57acf2b6ae5d703 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-13MAINTAINERS: sort AMD SoC alphabeticallyVarshit Pandya
Change-Id: I0eaf94f7fb91a4b11dab2731a0b5d08aa85fd41e Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78988 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13MAINTAINERS: Add Felix, Martin, Varshit for mb/amd/onyxVarshit Pandya
1. Split AMD mainboard between AMD server and AMD non-server SoC 2. Add maintainers for onyx mainboard Change-Id: I94814da1c06d57cc63c9b968866570a812346fde Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78987 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13tests/acpigen: Patch to allow moving buffersNico Huber
When a package length needs to be written, we used to always write three bytes for it, even when the length would fit into one or two bytes. To allow such compact package lengths, we have to move the written buffer data in case the length is smaller. This makes tracking the start of nested buffers harder, as they may be moved entirely later when a package length is written. So instead of tracking start addresses in test_acpigen_nested_ifs(), let's work with the generated AML alone. In this lucky case, we can simply search for the `if` operations. Change-Id: Id8557dd5d1be3878713ee0b6106c3e0975665e97 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-13arch/riscv/ramstage.S: Add comments for passed argumentsMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ib1af1359249008d9eba351271637748a7edcec26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78966 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/google/nissa/var/gothrax: Add GPIO configurationYunlong Jia
Add variant of LTE and WFC support on gothrax board. We base decisions on the values within the firmware configuration CBI field. In fw_config settings, if the board move LTE and WFC modules, the hardware GPP_A8/GPP_E13/GPP_F12/GPP_H19/GPP_H23/GPP_R6/GPP_R7 pins need to be deasserted. BUG=b:303526071 TEST=emerge-nissa coreboot & \ Check against schematic. Whether it works as expected under different SKUs. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ia8041bdc599509911bde95d6294314036e75b227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78916 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13spd/lp4x: Add SPD for CXDB4CBAM-ML-A in parts_spd_manifest.generated.txtDaniel Peng
Generate initial SPD matched for CXMT CXDB4CBAM-ML-A. BUG=b:304932936 TEST=make -C util/spd_tools util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: Ia33a94a1784f865b4776ad9107e25e87420f944f Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78891 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-12util/docker/jenkins-node: Install pip modules into virtual envMartin Roth
Instead of installing the pip modules system-wide, and possibly causing conflicts, install them into a virtual environment for the coreboot user. If we wanted to, in the future, we could install different versions of the modules into different virtual environment directories to allow for testing or anything else we needed. Change-Id: I49c749a13a698bfb7af29bf07e42ac14b67b2ae7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-12util/docker: change main branch back to master for encapsulateMartin Roth
The branch for the encapsulate tool accidentally got caught up in the switch from master to main. The default branch for this tool has not changed, so still needs to be referenced as master. Change-Id: I0ff47308dcbf30888e4e88637bab63f20467307a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-12mainboards: Drop stale comment about enumerate_buses()Nico Huber
There is no enumerate_buses() today and also no trace of it in our repository. Also, in current terms, mainboard_enable() is called as the very first thing in our enumeration so the comment seems misleading. Change-Id: Iae620f83c8166c1cfc8b9fb9ef4a7025987bf1be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-11rockchip/rk3288: Reshuffle memlayout to make a bit more verstage spaceJulius Werner
RK3288 is bursting at the seams again. This patch reshuffles two more kilobytes to verstage to make things fit a little better. Change-Id: I5e7667061dce3d02441be83c0b8fb81500a1b1a3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78970 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-11acpi/acpigen: Fix buffer length in acpigen_write_name_unicode()Matt DeVillier
The buffer length is in bytes, and since we are converting from ASCII to UTF-16, the value written needs to be 2x the string length + null terminator. TEST=build/boot google skyrim (frostflow), dump acpi and check bytecode for correct buffer length preceding unicode strings. Change-Id: Id322e3ff457ca1c92c55125224ca6cfab8762a84 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-11payloads/ipxe: Prefix iPXE options with "IPXE" instead "PXE"Felix Singer
Change-Id: Ieef433e9d6745c6243b4823c9a7f250d3c53ebcb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78926 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-11payloads/ipxe/Kconfig: Properly guard iPXE optionsFelix Singer
Guard multiple options depending on another with an if-block. It's not needed to repeat the condition for every option. This also cleans up the ordering of the options and groups all options related to iPXE. Change-Id: I9e74ab567f619a2d5c20c6c0282b37193d9ac01b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78925 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-11mb/clevo/kbl-u: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I51b3bca2421b64f73d4d3c0d9346a1416bf15f35 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78976 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-11mb/amd/birman: Use common option for variant configurationFelix Singer
When a variant setup is used, checking for each variant in order to do the mainboard configuration is quite painful. Thus, move the selects from BOARD_SPECIFIC_OPTIONS, which is enabled by default when a variant is chosen, out to a common option, which is disabled by default but selected by the variants. So in order to enter that config block, it's only needed to check if that common option is enabled and not for each variant. It's also a very common scheme now. Change-Id: I4ed889ce78a0d7cd088e05d0f4b7fbbc89153860 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-11mb/amd/birman: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I836c35e6bbfa77d536065a4237ef85a170df9fdb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-10mainboard/msi/ms7e06: Remove FSP_TYPE_IOTMichał Żygowski
MSI PRO Z790-P is not an IoT platform. FSP_TYPE_IOT was selected only temporarily to allow builds from public components. Now that Client FSP is available, switch to it. TEST=Build and boot MSI PRO Z790-P Change-Id: Ic5d84e48d58c3454b83b9df5eb93076d2ebde000 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-11-10soc/intel/alderlake: Allow using FSP repo for all RPL-S platformsMichał Żygowski
The Client FSP for Raptor Lake-S is present on the Intel FSP repository, so there is no need to restrict Raptor Lake-S FSP binary repository to IoT only. TEST=Build and boot MSI PRO Z790-P Change-Id: I77aecd6e2d753732bf6358afe2c7ea0491348387 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-10soc/alderlake: Fix order of defaults in FSP_HEADER_PATHMichał Żygowski
The combination of SOC_INTEL_RAPTORLAKE_PCH_S and FSP_TYPE_IOT is currently broken. By default, e.g. for MSI PRO Z790-P, the FSP_HEADER_PATH does not match the default FSP_FD_PATH. For headers the client FSP is selected, while for the FD file, IoT FSP binary is chosen. The order of default for both headers and FD file must be the same to match the headers and binaries. TEST=Build default MSI PRO Z790-P config and see that FSP_HEADER_PATH matches FSP_FD_PATH FSP variant-wise. Change-Id: I8db5ea10c2986ff8d3fa7d616b3f1617d05f0260 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78410 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-10soc/intel/meteorlake: Set DTT PCI device IRQ to INT_A/PIRQ_AJeremy Compostella
The Dynamic Tuning Technology (DTT) device IRQ is not programmable and is INT_A/PIRQ_A (IRQ 16). Reference: Meteor Lake U/H and U Type4 External Design Specification External Design Document (657165) TEST=Linux driver successfully uses IRQ 16 on rex. Without this patch it was binding IRQ 18 but interrupts were going to IRQ 16. Change-Id: I2cbb9dd41f27c40a29346be325bb9c46d1061afb Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-10mb/siemens/{mc_ehl3,mc_ehl5}: Fix GPIO settings for latest HW revisionMario Scheithauer
With the latest hardware revision of both mainboards, native function two of GPIO B23 (PCHHOT_N) is used for diagnostic purposes. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: Ibe130b5d4c74576294183221765c5f4db9b5ec2a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78962 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-10device/Kconfig: rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORTFelix Held
Rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT and add a help text to this Kconfig option to clarify what this option is about. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71e36869c6ebf77f43ca78f5e451aebfb59f1c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-10src: Remove unnecessary semicolons from the end of macrosMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia005915a05d02725f77b52ccd7acebefaf25d058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78964 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-10cpu/x86/smm: Fix get_save_state calculationEugene D. Myers
When the SMI transfer monitor (STM) is configured, get_save_state returns an incorrect pointer to the cpu save state because the size (rounded up to 0x100) of the processor System Management Mode (SMM) descriptor needs to be subtracted out in this case. This patch addresses the issue identified in CB:76601, which means that SMMSTOREv2 now works with the STM. Thanks to Jeremy Compostella for suggesting this version of the patch. Resolves: https://ticket.coreboot.org/issues/511 Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Signed-off-by: Eugene D. Myers <edmyers@cyberpackventures.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-10mb/google/rex/var/screebo: Update DFP portzhourui
Update DFP port setting for retimer power GPIO BUG=b:302428013 BRANCH=none TEST=Retimer enumaration in NDA works. Change-Id: Idc1a728ec4cbb66e776c2700025db41d85801c60 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-10mb/google/brya/Kconfig.name: Remove duplicate selectFelix Singer
That select is duplicate to the ones in the Kconfig file, and it shouldn't be there anyway. Remove it. Change-Id: I1a940f034a69f72280d15ab9a0c9d83f8111910e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78973 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-09mb/google/brox: Remove use of EC_IN_RW_OD GPIOShelley Chen
Later GSCs don't need a EC_IN_RW GPIO anymore, so removing the use of this for get_ec_is_trusted(). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I29f94969e9f2c1f239d9f9655f39b8410296f695 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-11-09Allow to build romstage sources inside the bootblockArthur Heymans
Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-09soc/amd: Remove unnecessary choice symbol name from PSP KconfigMartin Roth
There's no reason to name this choice block. Remove the name. Change-Id: Iebf8b1e7af928b988ab514d9dd85d2e70bf00c09 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78917 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-09mb/google/nissa/var/gothrax: Add FW_CONFIG probe about DB/WFCYunlong Jia
Add FW_CONFIG probe to separate WFC settings. WFC_PRESENT/WFC_ABSENT Add FW_CONFIG probe for new DB_USB sku. DB_C_A_LTE/DB_A BUG=b:303526071 TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I93e0bce4b8be37e259efe0d7b0185035b3e88785 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78963 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-09mb/google/rex/variants/deku: Add display configurationEran Mitrani
Enable DDI on ports 1 to 4 for Type-C DisplayPort. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I3acaff4a9306f2d058ce9542e8956ee0acba94cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78498 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-093rdparty/arm-trusted-firmware: Update submodule to upstream masterFelix Singer
Updating from commit id 37366af8d: 2023-07-28 17:04:54 +0200 - (Merge "fix(cpus): fix minor issue seen with a9 cpu" into integration) to commit id 88b2d8134: 2023-09-06 11:26:32 +0200 - (Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration) This brings in 225 new commits. Change-Id: I97147fbec5c0a91daab67524027f57962f61d0a1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-08mb/google/rex: split TOUCHSCREEN_I2C_SPI definitionYH Lin
As TOUCHSCREEN_I2C_SPI will be used for two different configurations, splitting it to TOUCHSCREEN_GSPI and TOUCHSCREEN_THC, and re-order the FW_CONFIG bits by moving VPU to different bit position. BUG=b:307774932 TEST=build and boot rex Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ied4d732ef7993e95edbb7eb281842b9392e72820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-08mb/google/brox: Configure early GPIOs in bootblockShelley Chen
Some GPIOs (like WP and GSC) need to be configured in bootblock. Making sure that they get configured earlier for this. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8dd4853bc05b954f47d858d87ea2aed48e4b8074 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78943 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08mb/google/brox: Correcting GPIOs based on latest schematicsShelley Chen
There are some inaccuracies in arbitrage. This is the first pass at correcting the incorrectly generated configs. I also tried to update the "No heuristic was found useful" comment generated by arbitrage into something more useful (ie: the appropriate NFs). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I836565e09a3e0b25746b3e2f9ed6610eaacf7e97 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78942 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08payloads/edk2: Remove the warning about edk2/master not workingSean Rhodes
Since #c4fdec0a83d69bd0399b1b4351fa9c3af3c6fd65, edk2/master will work with coreboot without modification. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8350f5114445d2608861ef6e807f958e598dfe07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-08mb/google/brya/var/anraggar: Initialise overridetreewuweimin
Initialise overridetree based on the schematics revision 20231020A. Added data.vbt just only for running abuild completed. Real vbt define by CONFIG_INTEL_GMA_VBT_FILE in chromium:4936896. BUG=b:304920262 TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I232bde990747be80e1ab62c3f0d010d5fc854cb5 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78456 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08mb/google/brya/var/anraggar: Add initial GPIOs configwuweimin
Configure GPIOs according to schematics revision 20231025G. BUG=b:304920262 TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I7be6829fc27ee20e014c372d704333ebfd4967b8 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-08sio/nuvoton/npcd378: Use acpi_device_path_joinArthur Heymans
This achieves the same without the strconcat & free dance. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4d8e9bae6085a6e05847b01497fb4b51041ca7b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-08drivers/i2c/lenovo_serials: Use buildtime constantsArthur Heymans
The coreboot_version global variable just gets filled with the COREBOOT_VERSION macro so there is no reason to use a runtime strconcat. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3a2be7293d07ac591855ebd784bba350cdffa70f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78945 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-08mb/hp/elitebook_820_g2: do not set EC SLPT on S5Iru Cai
Setting EC SLPT bit in S5 will make HP EliteBook 820 G2 fail to reboot under Linux 6.1 and later kernel versions. Change-Id: I48f5a35cd78db3b32d9f76cb8e266c738da34e7c Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-07Kconfig.cbfs_verification: Update TOCTOU_SAFETY combination with VBOOTJulius Werner
Now that VBOOT_CBFS_INTEGRATION exists, it is possible to use TOCTOU_SAFETY with VBOOT. Change-Id: I9f84574f611ec397060404c61e71312009d92ba7 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78915 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-07fmap: Eliminate some impossible code pathsJulius Werner
When the FMAP cache is enabled, it cannot fail in pre-RAM stages unless flash I/O in general doesn't work. Therefore, it is unnecessary and a waste of binary size to also link a fallback path for this case. Similarly, once the cache is written to CAR/SRAM/CBMEM there should be no way for it to become magically corrupted between boot stages. Many other parts of coreboot blindly assume that persistent memory stays valid between stages so there is no reason why this code should link in extra fallback paths in case it doesn't. This saves a little over 200 bytes per affected (uncompressed) stage on aarch64. Change-Id: I7b8251dd6b34fe4f63865ebc44b9a8a103f32a57 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78904 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07fmap: Die immediately on verification failureJulius Werner
A recent security audit has exposed a TOCTOU risk in the FMAP verification code: if the flash returns a tampered FMAP during the first setup_preram_cache(), we will abort generating the cache but only after already filling the persistent CAR/SRAM region with the tampered version. Then we will fall back into the direct access path, which could succeed if the flash now returns the original valid FMAP. In later stages, we will just use the data from the persistent CAR/SRAM region as long as it looks like an FMAP without verifying the hash again (because the hash is only linked into the initial stage). This patch fixes the issue by just calling die() immediately if FMAP hash verification fails. When the verification fails, there's no recourse anyway -- if we're not dying here we would be dying in cbfs_get_boot_device() instead. There is no legitimate scenario where it would still be possible to continue booting after this hash verification fails. Change-Id: I59ec91c3e5a59fdd960b0ba54ae5f15ddb850480 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78903 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07fmap: Map full FMAP for verification in fallback pathJulius Werner
The rarely-used fallback path for accessing the FMAP without a cache currently only maps the FMAP header for the initial verify_fmap() call. This used to be fine when we were just checking the magic number, but with CBFS verification we may need to hash the entire FMAP. Since this path is so rarely used anyway and the size difference only has a practical impact on a few platforms, lets keep things simple and just always map the whole FMAP. Change-Id: Ie780a3662bf89637de93a36ce6e23f77fed86265 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78914 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07mb/google/rex/variants/deku: Add USB configurationEran Mitrani
+-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I743fd82f088a57e906b8b9d0fe2e012d9c5f9567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78497 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07mb/google/rex/variants/deku: Add SSD card configEran Mitrani
BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I167a02bf2219c6ef8e0093956a649305c8e8f76b Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-07mb/google/rex/variants/deku: Add I2C configEran Mitrani
Add I2C config based on Deku schematics. TPM is connected to I2C 4 BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I496e236531b2b59b320c77c36f542f4fa80a51a1 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78449 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07mb/google/rex/variants/deku: Add RAM id for MT62F2G32D4DS-026Eran Mitrani
Add RAM id for: MT62F2G32D4DS-026 WT:B (Micron) BUG=b:305793886 TEST=Run part_id_gen tool without any errors Change-Id: If2ed2bdcee44f6dbbda51a3ff484edaf3df4830d Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-07libpayload/libc/time: Fix possible overflow in multiplicationYidi Lin
The value from raw_read_cntfrq_el0() could be large enough to cause overflow when multiplied by USECS_PER_SEC. To prevent this, both USECS_PER_SEC and hz can be reduced by dividing them by their GCD. This patch also modifies the return type of `timer_hz()` from `uint64_t` to `uint32_t`, assuming that in practice the timestamp counter should never be that fast. BUG=b:307790895 TEST=boot to kernel and check the timestamps from `cbmem` Change-Id: Ia55532490651fcf47128b83a8554751f050bcc89 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78888 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07soc/amd/common,stoneyridge: drop invalid hda_soc_ssdt_quirksFelix Held
Drop the hda_soc_ssdt_quirks function since it doesn't apply for any of the SoCs supported by the Stoneyridge code which was the only SoC implementing it. This code was added when commit 91a7abf25c72 ("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") rewrote the code originally added in commit 1587dc8a2b4d ("soc/amd/stoneyridge: Add northbridge support") as a copy from northbridge/amd/pi/00670F00. This code was moved around in commit 6580408a7e0a ("amd/pi/hudson: Move audio to northbridge"), since the HDA controller was moved from the FCH to the northbridge complex. When the controller was moved, the PCI config space interface also changed, so those bits are no longer the DisableNoSnoop, DisableNoSnoopOverride, and EnableNoSnoopRequest bits of the Misc Control register of the HDA controller, but some bits within the ClassCodeW field of the ACGAZ Mirrot Reg Ctrl 0 register. BKDG #55072 Rev 3.04 (Stoneyridge), BKDG #50742 Rev 3.08 (family 15h model 60h-6fh / 00670F00), and BKDG #52740 Rev 3.05 (family 16h model 30h-3fh) were used as a reference. Only the SoC with BKDG #52740 still has the HDA controller in the FCH; the other two have it in the northbridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77fc76752b1c7de62ba8a196f15c198f55be3074 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78940 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07util/abuild: Add all builds to junit.xml filesMartin Roth
The builds from the configs directory were not being saved in the junit.xml files that Jenkins uses to determine pass vs fail of the individual builds. This also fixes the path to a log file that I noticed while testing. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I37dbee676cc9e507e612ce66994a04aba062757a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78863 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07Revert "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6. Reason for revert: It breaks wakeup from suspend on a bunch of boards. While this approach of eyeballing "correct" values by chipset _should_ be fixed, it should also be accompanied by compile time verification that the memory map works out. Since nobody seems to care enough, let's just revert this, instead of keeping the tree broken for a bunch of configurations. Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-07mb/google/rambi: Fix assumption that vboot runs after romstageArthur Heymans
Now VBOOT is always assumed to run after romstage and be linked inside romstage. This currently is the case but for flexibility reasons (e.g. linking romstage into bootblock or having a verstage before romstage) this could be more precise. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I361731c930a35e12245153920df1b6884d47064c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-07mainboard/google/poppy: Use initialized dataArthur Heymans
A .data section now exists. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic1510221582aca91c814d43f522a8fb6cba05921 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78937 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07console.c: Enable gdb support in bootblockArthur Heymans
This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I34812fbcd1222eceeb9870b9cbb7431ead63ce6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78936 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07console/spkmodem: Make it work for bootblockArthur Heymans
This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4113dc3208fe15305d1132136dd33417dd086bfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/78935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-07drivers/net/ne2k: Make it work for bootblockArthur Heymans
This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I708e8a3b503eb3a7fdf6063803d666529096f651 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-07vc/amd/opensil/genoa_poc/openSIL: Add openSIL code as submoduleMartin Roth
This is a RW mirror of AMD's openSIL for Genoa with additions from Arthur Heymans. - origin/openSIL/main from https://github.com/openSIL/openSIL.git - origin/ArthurHeymans/64b_public from https://github.com/ArthurHeymans/openSIL.git The current main branch starts with Arthur's branch and adds 5 commits from the AMD's openSIL repo. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8917edf3a6a8493ffa9230902cafcc6234d3d571 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-07doc/soc/intel/xeon_sp: Add Xeon-SP coreboot community preview guideShuo Liu
The community preview branch for coreboot on latest Xeon Scalable processor is opensource at: https://review.coreboot.org/plugins/gitiles/intel-dev-pub/. Change-Id: Ie2ffc1722a4a26d6039b6642efa95bf072d896ad Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-11-06soc/amd/genoa/chipset.dt: add UART device opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9fc155fe76c05fefd4ce31ae6b96dcc4527b6abc Reviewed-on: https://review.coreboot.org/c/coreboot/+/78901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-06soc/amd/*/iomap: drop unused I2C_MASTER_START_INDEX definitionsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0eae9e4d246bd07f43b1d77e5ad7649c010d0efe Reviewed-on: https://review.coreboot.org/c/coreboot/+/78899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-06soc/amd/common/block/i2c: add pre-processor guards for ACPIFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8dc93b12b81abee41f6f225f41d1f9953d1d93e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-06soc/amd/genoa/include/iomap: add missing I2C and I3C MMIO basesFelix Held
All base addresses of MMIO devices in the devicetree should also have corresponding defines in iomap.h. PPR #55901 Rev 0.26 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0444e6cc0587b484a4a1ff49fa4b1540a24c8e80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78897 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-06soc/amd/genoa/devicetree: fix MMIO base addressesFelix Held
The base addresses of I2C 5 and I3C 3 were wrong and all I3C controllers should use the base address of the 4kiB block where all registers of that I3C controller are located in. PPR #55901 Rev 0.26 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c983d4a709000ef7963b96228322603b98728aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/78896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-06payloads/ipxe/Makefile: Use sed more properlyFelix Singer
Instead of redirecting the output of sed into a temporary file and copying it to its target then, just tell sed to do the replacements in-place and don't let it create a backup of the original file. The overhead is not needed. Change-Id: I442616cd78098b653af5bd49bc7a4f021c99e081 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-04mb/google/poppy/var/nami: Fix SMBIOS name for Akali360Matt DeVillier
Remove space to improve compatibility with OS drivers and various tools, and to be consistent with other device names with the 360 suffix. TEST=build/boot Windows/Linux on Akali360, verify audio functional. Change-Id: Ib9b909dba939f726e6fbe71f5b4956b432086029 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-04libpayload/libc/getopt_long: Use common GCDYidi Lin
TEST=emerge-geralt libpayload Change-Id: Ib9dd1d2f658d4411c36d0198774819690686a393 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78887 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-04arch/arm64/arch_timer: Fix possible overflow in multiplicationYidi Lin
The value from raw_read_cntfrq_el0() could be large enough to cause overflow when multiplied by USECS_PER_SEC. To prevent this, both USECS_PER_SEC and tfreq can be reduced by dividing them by their GCD. BUG=b:307790895 TEST=emerge-geralt coreboot TEST=boot to kernel and check the timestamps from `cbmem` Change-Id: I366667de05392913150414f0fa9058725be71c52 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78800 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-04soc/qualcomm/sc7280: Enlarge BOOTBLOCK to 44KYidi Lin
After CB:78800 applied, the bootblock increases 2128 bytes and exceeded its allotted size (40K). Therefore, we enlarge BOOTBLOCK to 44K to solve the compilation error. This patch also increases PRERAM_CBFS_CACHE to 103K to fill the empty space (1K) between TIMESTAMP and TTB. BRANCH=none BUG=none TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B Change-Id: Iae9d44939b29098e823508dd3965a1bae7a69041 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-04Use common GCD functionYidi Lin
Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78799 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-04commonlib: Add GCD functionYidi Lin
Implement a simple GCD function. BUG=b:307790895 TEST=emerge-geralt coreboot TEST=make tests/commonlib/bsd/gcd-test Change-Id: I21819cda4299b3809b8ca7a95cbdc6a87e4b3481 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78798 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-04mb/google/brya/var/marasov: Enable Wi-Fi sar table for Intel moduleDaniel Peng
1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings on marasov. - WIFI_SAR_ID_0 for MTK Wi-Fi module MT7921L - WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW BUG=b:300045956 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77789 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-04soc/intel/meteorlake: Consolidate settings for enabling tracehubKane Chen
To get tracehub working, it requires few settings such as SOC_INTEL_METEORLAKE_DEBUG_CONSENT=2 and enable tracehub device in dev tree. This commit binds all tracehub related settings to Kconfig, so that users only need to enable SOC_INTEL_COMMON_BLOCK_TRACEHUB TEST=boot on screebo and test tracehub device exists and working Change-Id: Ie830fe2fd38e3456497bea37fe42ca60d26ca305 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-04mb/google/corsola: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBIYu-Ping Wu
Enable FW_CONFIG for corsola so that the information can be passed to payloads via coreboot tables. BUG=b:157692450 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I6c12041d3666907c884f5a50a12c1433c2085961 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-04soc/intel/alderlake: Add missing min sleep state for DPTF deviceMatt DeVillier
Add an entry in the min_pci_sleep_states array for SA_DEVFN_DPTF, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:04.0 TEST=build/boot google/brya (banshee), verify warning not present in cbmem log, verify entry for DPTF device in ACPI LPI constraint list. Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78877 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-03soc/amd/mendocino: Conditionally select HAVE_FSP_LOGO_SUPPORTKarthikeyan Ramasubramanian
Indicate FSP has support to display logo when graphics initialization is done in FSP. BUG=b:294055390 TEST=Build and boot to OS in Skyrim with and without passing the BMP logo buffer from coreboot. Change-Id: I6112c03723dcbc34cb0f57c400f831c765b95115 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78882 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-03soc/intel/braswell/Kconfig: Set HPET_MIN_TICKSMatt DeVillier
Commit 2bc9cee0f70f ("Braswell: Update the ACPI tables") switched the SoC from using its own HPET generation code to the common x86 code, but along the way the min_tick value got lost. Restore the original value prior to the above commit, which is now set via a Kconfig override. TEST=build/boot google/cyan (edgar), verify min_tick value in HPET ACPI table is correct. Change-Id: I2633e7cd0c3d74c1554ae8c1f2bb6387fd6dde2b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78744 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-03soc/intel/braswell: Unify DPTF enablementMatt DeVillier
Currently, there are 3 separate settings for DPTF which are not always in sync: - the enabled/disabled state of the devicetree PCI device - the 'dptf_enable' register, which sets the ACPI device status via GNVS - the 'DptfDisable' register, which sets the FSP UPD of the same name To make things sane, drop the two chip registers, and set the GNVS variable and FSP UPD based on the enabled/disabled status of the DPTF PCI device in the mainboard's devicetree. TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI devices are present/enabled when DPTF is enabled in devicetree, and not present/disabled when disabled in devicetree. Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-03soc/intel/cannonlake: Add missing entry to soc_acpi_name()Matt DeVillier
The device name for the SA thermal/DPTF PCI device was missing from soc_acpi_name(), leading to an invalid PLI device constraint entry being generated in the SSDT (the name field was blank/missing). Add the missing entry, matching the name to the existing ACPI device. TEST=build/boot Win11 on google/puff (wyvern) without a BSOD. Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78869 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-03soc/intel/cannonlake: Add missing min sleep state for thermal deviceMatt DeVillier
Add an entry in the min_pci_sleep_states array for SA_DEVFN_THERMAL, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:12.0 TEST=build/boot google/puff (wyvern), verify warning not present in cbmem log, verify entry for THRM device in ACPI LPI constraint list. Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78868 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-03mb/google/puff/var/*: Set LAN/WLAN device type to genericMatt DeVillier
Change the LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=build/boot Win11 on google/puff (wyvern). Verify LAN/WLAN devices function correctly under Windows and Linux. Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-03mb/google/nissa/var/craaskov: Disable storage devices based on fw_configRex Chou
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:305887856 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-03mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to genericMatt DeVillier
Change the dGPU/LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create does a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=untested Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78873 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-03soc/intel/cmn/gfx: Join MBUS while FSP-S performs GFX initSubrata Banik
This patch calls into the function to join the MBUS if the GFX PEIM module inside the FSP binary is taking care of graphics initialization based on the RUN_FSP_GOP config option. The FW skips joining the MBUS in case of a non-FSP solution and/or SOC_INTEL_GFX_MBUS_JOIN config is not enabled. BUG=b:284799726 TEST=MBUS joining is only applicable for google/rex while using GFX PEIM. Change-Id: I50d719a286722f5aafbad48ab4ca60500c836dd6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-02Revert "soc/intel/{tigerlake,meteorlake}: Check ITBT FW version"Ravi Sarawadi
This reverts commit 2e10a6d6f3ec46bcaf75bd066319d51f001be764. Reason for revert: The FW version check is not supported except for ADL platform. Reverted change broke S0ix functionality; the original CL was added as HW W/A for ADL ONLY. BUG=b:306214725 TEST=S0ix cycles on Rex with TBT Device attached. Change-Id: Ib8eb11d36eac4e1c94a3349386442fa3eeeaef37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 01:42:32 +0000