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2021-08-17mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen
Add SPD support to lantis for MT53E512M32D1NP-046 WT:B BUG=None BRANCH=firmware-dedede-13606.B TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-17mb/google/dedede/var/cappy2: Fix the DUT with cirrus codec PLT failSunwei Li
irq(ACPI_IRQ_LEVEL_LOW) -> ACPI_DESCRIPTOR_INTERRUPT -> IO-APIC, will assert interrupt frequently; irq_gpio(ACPI_GPIO_IRQ_EDGE_BOTH) -> ACPI_DESCRIPTOR_GPIO -> INT34C8; will not assert interrupt frequently; Because IRQ configuration can't be setted to both EDGE trigger. BUG=b:195635555 BRANCH=dedede TEST=Cirrus audio codec PLT pass Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I65bca519f75af84848284f039b6ad67cb1887823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56973 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16trogdor: Fix "TPM interrupt" lb_gpio to be ACTIVE_HIGHJulius Werner
"Latched" GPIOs like this one are a virtual representation of the pending interrupt flag for the edge-triggered pin and not a direct representation of line state, so they should always be marked ACTIVE_HIGH or depthcharge will incorrectly negate them. This has always been wrong and meant that depthcharge doesn't correctly wait for Cr50 flow control responses on these platforms. Thankfully it doesn't seem like we've seen any practical issues from this, but it's still very wrong. BRANCH=trogdor BUG=none TEST=Booted CoachZ (no visible difference) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie1586b0e10b64df0712e28552411c4d540a7e457 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-08-16mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD devicePatrick Huang
Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources. In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device. BUG=b:186384256 BRANCH=none TEST=Verify the config setting can update to the GPPCLKCONTROL registers. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/intel/adlrvp_m: Enable CR50 TPM support over SPIThejaswani Puta thejaswani.putta@intel.com
Add Kconfig options and enable TPM device in devicetree BUG=None TEST=Booted the image and checked the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com> Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-16mb/google/dedede: Create driblee variantFrank Wu
Create the driblee variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:191732473 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DRIBLEE Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-16mb/google/dedede: Create corori variantIan Feng
Create the corori variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:194356176 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CORORI Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56796 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/poppy/variants/atlas: stop setting touchscreen probed=1Matthew Blecker
All Atlas devices have the touchscreen controller, so probing for its presence is unnecessary. Removing the probe requirement allows the touchscreen ACPI device in Linux to re-enumerate when rebinding its I2C adapter device. Without this change, after rebinding the touchscreen's I2C adapter device using sysfs the touchscreen ACPI and HID devices are absent, and the touchscreen is unresponsive. With this change, the touchscreen ACPI and HID devices are re-created after rebinding its I2C adapter device, and the touchscreen becomes responsive again. BUG=b:177350937 TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds with Linux 4.4 and 5.4. Built new AP FW from Atlas Chrome OS firmware branch with this change applied. Tested shipping RO + new RW, and new RO + new RW. Test sequence: 1) Boot DUT, verify basic touchscreen functionality. 2) $ cd /sys/bus/platform/drivers/i2c_designware 3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002 drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1 4) $ echo i2c_designware.0 > unbind 5) Verify touchscreen is unresponsive (as expected after unbind). 6) $ ls -ld i2c_designware.0 ls: cannot access 'i2c_designware.0': No such file or directory 7) $ echo i2c_designware.0 > bind *** Without this change: *** 8) Touchscreen remains unresponsive. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}} ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6 *** With this change: *** 8) Touchscreen is functional again. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003 drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1 Signed-off-by: Matthew Blecker <matthewb@chromium.org> Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: Add I2C parameterEric Lai
Add I2C parameters to make sure each bus speed is around 390kHz. BUG=b:188793264 TEST=Measure by scope. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya/variants/kano: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: Configure EN_FCAM_PWR to highVarshit B Pandya
Recent change "7a8c68a: mb/google/brya: Configure H21 as GPO and A17 as low" turned EN_FCAM_PWR low since EN_FCAM_PWR is turned ON and OFF by IPU driver while MIPI UFC probing. However USB UFC also requires 3.3V which is enabled by A17. This caused USB UFC enumeration to fail BUG=b:196014678 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56882 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16Documentation/util/kconfig: Remove silentoldconfigYu-Ping Wu
The "silentoldconfig" target has been removed in Linux 5.13's kconfig (CB:37152). As explained by Michal Marek at https://lkml.org/lkml/2011/8/31/189, the "silentoldconfig" target has become an internal interface and "oldconfig" is just as silent now. Therefore, correct the target for syntax checking. Change-Id: I8416bd4a96d15415f46c591ceb26ebb29aef1ab0 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-08-16mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarityCasper Chang
modify reset_gpio as active low to meet touchscreen spec BUG=b:195490284 BRANCH=none TEST=build coreboot and touchscreen works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: allow MKBP devices and disable TBMC deviceBoris Mittelberg
Enable MKBP (Matrix Keyboard Protocol) interface for all Brya family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Brya P1: Volume Up/Down buttons Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/guybrush: Update GPIOs for fingerprint MCUMartin Roth
Add mainboard finalize and shutdown call to match zork. Deassert EN_PWR_FP in bootblock, power up correctly in finalize. | Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume | |-----------|--------------|-----------|----------------------| | Bootblock | **Low** | **Low** | Maintain High / High | | Romstage | Low | Low | Maintain High / High | | Ramstage | Low | **High** | Maintain High / High | | Finalize | **High** | High | | | Shutdown | **Low** | **Low** | | BUG=b:191694480 TEST=Build, verify GPIO configuration. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-16Documentation: Mark ECC as working on Sandy BridgePatrick Rudolph
Change-Id: I9f9aa5bf6ed4e1430e7067bfe5d3ce8e59e85812 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-16crossgcc: upgrade Expat from 2.2.9 to 2.4.1Mackenzie May
Versions of expat before 2.4.0 have been renamed to prevent their use, due to some kind of vulnerability. without updating this dependency it is currently not possible to build crossgcc with GDB. Change-Id: Iec2cf560902dc556a41206d7dcd65c22cf3e1215 Signed-off-by: Mackenzie May <ky0ko@disroot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56868 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16soc/intel/alderlake: Create eNEM Kconfig for Alder LakeSubrata Banik
Alder Lake SoC specific Kconfig that internally selects all eNEM related Kconfig. CONFIG_ALDERLAKE_CAR_ENHANCED_NEM will get autoselected if platform doesn't have INTEL_CAR_NEM Kconfig selected explicitly. BUG=b:168820083 TEST=Verified CONFIG_INTEL_CAR_NEM is still enable. Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS KconfigSubrata Banik
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000 BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode. Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enableSubrata Banik
As per TGL EDS doc:575681, two ways will be controlled with one bit of SF QoS register(SF Mask#1/#2) hence, selects SF_MASK_2WAYS_PER_BIT for TGL SoC. Change-Id: Ibeef653e0c510b62880b10b3f9767664d89c9623 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/common: Calculate and configure SF Mask 1Subrata Banik
MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates the maximum number of bits that may be set in any of the SF MASK register. Hence, this patch calculates SF way count using below logic: Calculate SF masks 1: 1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: a. SFWayCnt = SFWayCnt / 2 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - SF_MASK_2 Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/common: Calculate and configure SF Mask 2Subrata Banik
As per TGL EDS, two ways will be controlled with one bit of SF QoS register hence, this patch introduces SF_MASK_2WAYS_PER_BIT Kconfig to allow SoC users to select SF_MASK_2WAYS_PER_BIT to follow the EDS recommendation. Calculate SF masks 2: 1. if CONFIG_SF_MASK_2WAYS_PER_BIT: a. data_ways = data_ways / 2 Also, program SF Mask#2 using below logic: 2. Set SF_MASK_2 = (1 << data_ways) - 1 Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15mb/google/brya: set PL4 value dynamically for thermalSumeet Pawnikar
Set PL4 value dynamically for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I20b98ccd8493ed238de647cda8ceb25f62029133 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15mb/google/brya/{redrix,taeko}: Deduplicate lockdown configFelix Singer
Lockdown configuration is done in their baseboards. Thus, remove the setting from the variants overridetree. Change-Id: Iadb1201718466503987e4f6bd72bf711a2d3128e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-13mb/google/guybrush: Create nipperkin variantKarthikeyan Ramasubramanian
Create the nipperkin variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_NIPPERKIN Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie525ea501e6c3d5d94e67c1db1d4e307fb7ccba7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56921 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13soc/intel/tgl: Hook up ucode for TGL-U and TGL-RTim Crawford
Hook up microcode from 3rdparty repo for: - TGL-U: 06-8c-01 (CPUID signature: 0x806c1) - TGL-R: 06-8c-02 (CPUID signature: 0x806c2) Verified microcode blob was found in CBFS on system76/darp7 (TGL-U). CBFS: Found 'cpu_microcode_blob.bin' @0x103c0 size 0x31c00 in mcache @0x76c2d0ac microcode: sig=0x806c1 pf=0x80 revision=0x88 coreboot reports the correct revision for the microcode. Change-Id: I210c0133dad7ade63b9f7177aaa9a69b019469af Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56862 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-133rdparty/intel-microcode: Update submodule to 20210608 releaseTim Crawford
Update submodule pointer to include microcode for TGL and others. Tested the following still boot: - galp3-c (WHL-U): sig=0x806eb pf=0x80 revision=0xe9 - oryp5 (CFL-H): sig=0x906ea pf=0x20 revision=0xe9 - gaze15 (CML-H): sig=0xa0652 pf=0x20 revision=0xe9 coreboot reports the revision as -1 from what it actually is. i.e., these should report revision=0xea (and that is what Linux reports). However, this behavior is not new. Change-Id: I084ba67e8eaf7383f1c05fa5589b63c92ff900b1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56861 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13tests/Makefile.inc: Add missing include paths to TEST_CFLAGSJakub Czapiga
Add missing paths to common tests cflags and remove these paths from individual tests configuration. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I13cb336195bfb06b861d7f403822f06bec8a40aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13tests/Makefile.inc: Add copy-test macroJakub Czapiga
copy-test macro copies attributes from one test to another. It can be used to create multiple tests with the same subset of attributes values. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I9c9b6b12830c7060ffe5dcf35c9486655cbd08e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13tests/Makefile.inc: Change assignments to immediate and fix styleJakub Czapiga
Change assignments to be immediate instead of lazy. Add spaces between variable name and assignment operators to increase readability. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Idf07b5a836b33cd80c3533e582e2a1916a7bd45d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13mb/google/brya/variants/brya0: add PL4 values for different SKUsSumeet Pawnikar
Add PL4 values for brya0 board for different CPU SKUs. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-13mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5Ivy Jian
Tune the USB phy settings to update TXVREFTUNE0/COMPDISTUNE0 to higher value for USB port 5 (Type-A). BUG=b:194053549 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56925 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKUMeera Ravindranath
DDR5 Maple Ridge SKU (Board ID 0x16) uses a Memory down DIMM configuration. TEST=Boot DDR5 MR SKU to OS. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56881 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13util/mb/google: add template files for guybrushBhanu Prakash Maiya
Create template for guyrbsuh variant creation. BRANCH=none BUG=b:194031783 TEST=n/a Change-Id: If62c1a63d0890539d4b43f840f75ee9d7ceab4f8 Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13mb/intel/adlrvp: Rename spd_info struct based on memory topologyMeera Ravindranath
Naming spd_info struct based on memory topology helps in reuse of code. lp4_lp5_spd_info -> memory_down_spd_info ddr4_ddr5_spd_info -> dimm_module_spd_info Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7a66b5524d8b80776ab7578ce7b13181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-08-13mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram optionNico Huber
Change-Id: I8c5d6686bf7c694f9d594e3801c79cfd7fb3da80 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56342 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/google/dedede: allow MKBP devices and disable TBMC deviceBoris Mittelberg
Enable MKBP (Matrix Keyboard Protocol) interface for all dedede family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Madoo: Volume Up/Down and Power buttons, Tablet Mode switch Cq-Depend: chromium:3069163 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I9d1f43e4dd56318af4c1d5f5c1c3a2c237a05c5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56840 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/intel/adlrvp: Use HDA TMODE 8T to match spec for ADL P RVPSathya Prakash M R
With current setting Display audio codec probe fails. Hence HDMI/DP audio fails. Earlier, with FSP 2037 was used the mode was incorrectly programmed to 4T This setting was carried ahead with below change: Commit : 50f8b4ebdd7db8077b87ab7686637599c9d93af3 The issue was fixed in later FSPs and with current FSP v2237, we need to set the TMODE to 8T as per spec. TEST=Verify HDMI/DP Playback on ADL P RVP Fixes: 50f8b4ebdd7db8077b87ab7686637599c9d93af3 (soc/intel/alderlake: Add enum for HDA audio configuration) Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56208 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/alderlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/jasperlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/tigerlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/skylake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-clause and adjust comments. This changes behavior since now related options are always set, depending on if coreboot or the FSP should be responsible for the chipset lockdown. This ensures a defined state independent from the default configuration of the FSP. Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/cannonlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause and adjust comments. Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
This patch configures the SKU specific power delivery parameters for the VR domains. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADLV Sowmya
This patch updates the VccIn Aux Imon IccMax for ADL-P to SOC SKU specific values from the FSP default value 160. * ADL-P 682(45W) = 137. * ADL-P 482(28W) = 128. * ADL-P 282(15W) = 128. These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56176 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/apollolake: add 4Gb and 6Gb dram densityJamie Chen
This patch adds 4gb and 6gb dram density support to APL and GLK. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: Ic0d5d14f26a30da7a9caf4ef43d7fac88a4d2bf1 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55153 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/apollolake: change LPDDR4 density enum definitionJamie Chen
Originally we use rank_density=0 to mean disable the channel, but actually rank_density=0 means 4Gb density in the FSP. This patch changes the LPDDR4 enum values to the real density number and adds a switch statement to mapping the density define in the FSP. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: I36dba2cef130211e7aea9e2a4f82c5db78f82a83 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56805 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/system76/*: Add CMOS option tableTim Crawford
System76 uses several custom CMOS values downstream. Reduce our diff by providing a generic layout with the defaults: boot_option=Fallback debug_level=Debug power_on_after_fail=Enable Tested on galp3-c, gaze15, oryp5, oryp6. All boards boot multiple times with USE_OPTION_TABLE selected. Change-Id: Ie57b0e5713bba8ad46e1a4123a3ddd43e0eea964 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-08-12soc/mediatek/mt8192: move DFD driver to common folderRex-BC Chen
Move DFD driver to common folder so MT8195 can also use it. BUG=b:192429713 TEST=emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7937cddf5f3a66f9269a94301d3134e6f4f9f22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore settingRyan Chuang
Remove the unnecessary Vcore setting for the DVFS feature. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If3c28e57a559a7ec04319c1a489138817e44ec4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12soc/mediatek: revise the dependency of DVFS config optionsRex-BC Chen
The MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT only makes sense if DVFS is enabled (e.g., MEDIATEK_DRAM_DVFS) so we should change it to depend on that instead of selecting DVFS. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib81e4e48e863616ed1e36cd5c0000f4e2cfb5456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12drivers/generic/alc1015: Add HID to support alc1019Eric Lai
ALC1019 will use the ACPI compatible and share the same driver with ALC1015. Add HID to support more compatible ICs. BUG=b:195891240 TEST=ALC1019P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3e98297f3a39048b24d61e61ca95c60cd2037eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-12libpayload: Mark Intel 300 series AHCI as testedNico Huber
Tested with filo on roda/rw14. Change-Id: Ia5f868d3a9cead0a872e6d3e9fdacd6eeb7f158b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56666 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12MAINTAINERS: Add Maxim Polyakov as intelp2m maintainerMaxim Polyakov
Change-Id: I85835712926ca456b108b1d80e6a55f75e604591 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-12mb/google/dedede/var/galtic: Add charger throttling functionFrankChu
Add charger current throttling support for galtic control charger index * 64 = Value mA 32*64=2048 28*64=1792 24*64=1536 20*64=1280 BUG=b:187231627 TEST=Built and tested on boten system Cq-Depend: chrome-internal:3846209 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I5e1849551ff051bca591f19f9e40da4c89ab74e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-08-12mb/google/dedede/variants/haboki: add discrete TPM in overridetreeWisley Chen
Haboki is project which use discrete TPM, so add discrete TPM and disable cr50 in overrideree. BUG=b:187094464 TEST=FW_NAME=haboki emerge-keeby coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I08f2a562c3f62c60402350151ea260b70890a744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-12soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-STim Crawford
Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. TGL also introduces parameters for customizing the default SVID:SSID. These must be set or it will still use the FSP defaults. Tested by checking lspci output on System76 darp7 (TGL-U). References: - b1fa231d76a ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S") - TigerLake FSP Integration Guide - Intel Document #631120-001 Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-12mb/google/brya/variants/redrix: enable LTE PCIe portWisley Chen
Enable LTE PCIe port according to fw config. BUG=b:192052098 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ic9472d2249c622858a75c63bc82e8e4e8166a3d7 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56894 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/brya/variants/redrix: add mipi camera supportWisley Chen
Add mipi camera support by selecting the Kconfig symbols and adding it to the devicetree with ACPI UID 0x50000 and name IPU0. BUG=b:192052098 TEST=checked mipi camera works Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I69281f36ddbc1abf9905c8db9287500f9aa995c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56893 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/brya/variants/gimble: Update GPIO for PP1800 DMIC enableMark Hsieh
add GPP_D16 in gimle gpio.c and set value to 1 for PP1800 DMIC init sequence BUG=b:195968649 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ia0639162e2c3f02f622470fa16c21fe8a067cf7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56889 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12MAINTAINERS: Add Tim Crawford as a maintainer for System76Tim Crawford
Change-Id: I8aa9ee1627bf319660b193b4602d8c2d0b562424 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52580 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/trogdor: Add new variant WormdinglerZanxi Chen
New board introduced to trogdor family. BUG=b:193870279 BRANCH=none TEST=make Change-Id: If3d9662e8725e30e1308d77b05545efbee29f846 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-08-11mb/google/brya/variant/taeko: Update devicetree settingsJoey Peng
Based on schematic and gpio table of taeko, generate overridetree.cb settings for taeko. BUG=b:195494281 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-11soc/intel/alderlake: Implement report_cache_info() functionSubrata Banik
Make use of deterministic cache helper functions from Alder Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384 Cache size = 12 MiB Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-11arch/x86: smbios write 7 table using deterministic cache functionsSubrata Banik
This patch makes use of deterministic cache helper functions, for example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper functions from arch/x86/cpu_common.c file. Also, changed argument for get_number_of_caches() function that receives cpu_get_max_cache_share() data directly. Drop unused variables partitions, cache_line_size and number_of_sets as struct cpu_cache_info.size would provide the cache size directly. TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output. Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0005, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 288 kB Maximum Size: 288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Data Associativity: 12-way Set-associative Handle 0x0006, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 192 kB Maximum Size: 192 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Instruction Associativity: 8-way Set-associative Handle 0x0007, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE2 Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Unknown Location: Internal Installed Size: 1280 kB Maximum Size: 1280 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: Unknown Handle 0x0008, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE3 Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 12288 kB Maximum Size: 12288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: 12-way Set-associative Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-11arch/x86: Helper functions to get deterministic cache parametersSubrata Banik
This patch creates helper function that internally detects the CPU type (AMD or Intel) and pick the leaf to send CPUID instruction with different cache level to retrieve deterministic cache parameters. Lists of helper functions generated as part of this CL : 1. cpu_check_deterministic_cache_cpuid_supported => if CPU has support for deterministic cache using CPUID instruction. 2. cpu_get_cache_ways_assoc_info => Get cache ways for associativity. 3. cpu_get_cache_type => Get cache type. 4. cpu_get_cache_level => Get cache level. 5. cpu_get_cache_phy_partition_info => Get cache physical partitions. 6. cpu_get_cache_line_size => Get cache line size. 7. cpu_get_cache_sets => Get cache number of sets. 8. cpu_is_cache_full_assoc => Check if cache is fully associative. 9. cpu_get_max_cache_share => Cores are sharing this cache. 10. get_cache_size => Calculate the cache size. 11. fill_cpu_cache_info => Fill cpu_cache_info structure. Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-10mb/google/dedede/var/cret: Fix DPTF passive and critical policiesDtrain Hsu
TSR2 thermal sensor doesn't define in cret. Fix DPTF passive and critical policies for getting negative temperatures in OS. BUG=b:195868075 BRANCH=dedede TEST=Build and boot to OS in cret. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I849662cbb3adc8e528d65af2c90e7c8e4880d607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-10mb/intel/adlrvp: create dynamic power limits mechanism for thermalSumeet Pawnikar
Add dynamic power limits selection mechanism for aldrvp board. BUG=None BRANCH=None TEST=Build FW and test on adlrvp with DPTF tool On adlrvp (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (55000, 55000) On adlrvp (682): Overriding DPTF power limits PL1 (5000, 45000) PL2 (115000, 115000) Change-Id: Id1aef0125c6e1e105665172f19bda271e232d94f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-10mb/google/brya/variants/primus: Remove DPTF fan controlScott Chao
BUG=b:195901486, b:195387997 BRANCH=none TEST=Check fan is able to control by EC Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If758d75ff24c88c9eaf0de90ac0ef08d172a2edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56879 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-10mb/system76/oryp6: Enable TAS5825M smart ampTim Crawford
Allows using the internal speakers of the oryp6. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I57781a7223a52b8fc5295cf686412926529c3a7f Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-10mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-10mb/*/brya/adlrvp: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-10mb/google/hatch/scout: Update DPTF parametersKenneth Chan
update the DPTF parameters received from the thermal team. BUG=b:195602767 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I5dc89d1d4c2b64c9aac780a7db743a91fd0ebc9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jeff Chase <jnchase@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-10mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codecSunwei Li
Compatible headphone codec "Realtek ALC5682I-VD" and "cirrus CS42L42" Compatible AMP codec "ALC1015Q-VB" and "MAX98360" BUG=b:193373320 BRANCH=dedede TEST=Both realtek and cirrus audio codec can work normally Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I9121e75eaf46b43e6dc5ef2e31029a153c7a807d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-10mb/google/brya/variant/taeko: Update memory settingsJoey Peng
Based on the Taeko's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4e23c28aaf20d9e52b43033b4e41c751e26872bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09mb/google/dedede/var/storo: Fixed iasl can not run on DutTao Xia
The TSR1._PSV has been redefined. It will report errors when disassembling the ACPI tables with the iasl. It is OK when Removing the TSR1._PSV and adding the TSR0._PSV BUG=b:194509417 BRANCH=dedede TEST=The iasl can run on Dut successfully Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I524255c79d3c71573d122944da5058389f79d95d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-08-09mb/intel/adlrvp: Support VBT binaries for LP4 and LP5Bernardo Perez Priego
This will enable to include multiple VBT binaries in a single image and load corresponding file according to HW configuration. BUG=None TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iace0e5e0783b2074393a537da8cc645102d2acda Reviewed-on: https://review.coreboot.org/c/coreboot/+/55969 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe SlotAamir Bohra
Keep the clock source for PCIe slots as always on. Also turn off the unused (0/1/5/6) clock sources. Currently bilby only uses clock sources 2, 3 and 4, out of which clock source 3 and 4 are routed for PCIe external slot. And clock source 2 is routed for M.2 PCIe slot. TEST:Verify end devices enumerate on D:F 1.1/1.2 RPs over warm reboot. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: Ida485b06279b0a8659c8d00873c3d6023d1e542f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56826 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09util/spd_tools/lp4x: Update READMETim Wawrzynczak
The lp4x spd_tools also support Alder Lake (ADL), so update the the README to reflect this fact. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iedb1ea1c3558e5f179feac2c725667db5b327b2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09tests/Makefile.inc: Add function wrapping mechanismJakub Czapiga
This patch extends mocks functionality to allowing wrapping of mocked functions. Original function name will be prefixed with `__real_`. Example: - Mocked function: cbfs_lookup() - New function name: __real_cbfs_lookup() - Mock name: cbfs_lookup() Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I7cd0d66a17029955cbf75c8b155a7ebb7f5513aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56719 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/google/brya/variants/taeko: Configure GPIOs according to schematicsJoey Peng
Update initial gpio configuration for taeko BUG=b:195252436 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09mb/google/brya/variants/brya0: set power limits for thermalSumeet Pawnikar
Set power limits for brya0 variant board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 variant board with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I4c07319af756b10e5d22f320e97ff956fb4a14c6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56622 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09gimble: enable elan touchscreenScott Chao
Enable Elan touchscreen and remove Goodix touchscreen. We also get confirmation by Elan that address is 0x15. BUG=b:195494292 BRANCH=none TEST=build coreboot and dmesg | grep hid, it showed i2c-ELAN9050:00. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I20a7fd0b370803c14990b77bab302727af197ccb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56801 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4Tim Wawrzynczak
The code is clearer when ACPI_DEVICE_SLEEP_D3_COLD is used instead of the number 4. Change-Id: I4b0ade1cd0b4b9cdb59f90f8d455269d0b69ed86 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/uart/acpi: Update _S0W return value to D3hotTim Wawrzynczak
In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most UARTs that do have wake capabilities support wake from D3hot rather than D3cold. BUG=b:187228954 TEST=compile Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/spi/acpi: Update _S0W return value to D3hotTim Wawrzynczak
In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most SPI peripherals that do have wake capabilities support wake from D3hot rather than D3cold. This also allows coreboot to expose a power resource to perform power sequencing for a SPI peripheral that is intended to retain power in S3/S0ix. If support for a device with d3cold wake support is needed, it could be added in later as an option. BUG=b:187228954 TEST=compile Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/i2c/da7219: Update _S0W to D3hotTim Wawrzynczak
The DA7219 does not support wake from D3cold, therefore update the return value of _S0W from D3cold to D3hot. BUG=b:187228954 TEST=compile Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09mb/google/brya: create dynamic power limits mechanism for thermalSumeet Pawnikar
Add dynamic power limits selection mechanism for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09elogtool: add to gitignoreJack Rosenthal
Add the binary output of the new elogtool to the .gitignore, so that running "make -C util/cbfstool" keeps the tree clean. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I806338a4b33abbc3d55e4edef2736c19d56fa005 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Quesada <ricardoq@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09mb/system76/oryp6: Drop DIMM_SPD_SIZETim Crawford
The board uses the default size specified in the SoC. Change-Id: Ie71a0fea1ff9de6c4f1ce8db2db09bb3cd35d04d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-08-09MAINTAINERS: Add System76 as maintainer for TAS5825MTim Crawford
Change-Id: I302e408fa9479e7fc03f344f092e145dd2b86ba5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52581 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-09soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpusMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will always be 0 but as per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, it says that BSP can be any processor whose index/APIC ID might not be 0. To handle this situation, init_cpu call is required to modify to handle dynamic detection of APIC ID from BSP instead of hardcoding always through devicetree. Function has been updated to create a new node with actual BSP APIC ID when devicetree doesn't contain APIC ID defined. In case APID ID is defined, function will use a node with the APIC ID defined in devicetree. Changes also requires to remove "lapic 0" hardcoding from devicetree to allow code to fill BSP APIC ID dynamically. Otherwise coreboot will create an extra node for CPU with APIC ID 0 and it'll show as a extra node in kernel. This will cause kernel to report wrong (extra) core count information then actually present. BUG=None BRANCH=None TEST=Boot the JSL system and observe there is no functional impacts. Without this CL kernel core count in `lscpu` = 3 With this CL, kernel core count is corrected to 2. Change-Id: Ib14a5c31b3afb0d773284c684bd1994a78b94445 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/ORyan Chuang
Disable reading of vdram/vddq/vmddr to reduce access of I2C to reduce DRAM init time by about 30ms. The values were only needed by HQA report and not needed on production units. BUG=b:195274787 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I32cd68fb8b52cec6e145d6772475fde0130ca6ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/56850 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency countRyan Chuang
Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM frequency counts to reduce DRAM initialization time by about 100ms. BUG=b:195274787 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09payloads/libpayload: add MTK_TIMER_V2 configRex-BC Chen
The timer structure (in particular, the offset to memory addresses) on recent MTK SoCs for example MT8195 has been changed. BUG=b:195274787 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifd6ff65a825c4309c47f3b115b80a8ecd42fedac Reviewed-on: https://review.coreboot.org/c/coreboot/+/56845 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/google/cherry: Improve boot time by raising little CPU frequencyRex-BC Chen
Raise little CPU to 2GHz at romstage to improve boot time by about 100 ms. BUG=b:195274787 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Id6aac8f9db86a6c1e61ea94863f2cbde12c0482e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 14:58:56 +0000