diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-08-09 16:06:21 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-13 18:04:02 +0000 |
| commit | bcc74afa73609f1555fca146196ef3179ae841f4 (patch) | |
| tree | 14feae3e8545d28977c1e76a24df540a281d5e68 | |
| parent | adc9e63c59829dba78888914c740a7dbf073508d (diff) | |
mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU
DDR5 Maple Ridge SKU (Board ID 0x16) uses a Memory down DIMM
configuration.
TEST=Boot DDR5 MR SKU to OS.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56881
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/spd/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex | 32 |
3 files changed, 34 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 5241f960a6..34fc04e6cb 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -53,9 +53,9 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) case ADL_P_DDR4_1: case ADL_P_DDR4_2: case ADL_P_DDR5_1: - case ADL_P_DDR5_2: memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); break; + case ADL_P_DDR5_2: case ADL_P_LP4_1: case ADL_P_LP4_2: case ADL_P_LP5_1: diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 5c5c1b4e72..4cb0f98da1 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -6,5 +6,5 @@ SPD_SOURCES += adlrvp_m_lp5 # 0b002 SPD_SOURCES += adlrvp_lp5 # 0b003 SPD_SOURCES += empty # 0b004 SPD_SOURCES += empty # 0b005 -SPD_SOURCES += empty # 0b006 +SPD_SOURCES += adlrvp_ddr5_mr # 0b006 SPD_SOURCES += adlrvp_lp5 # 0b007 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex new file mode 100644 index 0000000000..80ef521cfa --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex @@ -0,0 +1,32 @@ +30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00 +00 00 00 00 A1 01 E8 03 72 15 00 00 00 00 1E 41 +1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 AE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +08 00 C2 C4 80 00 80 B3 80 11 00 00 00 00 00 00 +00 00 80 B3 80 11 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 0F 10 00 01 01 22 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C AD +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |