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2023-04-11soc/amd/mendocino: Lower log level for TDP value to DEBUGPaul Menzel
Printing the value of a variable is not informative for a normal user, so decrease the value from BIOS_INFO to BIOS_DEBUG. Fixes: b9caac74a320 ("soc/amd/mendocino: Reinterpret smu_power_and_thm_limit") Change-Id: I22f6293fd47633dfdbdae37b7257f47a5a4bb29c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-04-11soc/intel/xeon_sp/acpi: Fix _OSC methodPatrick Rudolph
Fix a couple of bugs in the _OSC method for handling "PCI Host Bridge Device" on Xeon-SP. - Drop the Sleep. The code doesn't write to hardware at all, so there's no need to sleep here. - Make sure that the number of DWORD passed in Arg2 is at least 3. The existing check was useless as it would not create the DWordField, but then use it anyways. - Add check for CXL 2 device method calls which provide a 5 DWORD long buffer to prevent buffer overflows when invoking the "PCI Host Bridge Device" method. Test: Boot on Archer City and confirm that no ACPI errors are reported for _OSC. Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-04-11soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-SMichał Żygowski
According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11mb/siemens/mc_ehl2: Fix GPIO settings for latest HW revisionMario Scheithauer
With the latest hardware revision, the two GPIOs GPD11 and GPP_C8 are no longer used. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: Ia06f93aee4eccb0e4230f0c3ef53922d42701f21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74201 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-11util/sconfig: Remove unused ioapic and irq keywordsArthur Heymans
Ioapic information in the devicetree was only used to set up mptables but this generic driver was removed (ca5a793 drivers/generic/ioapic: Drop poor implementation). This removes the unused remainders from mainboard devicetrees. Remove ioapic setup from sconfig. Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11drivers/fsp2_0/mp_service_ppi: Use struct device to fill in bufferArthur Heymans
Now the CPU topology is filled in struct device during mp_init. Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11mb/google/skyrim: Enable UPD usb3_port_force_gen1 for MarkarthJohn Su
From request, all type C port limit to to Gen1 5GHz. So enable UPD usb3_port_force_gen1 for Markarth. BUG=b:273841155 BRANCH=skyrim TEST=Build, verify the setting will be applied on Markarth. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I9314b67a82ad2993c87f0110db5ec927caaa772b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74087 Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11mb/google/brya/variants/hades: Update GPU power sequencing to add Hades supportTarun Tuli
Add GPU power sequencing changes for the Hades baseboard and variant. Some signals were added, moved or inverted. Based on implementation from Agah. Moved signals: GPIO_1V8_PWR_EN GPP_E11 GPIO_NV33_PWR_EN GPP_E2 GPIO_NV33_PG GPP_E1 New signals: GPIO_NV12_PWR_EN GPP_D0 GPIO_NV12_PG GPP_D1 Inverted signals: GPIO_FBVDD_PWR_EN GPP_A19 ifdef's will be dropped once the Agah variant is retired. BUG=b:269371363 TEST=builds and verified on Agah that DGPU is still detectable (lspci) Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-11mb/lenovo/x200: Read EDID in mainboard_vbt_filename()Bill XIE
mainboard_vbt_filename() used to assume that it is called after a call to get_blc_pwm_freq_value() with a valid parameter, but currently it is the first call of get_blc_pwm_freq_value(NULL), and will return 0, so "data_led.vbt" is always returned, regardless of the actual type of the panel. Combined with the previous commit, in this commit mainboard_vbt_filename() will explicitly read EDID string via gm45_get_lvds_edid_str() and use this string to call get_blc_pwm_freq_value(). Resolves: https://ticket.coreboot.org/issues/475 Tested on my x200s with LTD121EQ3B (LED), and x200 with LTD121EWVB (CCFL). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74181 Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-11mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the Rex debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4ab69eb24937d58c8bc5d3c0a6e5cb70b843a1ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the MTLRVP flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/google/rex: Update Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the Rex flash layout to optimize WP_RO to 4MB. The idea is to create more space inside FW_RW_A/B to accommodate multiple blobs to boot google/rex with different Intel MTL SoC stepping. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74229 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-11soc/intel/{adl, cmn}: Send CSE EOP Async CMD earlySubrata Banik
This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample whichcauses idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/marasov EVT sku to ChromeOS and observed ~30ms of boot time savings (across warm and cold reset scenarios). Without this patch: 963:returning from FspMultiPhaseSiInit 907,326 (97,293) ... ... 115:finished elog init 967,343 (2,581) 942:before sending EOP to ME              967,821 (478) …  16:finished LZMA decompress (ignore for x86)    1,017,937 (12,135) 943:after sending EOP to ME                     1,067,799 (49,861) … … 1101:jumping to kernel                          1,144,587 (13,734) Total Time: 1,144,549 With this patch: 963:returning from FspMultiPhaseSiInit 918,291 (97,320) 942:before sending EOP to ME                    918,522 (230)   ... ... 16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483)   943:after sending EOP to ME                     1,033,456 (3,980)   ... ...   1101:jumping to kernel                          1,111,410 (14,007) Total Time: 1,111,375 Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-11mb/intel/mtlrvp: Enable PCIe port 6 and RTD3 support for x1 slotCliff Huang
This change enables PCIe x1 slot. In addition, it turns off 3.3v and 12v power and assert PERST# when suspend and turn on the power and deassert the PERST# when resume for the x1 slot. NOTE: Kconfig flag and required GPIO pins are already configured. - /soc/intel/meteorlake/Kconfig select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 - gpio.c: /* GPP_A18: X1_PCIE_SLOT3_PWR_EN */ PAD_CFG_GPO(GPP_A18, 1, DEEP), /* GPP_A19: X1_DT_PCIE_RST_N */ /* SRCCLKREQ: GPP_C12: SRCCLKREQ3_GEN4_X1_DT_SLOT3_N */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), BUG=b:224325352 BRANCH=None TEST=Insert a SD card or NIC AIC on PCIe x1 slot and the AIC should be detected and enabled at boot. For S0ix, run 'suspend_stress_test -c 1'. The RP6 should not cause any suspend and resume issue. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Id2e92acf754569a22ea76a68c91aafce0075a742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73054 Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/amd/common/blk/pcie: Program LTR max latenciesMatt DeVillier
PCIe bridges need to provide the LTR (latency tolerance reporting) maximum snoop/non-snoop values so that they are inherited by downstream PCIe devices which support and enable LTR. Without this, downstream devices cannot have LTR enabled, which is a requirement for supporting PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior, including some devices refusing to enter L1 low power modes at all. Program the max snoop/non-snoop latency values for all PCIe bridges using the same value used by AGESA/FSP, 1.049ms. BUG=b:265890321 TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure LTR is enabled, latency values are correctly set, and that device power draw at idle is in the expected range (<25 mW). Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74288 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-10mb/google/sarien: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. TEST=build/boot Windows/linux on drallion, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I3b91a628cd4a9edb5d5a7521529f39b75935e1d0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
Ensure the GPIOs themselves are configured as level triggered, as well as the devicetree entiures. I2C-HID spec requires LEVEL trigger, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE trigger. TEST=tested with rest of patch train Change-Id: I4fba55c938f401876798c2b32c5922523f32180f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/sarien: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on sarien, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I3ce7bfc0fa4c03c0bb96bebaa3c3d256f886ecc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/sarien: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set. TEST=tested with rest of patch train Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/brya: Compile gpio.c in SMM when neededMatt DeVillier
Without gpio.c compiled in, SMMSTORE will fail to initialize and hang. Add a conditional inclusion so gpio.c is compiled in SMM when SMMSTORE is selected. TEST=build/boot google/banshee with SMMSTORE support enabled Change-Id: If049cba98f13f060807058029306dcad2ada2d49 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-10mb/google/poppy/var/nami: Fix stylus runtime detectionMatt DeVillier
Stylus reset GPIO needs to be held low in romstage, released in ramstage for runtime i2c detection to pick it up. TEST=build/boot AKALI360 variant, verify stylus detected in cbmem, functional in OS. Change-Id: I2e7f2a28f6b3a71b0c8fc367168cffbe3f064663 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-10mb/google/fizz/var/fizz: update VBTMatt DeVillier
Deselect the 'fixed resolution at boot' and 'eFP attached' options via the Windows BMP tool. Fixes HDMI audio output under Windows 10/11. TEST=build/boot Win 11 on Fizz, verify HDMI audio now functional. Change-Id: Iecede735bc1266af837e791e6c024aec2f9a8a80 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74235 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10security/tpm: make usage of PCRs configurable via KconfigSergii Dmytruk
At this moment, only GBB flags are moved from PCR-0 to PCR-1 when vboot-compatibility is not enabled. Change-Id: Ib3a192d902072f6f8d415c2952a36522b5bf09f9 Ticket: https://ticket.coreboot.org/issues/424 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-04-10mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C portDtrain Hsu
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. BUG=b:277149723 BRANCH=firmware-brya-14505.B TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u2 disabled Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ron Lee <ron.lee@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-10soc/mediatek/mt8188: Set pin drive strength to 8mA for NORJason Chen
Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.8 and 5.19 in MT8188 Functional Specification. BUG=b:270911452 TEST=boot with following logs [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74064 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Add GPIO driving functionsJason Chen
Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.2 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74063 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8186: Move GPIO driving-related functions to commonJason Chen
Move GPIO driving-related functions to common for code reuse. BUG=b:270911452 TEST=build pass Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74068 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8186: Reduce GPIO code size in bootblockJason Chen
Create a new GPIO driving info table that contains only the pins used in the bootblock. The GPIO driving info table is downsized from 1480 bytes to 24 bytes. BUG=b:270911452 TEST=build pass Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74062 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytesYidi Lin
Original lastbus configuration consumes constant memory size by allocating 16 and 8 members arrays and the utilization is bad. Refactor the lastbus structs to save memory usage. BRANCH=none BUG=none TEST=bootblock.raw.bin size is reduced from 60328 bytes to 59048 bytes. Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74061 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/geralt: Power on Samsung ATNA33XC20 eDP panelJianeng Ceng
Geralt uses Samsung panel, and Mutto is responsible for bonding the panel and touch, so rename the panel description. Add power-on sequence for Samsung ATNA33XC20 panel. EDID Info: header: 00 ff ff ff ff ff ff 00 serial number: 4c 83 62 41 00 00 00 00 28 1e version: 01 04 basic params: b5 1d 11 78 02 chroma info: 0c f1 ae 52 3c b9 23 0c 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 35 36 80 a0 70 38 20 40 30 20 88 00 26 a5 10 00 00 1b descriptor 2: 35 36 80 a0 70 38 20 40 30 20 88 00 26 a5 10 00 00 1b descriptor 3: 00 00 00 0f 00 d1 09 3c d1 09 3c 28 80 00 00 00 00 00 descriptor 4: 00 00 00 fe 00 41 54 4e 41 33 33 58 43 32 30 2d 30 20 extensions: 01 checksum: 6f BUG=b:276097739 TEST=test firmware display pass. Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74115 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/myst: Build for chromeOSJon Murphy
Adjust build configs to build Myst for chromeOS. BUG=b:270618097 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If4b6917fe024067409bfbb3d2691c37759b5cace Reviewed-on: https://review.coreboot.org/c/coreboot/+/74097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-10mb/google/brya/var/marasov: Configure Acoustic noise mitigationFrank Chu
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:271788117 TEST=build FW and system power on. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2023-04-10mb/google/myst: Declare CrOS GPIOsJon Murphy
Declare CrOS GPIOs for Myst, add relevant defines needed by chromeOS for additional control GPIOs. BUG=b:270616013 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie876883d6ee2e3bc6324c038cefee12d99702dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74096 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/myst: First pass GPIO configuration for MystJon Murphy
Initial GPIO configuration for Myst. BUG=b:270596581 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74095 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/myst: Add stubs to configure GPIOsJon Murphy
Add configuration stubs for GPIOs to be implemented later. BUG=b:270596581 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I3228f857da7c8c76cf32faf4a23418aedaf40875 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74094 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-10mb/google/myst: Add new mainboardJon Murphy
Myst is a new Google mainboard with an AMD Phoenix SOC. BUG=b:270596106 TEST=util/abuild/abuild -t GOOGLE_MYST --clean Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74093 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-08ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .backlight_enable = 0x01, ^~~~ /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .dock_event_enable = 0x01, ^~~~ Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-08sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .c4onc3_enable = 1, ^ /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .p_cnt_throttling_supported = 1, ^ Change-Id: I691b51a97b359655c406bff28ee6562636d11015 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-08sb/intel/i82371eb/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: CC romstage/mainboard/emulation/qemu-i440fx/static.o build/mainboard/emulation/qemu-i440fx/static.c:31:17: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .ide0_enable = 1, ^ build/mainboard/emulation/qemu-i440fx/static.c:32:17: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .ide1_enable = 1, ^ Change-Id: I36cc19bc2908119fe940941e108ee217a7b26f50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-07Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS"Arthur Heymans
This reverts commit 89b4f69746ac215e4a7c5f204d1ea807b4ea08b5. SI_BIOS is mostly used to indicate the BIOS region in Intel IFD. Not all platforms are Intel platforms with an IFD, so revert this change. Also tooling often depends on names not changing so renaming things should not be done lightly. The default region should also be in sync with non-x86 and made systematic across the tree. Change-Id: I46f52494498295ba5e2a23d0b66b56f266293050 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74290 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-04-07soc/intel/common: Order the different types of cores based on APIC IDsSridhar Siricilla
Currently coreboot presents the BSP core first, then efficient cores and Performance cores as indicated below: ``` /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4 /sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5 /sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6 /sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7 /sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3 ``` Existing code presents mix of different cores to OS and causes CPU load balancing and power/performance impact. So, the patch fixes this disorder by ordering the Performance cores first, compute die efficient cores next, and finally SOC efficient cores if they are present. This is done to run the media applications in a power efficient manner, please refer the ChromeOS patches for details: https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893 BUG=b:262886449 TEST=Verified the code on Rex system After the fix: ``` /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4 /sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5 /sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6 /sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7 ``` Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-04-07mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-07soc/intel/cmn/cse: Handle EOP completion asynchronouslyJeremy Compostella
coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. This patch also introduces a new code logic to detect if CSE is in the right state to handle the EOP command. Otherwise, it uses the prescribed method to make the CSE function disable. The typical scenario is the ChromeOS recovery boot where CSE stays in RO partition and therefore EOP command should be avoided. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [INFO ] HECI: coreboot in recovery mode; found CSE in expected SOFT TEMP DISABLE state, skipping EOP [INFO ] Disabling Heci using PMC IPC [WARN ] HECI: CSE device 16.0 is hidden [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06tree: Replace `egrep` with `grep -E`Felix Singer
For compatibility reasons, egrep is just a wrapper around grep today. Thus, replace it with `grep -E`. Change-Id: Ief08a22e4cd7211a3fee278492c95d37f9e058fa Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-06soc/intel/meteorlake: Perform feature control lockSubrata Banik
This function calls into `set_feature_ctrl_lock()` to lock IA32_FEATURE_CONTROL MSRfeature control. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Enable VMX using coreboot CPU feature programSubrata Banik
This function calls into `set_feature_ctrl_vmx_arg()` to enable VMX for virtualization if not done by FSP (based on DROP_CPU_FEATURE_PROGRAM_IN_FSP config is enabled) in MeteorLake SoC based platform. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Set AES-NI LockSubrata Banik
This function performs locking of the AES-NI enablement state. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Disable 3-strike errorSubrata Banik
This patch calls into API to disable 3-strike error on Meteor Lake SoC based platform. TEST=Able to build and boot google/rex to ChromeOS. Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled ``` localhost ~ # iotools rdmsr 0 0x1a4 0x0000000000000900 ``` Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06soc/intel/meteorlake: Allow to drop redundant CPU feature programmingSubrata Banik
This patch introduces a new config named `DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU feature programming on BSP and on APs using the "CpuFeaturesPei.efi" module. Most of this feature programming is getting performed today in scope of coreboot doing MP Init. Running this redundant programming in scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) results in CPU exception (for example: attempting to reprogram CPU feature lock MSR is causing CPU exception). SoC users should select this config after dropping "CpuFeaturesPei.ffs" module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional feature programming on BSP and APs. This feature is by default enabled, in case of "coreboot running MP init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected. At present, this option does not do anything unless any platform eventually decides to drop FSP feature programming module and choose coreboot CPU feature programming over it. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06soc/intel/cmn/cpu: Add function to disable 3-strike CATERRSubrata Banik
In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a 3-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. This patch prevents the Three Strike Counter from incrementing (as per Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-06amd/mendocino/root_complex: Restrict DPTC to 15W boardsTim Van Patten
Restrict DPTC to 15W boards, since we only have 15W values defined in the devicetree. This will revert the 6W boards back to their default values, rather than (incorrectly) configuring them with 15W values. BUG=b:253301653 TEST=Verify DPTC values are set for 15W boards TEST=Verify DPTC values are set not set for 6W boards Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74127 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06soc/amd/mendocino: Reinterpret smu_power_and_thm_limitTim Van Patten
The FSP will return the TDP in the format 0xX0000, where 'X' is the value we're interested in. For example: 0xF0000 (15W), 0x60000 (6W). Re-interpret the value so the caller just sees the TDP directly, without needing to re-interpret things themselves. BUG=b:253301653 TEST=Manually verify value is correct Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74126 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/x86/topology: Add code to fill in topology on struct pathArthur Heymans
This is needed to generate MADT and SRAT where lapicid for threads need to be added last. When CPUID leaf '0xB' is not present assume some defaults that would result in identical ACPI code generation. Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69222 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/mp_init.c: Only enable CPUs once they execute codeArthur Heymans
On some systems the BSP cannot know how many CPUs are present in the system. A typical use case is a multi socket system. Setting the enable flag only on CPUs that actually exist makes it more flexible. Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68892 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/smm_module_loader.c: Fix up CPU index locallyArthur Heymans
Don't pass the stub params to the mp_init code. Change-Id: I070bc00ae5e5bceb6c5b90ea833cc057dd41f6cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64802 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/x86/mp_init.c: Generate a C header to get start32 offsetArthur Heymans
In the current design the relocatable parameters are used to know the offset of the 32bit startpoint. This requires back and forward interaction between the stub, the loader and the mp init code. This makes the code hard to read. This is static information known at buildtime, so a better way to deal with this is to generate a header that contains this offset. Change-Id: Ic01badd2af11a6e1dbc27c8e928916fedf104b5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64625 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_pathArthur Heymans
It's quite confusing to keep track of lapic ID inside the device struct and initial lapic ID inside an array. Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06configs/config.lenovo_t400_vboot_and_debug: Move PT lowerArthur Heymans
Bootblock gets too big, so move the RO page table downwards. Change-Id: I3f72d1639478eaaac09d7cfb3408944ac76307c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74219 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06util/lint/stable-017: Update full config pattern matchingArthur Heymans
CONFIG_ARCH gives false positives for CONFIG_ARCH_X86_64_PGTBL_LOC so use a different string: 'CONFIG_MAINBOARD_DIR'. Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74220 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-06security/vboot: Don't add RO pagetables to RW_A/BArthur Heymans
Currently this is only used in bootblock and expects a fixed offset. Change-Id: I3c4db6fffe3343f12383fe9585620ffefb01cf81 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-06payloads/external/edk2: Add option to clone edk2-platforms repoMichał Żygowski
Add possibility to clone edk2-platforms repository. Some edk2 repositories may use modules from edk2-platforms which contains various feature packages for Intel platforms, e.g VT-d driver if DMA protection is enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iabd0793dfdcb95260046dc992ff30ef581159db9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68872 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06nb/intel/gm45: Export EDID-reading routine as a functionBill XIE
It will cache decoded EDID string in a static array. If called more than once, a pointer to the static array is directly returned, without reading EDID again. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/74180 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-06soc/intel/xeon_sp/spr: Drop devicetree setting X2apicPatrick Rudolph
Drop devicetree setting X2apic as the same functionality is already exposed in Kconfig. To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in the "APIC operation mode". Note: Your OS must have support for X2APIC. If you are using less than 256 CPU cores select XAPIC_ONLY here. Test: - Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME was selected. - Booted to OS in XAPIC mode when XAPIC_ONLY was selected. Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-06soc/intel/xeon_sp/spr: Default to X2APIC supportPatrick Rudolph
When more than 255 CPU cores are present on a board the X2APIC must be used. Select DEFAULT_X2APIC_RUNTIME to support X2APIC by default when a mainboard enables it in the devicetree. Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-06mb/intel/mtlrvp: Use `-` over `.` in chromeos-debug-fsp.fmdSubrata Banik
This patch renames debug FMD file (chromeos.debug-fsp.fmd) to chromeos-debug-fsp.fmd in order to match the file path name in `FMDFILE` config. TEST=Able to build intel/mtlrvp with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic8de07e4befa6b1ab8ab57d593c6939d87c48e9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06mb/google/skyrim: override Markarth PCIe configJohn Su
Because Markarth PCIe port 1 use for eMMc not SD. So we need override PCIe config for Markarth. And also the Markarth have NVMe and eMMC SKU. Follow Winterhold to look at the NVMe CLKREQ signal before initializing the ports allowing us to identify which device is populated and only initialize that device. BRANCH=none BUG=b:275669215 TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74133 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-04-05soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systemsPatrick Rudolph
Inject ACPI code for all generated ASL templates. This fixes ACPI errors shown in linux when not all sockets are currently plugged in or some have been disabled. Test: Boot Archer City with CONFIG_MAX_SOCKET=4 Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74183 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
2023-04-05drivers/wwan/fm: Use RTD3 root port mutex for reset methodsCliff Huang
The RTD3 driver should have its 'use_rp_mutex' set in the devicetree. BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the WWAN The RTD3 RPMX mutex should be used in the reset Methods Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ic3fe20c56b67c2b5177f55f4845610087a30dc7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73381 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-05soc/intel/common/block/pcie/rtd3: Add root port mutex supportCliff Huang
When 'use_rp_mutex' (default = 0) is set in the device tree, a root port mutex will be added. This mutex is used in _ON and _OFF method, where the GPIO reset and/or enable GPIO value is changed. The companion driver, such as WWAN driver, needs to acquire this root port mutex when accessing the same GPIO pins. Using this common mutex prevents those invoked methods from being called from different thread while one is not completed. An example is that WWAN driver calling _RST method to reset the device and does remove/rescan for the device while the pm runtime work might call RTD3 _OFF. For those root port without additional driver, this mutex is not needed. BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated and _ON and _OFF should use this mutex. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ibc077528692b2d7076132384fb7bd441be502511 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-05mb/google/skyrim: Remove unused sleep GPIO tableKarthikeyan Ramasubramanian
On Skyrim, there isn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function overhead. BUG=None BRANCH=Skyrim TEST=Build Skyrim BIOS image. Change-Id: Ia9d55a5e2295bb2e2c2957c4f5207362f616022c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-05nb/intel/gm45: Prevent null-deref in get_blc_pwm_freq_value()Bill XIE
IF its first call is get_blc_pwm_freq_value(NULL), null dereference will occur. Now when the parameter is NULL, it will return the value of the static blc_pwm_freq directly, so the original behavior is kept. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I32354aa0fe1a3ca725c2031f973ffad0bda81ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-05util/spd_tools: Add support for Phoenix platformKarthikeyan Ramasubramanian
Update spd_gen and part_id_gen utilities to accommodate Phoenix platform so that SPD can be generated for the memory parts used in that platform. SPD requirements for Phoenix and Mendocino platforms are identical. BUG=b:273383819 TEST=Run spd_gen and ensure that both Mendocino and Phoenix platforms share the platform manifest for LP5 memory parts. Change-Id: I7a12f73065864f08db8922c1a69eb503865a25b1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-05Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"Nick Vaccaro
This reverts commit e7a1204f26fe3628de99b4ab4e3f32916565b95c. This initial change was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74207 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-05Revert "mb/google/brya: Enable asynchronous End-Of-Post"Nick Vaccaro
This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32. Revert initial change as it was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04cpu/x86/64bit/Makefile: use all_x86 make targetFelix Held
Use the newly introduced 'all_x86' make target to add the mode_switch.S compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8950375d31557d9a38169869c1d250417261c31c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-04cpu/x86/64bit/Makefile: use verstage_x86 make targetFelix Held
Use the 'verstage_x86' make target for the mode_switch.S compilation unit instead of making adding it to the 'verstage' target depending on VBOOT_STARTS_BEFORE_BOOTBLOCK not being selected. The only case where VBOOT_STARTS_BEFORE_BOOTBLOCK is selected is the verstage on PSP case, so I find using the 'verstage_x86' target here a bit easier to understand. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab618d4b9e325b07a648b91fcdce99c63644fbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74196 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04drivers/pc80/pc/Makefile: use all_x86 make targetFelix Held
Use the newly introduced 'all_x86' make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23c6977ae8acebb8dcd546f86f7f7b677272a6cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74153 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04cpu/x86/lapic,pae,tsc/Makefile: use all_x86 targetFelix Held
Use the newly introduced 'all_x86' make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181c3207bb1ebe9c5080ef3a3cdda8146ed05822 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74152 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04soc/amd/*/Makefile: use all_x86 targetFelix Held
Use the newly introduced 'all_x86' make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless builds for Mandolin without verstage on PSP and Guybrush with verstage on PSP result in identical images with and without this patch applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94de6de5a4c7723065a4eb1b7149f9933ef134a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74151 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-04Makefile.inc: introduce all_x86 targetFelix Held
For compilation units that should be built for all stages that run on the x86 cores in a newer AMD SoC, but can't be built for verstage on PSP which is an ARM core, the 'all' target can't be used, since that would result in the compilation unit also being added to the verstage target in the verstage on PSP case. In order to not need to add a compilation unit to the 'bootblock', 'verstage_x86', 'romstage', and 'ramstage' targets in separate lines in the Makefile, introduce the 'all_x86' target that adds a file to 'bootblock', 'verstage_x86', 'romstage', 'postcar', and 'ramstage'. The compilation units also need to be added to the 'postcar' stage which is only present on the pre-Zen SoCs to be able to also use the 'all_x86' target in common AMD code that is also used in those pre-Zen SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74150 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-04mb/starlabs/*: Add CMOS entries for the mirror flagSean Rhodes
Add the required CMOS entries for the mirror flag, so that it can be enabled from a defconfig. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I174ac896df050480ee90c8141c5536b628c98432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04ec/starlabs/merlin: Add support for the ITE mirror flagSean Rhodes
When enabled, the EC will mirror the firmware contained inside the coreboot ROM. This allows it to be updated at the same time as coreboot. Enable the mirror flag if the installed EC firmware does not match the target version or if a CMOS option, "manual_mirror_flag" is set. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I377abbb37dc4d3e535e518a73e73969b25967daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-04mb/starlabs/starbook/adl: Add an option to enable Hot PlugSean Rhodes
Some third-party SSDs, from Samsung and WD, such as the 990 Pro and WD Black 850X aren't initialised by coreboot, seemingly as coreboot is too quick; debug builds work, and enabling hotplug does. Add a cmos option `pci_hot_plug`, defaulting to enabled to allow these SSDs to work. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I680211bc87153a5e6005d58040a94725c0973451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-04mb/starlabs/starbook: Disable ASPM in corebootSean Rhodes
ASPM is already configured by FSP so disable it in coreboot to reduce boot time by a whopping 34ms. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-04-04arch/x86/smbios: Check str for NULL in smbios_add_string()Maximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic228b869aea362c1f07e0808c2735ff3b285a6bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73980 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-04-04mb/starlabs/starbook/adl: Remove Soundwire workaroundSean Rhodes
This was added to solve Debian 10 not booting. Debian 10, which now isn't the latest stable version works, so remove the workaround that was included in the original port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/google/brya/var/omnigul: Add ADL and RPL dptf settingsJamie Chen
Add Alder Lake (ADL) and Raptor Lake (RPL) dptf settings for omnigul BUG=b:273415170 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I8280f82ff1534ea63bcb448da231712bb4abd6d3 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-04Revert "mb/starlabs/*: Remove sleepstates.asl"Sean Rhodes
This reverts commit ac69ce91229dee68d4135c596f49cf9e5efbe1e9. Reason for revert: Removing breaks suspend in kernels > 6.2 and Windows. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-04-04mb/google/rex: Enable CSE pre-cpu timestampsBora Guvendik
Enables pre-cpu boot timestamps from cse. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot on rex, check "cbmem -t" Change-Id: I68cd53c18af6a400bcd9dc15d428a904b0647495 Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73759 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-04soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp tableBora Guvendik
Get boot performance timestamps from CSE and inject them into CBMEM timestamp table. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Able to see TS elapse prior to IA reset on Rex Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04commonlib: Add new "DMU load completed" TSBora Guvendik
990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot to OS, check cbmem -t Change-Id: I4d2da820f39c40ea864d15d25a94a68497b2af3d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74047 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04soc/intel/alderlake: Add support for CSE timestamp data versionsBora Guvendik
CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04mb/google/mtlrvp: Update MTLRVP Flash LayoutUsha P
This patch updates the MTLRVP flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. SI_BIOS: SI_EC: Removed RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:271407315 TEST=Able to enable CSE update on MTLRVP and have free space to add one more PUNIT FW to support different SoC stepping. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73378 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-04-04mb/intel/mtlrvp: Add fmd for debug FSPUsha P
Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for MTL-P RVP flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. BUG=b:271407315 TEST=Build intel/mtlrvp with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: Ief7dd39af018c4c1519ca80d1303085d8298cda6 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74193 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-04-03option: Allow to use the EFI variable driver as option backendPatrick Rudolph
Use the introduced EFI variable store driver on top of the SMMSTORE region in SPI flash to read/write options. Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62562 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03drivers/efi: Add EFI variable store option supportPatrick Rudolph
Add a driver to read and write EFI variables stored in a region device. This is particularly useful for EDK2 as payload and allows to reuse existing EFI tools to set/get options used by the firmware. The write implementation is fault tolerant and doesn't corrupt the variable store. A faulting write might result in using the old value even though a 'newer' had been completely written. Implemented basic unit tests for header corruption, writing existing data and append new data into the store. Initial firmware region state: Initially the variable store region isn't formatted. Usually this is done in the EDK2 payload when no valid firmware volume could be found. It might be useful to do this offline or in coreboot to have a working option store on the first boot or when it was corrupted. Performance improvements: Right now the code always checks if the firmware volume header is valid. This could be optimised by caching the test result in heap. For write operations it would be good to cache the end of the variable store in the heap as well, instead of walking the whole store. For read operations caching the entire store could be considered. Reclaiming memory: The EFI variable store is append write only. To update an existing variable, first a new is written to the end of the store and then the previous is marked invalid. This only works on PNOR flash that allow to clear set bits, but keep cleared bits state. This mechanisms allows a fault tolerant write, but it also requires to "clean" the variable store for time to time. This cleaning would remove variables that have been marked "deleted". Such cleaning mechanism in turn must be fault tolerant and thus must use a second partition in the SPI flash as backup/working region. For now to cleaning is done in coreboot. Fault checking: The driver should check if a previous write was successful and if not mark variables as deleted on the next operation. Tested and working: - Enumerate all existing variables - Read variables - Write variables Change-Id: I8079f71d29da5dc2db956fc68bef1486fe3906bb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52564 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03mb/google/rex: Use FW_CONFIG for generating ACPI code for WIFISubrata Banik
This patch avoids creating runtime ACPI for unused WIFI solutions. For example: if the Rex SKU is with WIFI_CNVI then you don't need to populate ACPI code for WIFI_PCIE. FW_CONIG can be used for making those decisions. TEST=No ASL entries being created for WIFI_PCIE if the FW_CONIG is set to WIFI_CNVI. Also, helped to save the boot time on google/rex (FSP-S API) by 9ms. Change-Id: I60e4332d8d8c360fdf425b30513ff79209979e85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74147 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-03commonlib/coreboot_tables.h: Fix typo in enum type nameAngel Pons
Fix a typo in an enum's type name, "tmp" ---> "tpm". The enum type is not used anywhere in the coreboot tree. Change-Id: Ie7529e7ee80aa9661ec053da8211c2c3295b3942 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-03soc/amd/cezanne,glinda,mendocino,phoenix,picasso/Kconfig: use all targetFelix Held
The i2c.c compilation unit is added to all stages in all cases, so use the all target instead of adding it to all stages separately. Also order the all targets alphabetically. TEST=Timeless build on Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie90380075a3c87d226cdcb0f41f7e94275eaaa42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>