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2021-08-31mb/razer/blade_stealth_kbl: Disable UART #0 in devicetreeAngel Pons
FSP-S disables UART #0 as per the `SerialIoDevMode` settings. Change-Id: Ic1f9f7ce6fd4f453200d563bd8556946eef1b287 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Mimoja <coreboot@mimoja.de>
2021-08-31mb/google/caroline: Enable I2C #2 in devicetreeAngel Pons
Commit 98ec53bdf15ff79369307862e71142d4606f9e5a (mb/google/caroline: Re-enable I2C2 / fix digitizer) enabled I2C #2 in the `SerialIoDevMode` array, but left the device disabled in the devicetree. Enable it. Change-Id: I67eec1c753bfd2a78ed0c1e0a78057cd4a3d4153 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-31mb/google/poppy: Do not let FSP-S init UART 0Angel Pons
FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy boards only enable UART 0 because it's function 0 of PCI device 30, and the PCI specification requires that function 0 of multifunction devices be implemented if other functions are implemented as well. Nautilus got remedied in commit 8a1f095e50e068e42d378f47c79467e7b6295b7b (mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the SerialIO device. This way, it remains enabled and the GPIO settings will not be overwritten by FSP. However, not all variants do this, but use some UART 0 pads as GPIOs. To prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the variants. Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31amdfwtool: Add flag for multi FW level to the struct amd_cb_configZheng Bao
This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31amdfwtool: Copy string in a safer wayZheng Bao
The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd/cezanne/fch: implement and use fch_clk_output_48MhzFelix Held
Make sure that the 48MHz clock output that is typically used as a clock source for an I2S audio codec or a Super I/O chip. TEST=On Guybrush before and after this patch the final state of MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/(amd,google): Remove spi configuration from devicetreeMartin Roth
Now that the SPI configuration has been moved into Kconfig, it is no longer needed in devicetree. BUG=b:194919326 TEST=Build & boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifdcd3f33173194c4a25794137756b143751edd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd: Show SPI settings in bootblockMartin Roth
BUG=b:194919326 TEST=See SPI settings in bootblock Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd/common: Show current SPI speeds and modesMartin Roth
This patch adds code to print the current SPI speeds for each of the 4 different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays the SPI mode and whether or not SPI100 mode is enabled. BUG=b:194919326 TEST: Display the speed, change speeds, show that new speeds are the expected values. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd/cezanne/early_fch: Perform early SPI initializationKarthikeyan Ramasubramanian
Add the fch_spi_early_init call in fch_pre_init to perform early SPI initialization which enables SPI ROM and setting the speed & read modes. BUG=b:194919326 TEST=Build and boot to OS in Guybrush. Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd/common: Update SPI based on Kconfig & EFS instead of devtreeMartin Roth
Get the settings for fast-read and mode from EFS, and reprogram those. Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings. BUG=b:195943311 TEST=Boot and see that SPI was set to the correct speed & mode Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-30soc/amd/common: move GPIO register state save struct to gpio_banks.hFelix Held
The common_i2c_save struct isn't specific to the I2C code and since it contains the state of the GPIO control & status register and the state of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and rename it to soc_amd_gpio_register_save. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-30soc/amd/common/fsp/Makefile: drop strip_quotes call in FSP-M size checkFelix Held
No need to strip the quotes of the FSP-M file path in the size check and it's always a good idea to not remove the quotes around file paths that will get passed as parameters to shell programs so that spaces in the path can't cause malfunction. TEST=All cases still behave as expected for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-30mb/intel/adlrvp_m: Fix to Enable PCIe x1 SlotCliff Huang
This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs. The BDF for this PCIe slot is pci is: 0000:00:1d.0 TEST = show device command: $ lspci -s 00:19.0 expect this: 00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/brya/var/felwinter: Update gpio tableEric Lai
Based on latest schematic to update the gpio table. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0d91199ffd2128a136ea0a33dfe7affa77ae61d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30mb/google/brya/var/felwinter: Update device treeEric Lai
Based on latest shcematic to update the device tree. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I59601571c5e4c2d19738cb333605fb22e1ea0d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30mb/google/brya: Enable TCSSDeepti Deshatty
Enable flag SOC_INTEL_COMMON_BLOCK_TCSS. BUG=b:187385592 TEST=type-C pendrive/Gen-2 SSD detected as Super speed. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54090 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/dedede/var/driblee: Configure thermal sensor settingFrank Wu
According to schematics, TSR2 thermal sensor is not present in driblee. BUG=b:191732473, b:197180925, b:195868075 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I343a6161f71f66b77d23f1fa2f581aaee5eddf1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57091 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/dedede/var/driblee: Configure audio settingFrank Wu
Update the combination audio CS42L42 and amp. MAX98360. BUG=b:195619349, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I264c680ed5638b71c912253a38c27152a9015d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-29soc/amd/cezanne/chip: add functionality to power down eMMC interfaceFelix Held
Power down the eMMC controller via the AOAC interface when it's not enabled in the devicetree. BUG=b:184978118 TEST=On guybrush the unused eMMC controller is disabled in AOAC after applying this patch. Before this patch it was enabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-08-29superio/nuvoton/nct6776: Correct the definition of NCT6776_GPIOBASEBill XIE
NCT6776's data sheet does say that the virtual LDN of GPIO base should be 0x308, and most mainboards using it usually correctly config it in devicetree.cb under the path 2e.308, but in nct6776.h it used to be defined as 8 from the beginning (an ancient commit 1e3a22649a9, lately revived in commit f95daa510d6), identical to the LDN of WDT, which eliminates the definition of value 2e.308, and makes related resource allocations unable to take effect. (in log we can find "PNP: 002e.308 missing read_resources" if 2e.308 is enabled and assigned with resources) In this commit, NCT6776_GPIOBASE is set to a value consistent with the data sheet. With this commit, resources under 2e.308 of NCT6776 can be allocated successfully. Change-Id: I604bad7ab34a8f57262fdec508e5952cf8eabf1c Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-28mainboard/intel/harcuvar: Remove hardcoded lapic 0 from devicetree.cbMariusz Szafrański
This change follows other Intel SoCs common way to support SKUs with bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and allowing its detection at boottime. It completes support for HCV/DNV after base SoC patch: commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9 soc/intel/denverton_ns: Ensure CPU device has a valid link Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11 Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-28soc/amd/common/fsp/Makefile: check if CONFIG_FSP_M_FILE is definedFelix Held
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size call evaluates to an empty string, so the file-size call will run "cat | wc -c" which will cause make to get stuck in there. Also print a message when no FSP-M file is specified that the resulting image won't boot successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-28mb/google/{dedede,hatch}: Remove unneeded documentationFelix Singer
This documentation doesn't add any more value. Thus, remove it. Change-Id: I0402bc736c6cc77d88a836bddce8eadae8ec5d7c Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28mb/google/brya/variants/primus: update USB 2.0 controller Lane ParameterCasper Chang
Modify USB 2.0 port5 parameter to improve SI diagram measurement. BUG=b:187992881 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I1eff05a7ad6563898744c24f9657e28625319873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/dedede/var/drawcia: Add fw_config probe for ALC5682-VD/ALC5682-VSWisley Chen
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:194356991 TEST=ALC5682-VD/ALC5682-VS audio codec can work Change-Id: I71b824c42c13cc2a8bebe0072de4a65ce238f074 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/dedede/var/boten: Generate SPD ID for supported partstanley.wu
Add supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. The memory part being added is: MT53E512M32D1NP-046 WT:B BUG=b:194223174 BRANCH=dedede TEST=Build the boten board. Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya/var/anahera: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:197850509 TEST=build pass Change-Id: Ib7bdab1396138d728ae053c30656a9c80dddaff8 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/dedede/var/driblee: Configure I2C ports and touchpadFrank Wu
Update the I2C ports and touchpad based on the schematic. BUG=b:195622489, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I8778ad6564e526e029c46c36c78e38f764e3c6b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56998 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/driblee: Configure USB port settingsFrank Wu
Update the USB port configuration based on driblee schematic. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 1 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: None USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:195622487, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/(amd,google): Update SPI Kconfig settings based on devicetreeMartin Roth
This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya: Add two sensors for DPTF functionalitySumeet Pawnikar
Add two thermal sensors for fan and wwan for DPTF based thermal control. BRANCH=None BUG=b:181271666 TEST=None Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
2021-08-28mb/intel/adlrvp_m: Enable touchscreenBernardo Perez Priego
This will add ACPI information to enable WACOM touchscreen. TEST=Boot DUT and issue command: $ ls -al /sys/bus/i2c/devices WACOM PWB-D893 device should be listed and touchscreen should be functional. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-28mb/google/dedede/var/corori: Generate RAM ID and SPD fileIan Feng
Add the support RAM parts for Corori. Here is the ram part number list: DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR BUG=b:196744958 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56988 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure thermal sensor settingIan Feng
According to schematics, TSR2 thermal sensor is not present in corori. BUG=b:197281317 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Id69f9d6ace738ef1e792addd782d05c2d03d2b3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57110 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure I2C ports and touchpadIan Feng
1. Support Elan touchpad. 2. Follow schematic to disable I2C1, I2C2 and I2C3. BUG=b:197052531 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ideef57c275432e21f8580d4c5c937909b168d91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57031 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure audio settingIan Feng
Select the drivers for ALC5682 codec and MAX98360A spk amp BUG=b:197037090 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0659a05fbcc28702d922a23d74885ba65a4254f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57015 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure USB port settingsIan Feng
Follow schematic to modify USB port settings. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 0 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: Integrated Bluetooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:196998272 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2045b2be9d79bfd394fa4520faa0fb552a704206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57010 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure GPIO settingsIan Feng
Updated the GPIO pins based on the latest schematic. BUG=b:196867404 BRANCH=keeby TEST=FW_NAME=corori emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I683a7da4fcb2e4e0efdb3547b1de15796c6b55e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya: Create anahera variantWisley Chen
Create the anahera variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:197850509 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ANAHERA Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27mb/google/butterfly: Put braces around `else` branchAngel Pons
Ensure braces are consistent on all branches of a conditional statement, as per the coding style. Tested with BUILD_TIMELESS=1, Google Butterfly remains identical. Change-Id: I34f3b22486e0f0712bc248477acb43012b21c5ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-27mb/amd/majolica/Kconfig: add EFS SPI settingsFelix Held
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100 case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config for the EM100 emulator case that has limited SPI frequency support. Tested on Majolica by Martin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27broadwell: Drop weak `mainboard_fill_spd_data` definitionAngel Pons
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define this function accordingly. Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/intel/broadwell: Move `mainboard_fill_spd_data`Angel Pons
Move the `mainboard_fill_spd_data` function out of romstage, in preparation to confine `pei_data` usage to as few files as possible. Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27Broadwell boards: Do not assign unused SPD addressesAngel Pons
The `pei_data` struct is already zero-initialised. Change-Id: If539cddc007f32a04389bc3b3b06c43cb5c86e10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55804 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/auron: Refactor memory-down SPD handlingAngel Pons
Variants only need to provide the SPD index and whether said index corresponds to a dual-channel configuration, which can be achieved without using `pei_data`. Add two functions that return the values and use them in `spd.c` at mainboard level. Change-Id: I9bc4527057d4a771883c8cc60da2501516d6fb94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-27mb/google/brya/variants/primus: Enable SaGv supportAriel Fang
This patch enables SaGv support for primus. BUG=b:196286180 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I00074e348dd6347602c18dcfd231a890153b4685 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27soc/intel/denverton_ns: Ensure CPU device has a valid linkFurquan Shaikh
This change calls `add_more_links()` in `denverton_init_cpus()` if `dev->link_list` is NULL. This condition can occur if mainboard does not add any APIC device in the device tree. Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I6f453901b17f7eff22beed8dbf6995cdc9f9b776 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/intel/adlrvp: Enable SaGv supportV Sowmya
BUG=b:187446498 TEST=Boot and verify memory trains at all the SaGv points through FSP debug logs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-08-27mb/google/cherry: Support audio codec RT1011Trevor Wu
Add GPIO "rt1011 reset" and i2c2 initialization for RT1011. Add CHERRY_USE_RT1011 and CHERRY_USE_RT1019 to Kconfig, so we can spearate code for the specific codec by config. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I18939a2a2caae0444ce17f4712764647975121ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/57157 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27libpayload: cbgfx: Clear screen by sequential accessYu-Ping Wu
Currently clear_screen() calls set_pixel() to set all pixels. However, the actual order of pixels being set depends on the framebuffer orientation. With NORMAL orientation, the framebuffer is accessed sequentially; with LEFT_UP/RIGHT_UP orientation, it is accessed back and forth, leading to performance drop (>1 second on bugzzy). Therefore, ensure sequential access to the framebuffer, regardless of the orientation. BUG=b:194967458 TEST=emerge-cherry libpayload BRANCH=dedede Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57104 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27Doc/mb/ocp: Update Delta Lake documentation for RAS featuresJohnny Lin
Change-Id: I71b97930f1a1ca4a60f830a90d80af6ca0236c8e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-08-27mb/google/dedede/var/driblee: Configure GPIO settingsFrank Wu
Updated the GPIO pins based on the latest schematic. BUG=b:191732473, b:195619827 BRANCH=keeby TEST=FW_NAME=driblee emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I20baeb6b13c8c0a70c7555aa8f7f5557768c0083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56996 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/amd/common/block/spi: Add SPI config to KconfigMartin Roth
Currently, The SPI speed/mode configuration is split between Kconfig and devicetree. We'd like to have everything in one place. Since we need the fast-read speed and the mode available in the Makefile to build the AMD EFS table, we currently need it in Kconfig. Move all of the settings to Kconfig and remove them from Devicetree in a later commit. BUG=b:195943311 TEST=boot majolica & guybrush, verify spi settings Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/variant/drawcia: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen
Add SPD support to drawcia for MT53E512M32D1NP-046 WT:B. This part is already in global_lp4x_mem_parts.json.txt, and use /util/spd_tool/lp4x/gen_part_id to assigns DRAM IDs. BUG=b:196951879 BRANCH=firmware-dedede-13606.B TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage Change-Id: Ic42e6357943ba651ffd92fb2974e9ea52fa19020 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56905 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/var/sasukette: Add FW_CONFIG probe for EXT_VRZhi Li
commit df520855 (soc/intel/jsl: Add disable_external_bypass_vr config) Add FW_CONFIG probe for don't stuffing ANPEC APW8738BQBI IC. BUG=b:190727416 BRANCH=dedede TEST=test for enter S0ix and resume normally by powerd_dbus_suspend Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I15ab30f14df9dc02157009091aa8398e2fa75188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56804 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/amd/common/fsp/fsp_validate: add runtime check for FSP-M binary sizeFelix Held
When modules are added to the FSP and they won't fit into the FSP binary any more, the size can be increased in the FSP build. Especially in the case of debug builds the increased size might not fit into the memory region it gets decompressed into which starts at FSP_M_ADDR and has a size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header function that ends up being called by the FSP driver in romstage to do some additional checks on the FSP binary's header that includes the version number and the image size. We can use the image size field to check if it fits into the reserved region. Since the FSP-M memory region is located after romstage loading it won't clobber the romstage code where we do the check. This runtime check is added in addition to the build-time check to also cover the case when the FSP binaries in CBFS get replaced with ones that don't fit into the reserved memory region after the coreboot build. BUG=b:186149011 TEST=Mandolin still boots fine with the patch applied. When as a test the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000 which is by far not enough for the decompressed FSP-M binary to fit into it prints the newly added error message on the console and then stops. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26elog: Define constant for RW region nameRicardo Quesada
This CL indroduces the ELOG_RW_REGION_NAME. This constant replaced the hardcoded "RW_ELOG" value. This constant will be used also by elogtool (see CL in the commit chain). BUG=b:172210863 Change-Id: Ie8d31204e65fd67d52b0f8ced7b8c1ffdcf5b539 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56986 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26elog: move functionality to commonlib/bsdRicardo Quesada
This commit moves some drivers/elog/ functionality to commonlib/bsd since they will be called from util/cbfstool/. In particular: * elog_fill_timestamp(), elog_update_checksum(), elog_checksum_event() were moved to commonlib/bsd/elog * elog_fill_timestamp() receives the time parameters and updates the event based on the "time" arguments. The original elog_*() functions were written by Duncan Laurie (see CB:1311) and he gave permission to re-license the code to BSD. BUG=b:172210863 Change-Id: I67d5ad6e7c4d486b3d4ebb25be77998173cee5a9 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26mb/google/octopus: add CBI SKU RAM ID 5Sheng-Liang Pan
add CBI sku RAM ID 5 for 4GiB Capacity with dual channel and dual rank with 4gb dram density. BUG=b:178665760 BRANCH=Octopus TEST=build fw and flash to the dut with RAMID 5, dut can boot up successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I922a518cffc4dac71caec68e6f7a55c6c5717438 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56982 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26mb/google/dedede/var/bugzzy: Configure USB portsSeunghwan Kim
Override USB port configurations based on the latest bugzzy schematics. BUG=b:192521391 BRANCH=None TEST=Built test coreboot image Change-Id: I4368946f4175f4f065a3483dc7ca6068c6de3123 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-26soc/intel/tigerlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: Ice4c727f2b75893cd012345a556fd21d9807dfaa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26soc/intel/alderlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. TEST=boot to OS, read PCI 0:0.0 config register 0x80, value is 0x31 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0c3e16edeab6f85a79eb10e1477d95952b554a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26soc/intel/common/block: Add PAM locking functionTim Wawrzynczak
Some FSPs provide a UPD to allow the bootloader to set the PAM lock bit instead of the FSP, therefore add a function in the common code to do this. Source: ADL & TGL FSP integration guides Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1d6642b496617b6e8ccda8a0aa6bfd88ea9dc3ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/57145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26mb/google/var/redrix: Correct the WWAN_PERST_L settingWisley Chen
WWAN_PERST_L (GPP_E0) is wrongly configured to NC in ramstage. So, remove it. BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: If8e96045a0d78a942f77d8d8e371ab75dff0c202 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-26mb/google/brya/variant/redrix: Correct MAX98390 AMP settingWisley Chen
4 MAX98390 Speaker Amps are connected to i2c0 and device addresses are 0x38/0x39/0x3a/0x3b BUG=b:191931762 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ie8f01e6a7e09e18f6d34f3ceb1db8e2e238197bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57114 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26drivers/intel/fsp2_0: rename soc_validate_fsp_versionFelix Held
Rename soc_validate_fsp_version to soc_validate_fspm_header, since it can not only be used to check the version info in the FSP-M binary's header, but also to check every other field in the binary's header. This is a preparation for a follow-up patch that implements this function to check the FSP-M binary's size. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26soc/amd/common/fsp/Makefile: check if FSP-M is larger than FSP_M_SIZEFelix Held
The FSP-M binary needs to fit into the memory region that starts at FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time if the uncompressed FSP-M file is larger than the size of the region it will be copied into. BUG=b:186149011 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26device/mipi: Move to drivers/mipiJulius Werner
Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-26mb/google/guybrush: Create dewatt variantBhanu Prakash Maiya
Create the dewatt variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:196460993 BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_DEWATT Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I57860a7cad1bf202bd3ef3eed5f498fbf1d29af8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57108 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25tests: Fix function mocking for clangJulius Werner
clang seems to like to do some aggressive optimizations that break our approach of mocking functions for test by using objcopy to turn them weak after the fact on individual compiled object files. For example, in CB:56601 the function cbfs_get_boot_device() is mocked this way. When compiling the cbfs_boot_lookup() function in src/lib/cbfs.c with clang, it will generate a normal callq instruction to a relocation for cbfs_boot_lookup(), which can then later be pointed to the mocked version of that function. However, it will also somehow infer that the version of cbfs_boot_lookup() in that file can only ever return a pointer to the static local `ro` variable (because CONFIG_VBOOT is disabled in the environment for that particular test), and instead generate instructions that directly load the address of a relocation for that variable into %rdi for the following call to cbfs_lookup(), rather than using the real function return value. (Why it would do that is anyone's guess because this seems unlikely to be faster than just moving the function return value from %rax into %rdi like a normal compiler.) Long story short, this optimization breaks our tests because cbfs_lookup() will be called with the wrong pointer. clang doesn't provide many options to disable individual optimizations, so the only solution seems to be to make clang aware that the function is weak during the compilation stage already, so it can be aware that it may get replaced. This patch implements that by marking the mocked functions weak via #pragma weak lines in the per-test autogenerated config header. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1f9011f444248544de7a71bbefc54edc006ae0cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-08-25mb/roda/rv11/acpi: Use lower case format for hex valuesFelix Singer
Change-Id: I3bea9e1f9cc25a4476ddbaa8bd8e434609eb28f7 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25mb/roda/rv11/acpi: Use Printf ()Felix Singer
Change-Id: Iec6ec8bbf3cc5c9230ba6bcb0126ff6085f26464 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25soc/intel/cannonlake: Fix PCH-H IRQ constraintsAngel Pons
Cannon Point PCH-H does not implement the eMMC, I2C4 and I2C5 devices. Guard the IRQ constraints for these devices to prevent FSP assertions. Tested on Prodrive Hermes, debug FSP builds no longer fail to boot. Change-Id: I58674d1c3c5fe4535c022020674d48d6a5315bf9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25mb/google/brya/variants/gimble: Correct I2C slave address and update gpio.cMark Hsieh
1. According to the Maxim's comment and schematic diagram of proto, Modify I2C slave address to 0x38, 0x3c. 2. According to the schematic diagram of proto, Change GPD11 to NC. BUG=b:191811888, b:1191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibf8adf2ed8dda9ae6da06e7e995bef9395cdee35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57059 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/google/dedede/var/galtic: modify touchscreen to native I2C protocolFrankChu
Touchscreen will be no function with R93-14092.19.0 image or be later. It just happened to work because elants_i2c driver would bind to the device first based on "ELAN0001" HID ID BUG=b:195994810 TEST= verify only update RW FW can fix touchscreen no function issue 1.Build test firmware 2.prepare DUT enviroment (R93 image + update RW to test firmware) 3.verify touchscreen function normally Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie9e0fe726854d0128ad1bb430544640dc8f034ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/57011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2021-08-25mb/google/dedede/var/sasukette: Update DPTF parametersZanxi Chen
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I06d8a543dbd77137cb97c4ea695a1f2b9f8ee76c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57116 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/goog/bry/var/redrix: Enable Genesys GL9755 settingWisley Chen
BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I45ecab8c036a7e75cc0c564867119c027175ed06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25soc/intel/tigerlake: Hook up ucode for TGL-HTim Crawford
Hook up microcode from 3rdparty repo for: - 06-8d-01 (CPUID signature: 0x806d1) Verified microcode blob was found in CBFS on system76/gaze16 (TGL-H). CBFS: Found 'cpu_microcode_blob.bin' @0x11700 size 0x18400 in mcache @0x76c2d0ac microcode: sig=0x806d1 pf=0x2 revision=0x2c Change-Id: Icf0d8bc700a73697f06503e9d1bb40ce26741cdf Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57067 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/google/brya/primus: modify HID to MX98357A to enable audio functionCasper Chang
Primus has MX98360A, which Linux kernel 5.10 currently does not support and, therefore, audio does not work. As the device is compatible with the MX98357A, use that until Linux’ SoF driver supports the new version (https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268). BUG=b:194749863 BRANCH=none TEST=build coreboot and audio function works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I893d9a31dc2c7726599c150be01b9585fb6c8a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25mb/google/brya: Fix PL4 limitsTim Wawrzynczak
Commit e7f3e6a0558 added PL4 limits for brya0, but the units were mW, whereas the `tdp_pl4` field is expected to be in whole Watts, therefore divide all of the settings by 1000. BUG=b:197468828 TEST=boot brya0 to OS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6da6bae4eb8c83188d813828cdc4f7c1e20f1b5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-08-24mb/google/brya/variants/kano: Init devicetree for kanoDavid Wu
Init basic override devicetree based on schematics BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I283517427612e24eabe2ce736d677253065c7859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/brya: Enable SaGv supportV Sowmya
This patch enabled the SaGv support for brya0 baseboard. BUG=b:187446498 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I2a71e159fa49f677660af8279f2b582a3916eee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for primusMalik_Hsu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for primus. BUG=b:195611000 BRANCH=None TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0c60979a2d42f836e0f0261c42fcfc36c41e113a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/dedede/var/cret: Add new G2Touch touchscreenDtrain Hsu
Add G2Touch G7500 touchscreen into devicetree for cret. BUG=b:180547621 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I57638bf8a3eb4efcd819f5433fa54c22b7af3054 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-24mb/google/brya/var/felwinter: Generate RAM ID and SPD fileEric Lai
Add the support RAM parts for felwinter. Here is the ram part number list: DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) BUG=b:197308861 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I76febefc251b02a047819242e23c02dc50891c2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/broadwell: Move `pei_data` out of romstage.cAngel Pons
Prepare to confine all `pei_data` references in raminit.c and refcode.c so that mainboards don't need to know about its existence. Change-Id: I55793fa274f8100643855466b6cca486896fb2c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55801 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/broadwell: Do early ME init a bit earlierAngel Pons
Do early ME init before adding the "start of raminit" timestamp. Change-Id: If8b27a9d4eb3b801e3e05dc2f2b95bf748985707 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55800 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/tigerlake: Add USB ACPI devices for PCH-HJeremy Soller
Change-Id: Ia1c1c3d172366ddcc8c194cb2e0b0c2fb2acf678 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add SPI_DMI_DESTINATION_ID for PCH-HJeremy Soller
Change-Id: I9a316b91b31166831f23eaf9e271a7d67ac4ccff Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Set UserBd to recommended default for PCH-HJeremy Soller
Change-Id: Ie8a28d8e03d7176df5409e6cb507a0a802ff026f Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56951 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-HJeremy Soller
Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add TGL-H PEG portsJeremy Soller
Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCIe root ports for PCH-HJeremy Soller
Change-Id: I89e300adce2edeb9d9c2bba1782c212ee656a532 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H GPIO definitionsJeremy Soller
Add TGL-H GPIO definitions, based on existing TGL definitions and how CNP/CNP-H handles the split. Reference: - Intel doc 619207 - TigerLake FSP - linux/drivers/pinctrl/intel/pinctrl-tigerlake.c Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H PMC GPE group definitionsJeremy Soller
Reference: - TigerLake FSP Change-Id: I666eb710762f6b00d173ee1a473f1f5a612953a6 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H chipset devicetreeJeremy Soller
Based on the base TGL devicetree, add one specific to TGL-H that adds the additional supported devices. Introduces a new Kconfig for selecting the PCH support. Reference: - Intel doc 615985 Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add TGL-H power limitsJeremy Soller
Convert the power limit defines to an enum and add TGL-H entries. Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel: Add TGL-H CPUIDJeremy Soller
Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56942 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 12:08:39 +0000