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authorJeremy Soller <jeremy@system76.com>2021-08-12 10:49:58 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-08-24 14:50:42 +0000
commit86d8ac7a5f5c203f4a7f7e5eb094d045354147ce (patch)
tree776d63b4a0194edc5239ed5bdf23379d08e91bcc
parente7aa4541d432b3d543b55067dc277b77f0c18f8c (diff)
soc/intel/tigerlake: Set UserBd to recommended default for PCH-H
Change-Id: Ie8a28d8e03d7176df5409e6cb507a0a802ff026f Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56951 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 8c8461093e..40683e2a2e 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -29,7 +29,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
m_cfg->SaGv = config->SaGv;
- m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+ if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H))
+ m_cfg->UserBd = BOARD_TYPE_DESKTOP;
+ else
+ m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
m_cfg->RMT = config->RMT;
/* CpuRatio Settings */