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2023-03-09soc/amd/mendocino: Update XHCI GPE to use constantRobert Zieba
The GPE number used for XHCI has now been defined in AMD's common code in CB:67936. Change over existing code to use this new definition. BUG=b:186792595 TEST=Ran on skyrim device and verified XHCI GPE setting. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I3bfc2256ea2ca851afe88f2cdb419f39eee76fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/69916 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09soc/amd/common/xhci: Add support for logging XHCI wake eventsRobert Zieba
AMD SoCs currently only log the GPE# when an XHCI controller wakes the system. Add code to log XHCI wake events to the elog. BRANCH=guybrush BUG=b:186792595 TEST=builds Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-09util/ifdtool/ifdtool.c: Clean upMaximilian Brune
- Remove functions that are only called in one place. - Add warning if user doesn't supply a platform, since that can lead to dumps/layouts that do not include all IFD regions without the user even reliazing it. - Inform the User if IFD or Flashmap is not found. - Inform the User if there is not a single match between FMAP and IFD region - Avoid printing usage if not specifically asked by the user. It tends to obfuscate the original error message. - Keep indentation consistent throughout the file. - Remove typedefs (coreboot coding style) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7bbce63ecb2e920530394766f58b5ea6f72852e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-09mb/google/skyrim: override winterhold PCIe configMartin Roth
Winterhold boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09mb/google/skyrim: drop link_hotplug from port descriptorsMatt DeVillier
These ports are not hot pluggable, so drop the parameter, which will result it in being set to zero / not enabled. BUG=none TEST=build boot skyrim, verify all PCIe devices functional. BRANCH=skyrim Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-09mb/google/skyrim: Enable L1 ASPM substates for PCIe devicesMatt DeVillier
Enable both L1.1 and L1.2 substates for the WiFi, SD card reader, and SSD (both NVMe and eMMC). If a given device does not support a particular substate, then it will not be enabled during PCIe enumeration by coreboot. BUG=b:270690572 TEST=build/boot multiple skyrim/whiterun/frostflow SKUs with different storage configs, verify WiFi/SD card/SSD all functional and have L1 substates enabled insofar as they are supported by the device. BRANCH=skyrim Change-Id: Ib84df8b9d97282ae696414e52c4a65cfb0a81194 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-09mb/google/skyrim: Allow port descriptors to be overriddenMartin Roth
This allows variants to override the skyrim port descriptors. BUG=None TEST=Tested with following patches BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09soc/intel/broadwell/gma: don't unconditionally remap all GPU PCI IDsFelix Held
This fixes the case where a Broadwell CPU is combined with an AMD or NVIDIA GPU would result in using the Broadwell GPU VBIOS file from CBFS for the discrete GPU too. A further improvement would be to use a list of the Intel iGPU PCI IDs like it is done in the Skylake code. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3eb50cb9a0539255d50e5cd8163f10c3a062cc4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73611 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09amdfwtool: move FW_MPIO to PSP Dir Level 2 where it belongsNikolai Vyssotski
Type 0x5d (MPIO Firmware) was mistakenly placed to PSP Level 1 directory. It should be in Level 2 PSP directory instead. Change-Id: Ic5ea00859f1055e0c91600c5f941c5d3acca36e2 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09soc/intel: Update API name `pmc_send_bios_reset_pci_enum_done`Subrata Banik
This patch updates PMC API name from `pmc_send_pci_enum_done` to `pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done is also set along with PMC enumeration being done. BUG=b:270942083 TEST=Able to build and boot google/rex. Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-09mb/google/dedede/var/kracko: Generate new SPD ID for new memory partsRobert Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:272173189 TEST=run part_id_gen to generate SPD id Change-Id: I141bda6eda3f658ca608c86ad0b320d018598514 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73554 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09amdfwtool: Support multiple inst entriesFred Reitberger
Use the inst field when adding entries to the psp tables. Otherwise, entries that differ by the inst field will appear as duplicates with an inst of 0. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4a84a0730976f4c65902b5c24ed13e21e95b03bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-09mb/google/brya/var/marasov: Half touch power-on delay to 150 msFrank Chu
Decrease Touch i2c delay during power-on sequence from 300 ms to 150 ms to make S0ix resume time meet requirement. BUG=b:264199989 TEST=Run the following test from chroot. test_that -b {BOARD_NAME} {device IP} f:.*power_UiResume/control Check seconds_system_resume value less than 500 msec Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ib81a9c1a90589b8b08e6ce6471db2abef96047ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/73532 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/asrock/b75pro3-m: Advertise RTL NIC as onboard ethernet deviceFabian Groffen
Move the onboard Realtek NIC definition to a child device of PCIe port 6. This makes sure it is advertised as "onboard", such that it appears as eno0 on systemd/udev-based systems. This commit is very similar to https://review.coreboot.org/c/coreboot/+/73516 Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I0550ee9faddd65011ad914aef413a6d1b316c5ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/73519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-08cpu/x86,amd: drop unused LOGICAL_CPUS Kconfig symbolFelix Held
The LOGICAL_CPUS Kconfig option is always true and also not user- configurable, so it can be dropped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4866de003058ec0f99495b405e26dfd7ba1fa28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08mb/google/skyrim: Enable SPL fusing on whiterun/winterholdMartin Roth
Enable whiterun/winterhold platforms to send the fuse SPL (security patch level) command to the PSP. BUG=b:254568112 TEST=On a platform that supports SPL fusing, a message indicating that fusing was requested will appear in the coreboot console log, followed by a puff of smoke when the fuse is set and the message "OK" again on the debug console. (Kidding about the smoke.) BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I45578597234ba672c89ac421b4626088faca27d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72914 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-08soc/amd/common/psp: Check more error bits before SPL fusingMartin Roth
This adds checks for three more error bits before requesting that the SPL fuses are updated. - While I'm here, I'm adding the include of types.h which was previously done through other include files, but should be done independently. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I87a7d40850c4e9ddbb2d1913c1588a919fdb29d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-08soc/amd/common/psp: Only set SPL fuses if an SPL file is presentMartin Roth
Use the presence of an SPL (Software Patch Level) file to trigger the function that reads and writes the SPL fuses. The current Kconfig option will be used to decide to write the fuses. This allows us to see the state of the SPL update bit which determines whether or not SPL fusing is allowed and needed before enabling the fusing. - Refactor a bit to prepare for following changes. - Update phrasing Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7bd2798b984673a4bd3c72f3cab52f1c9a786c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-08soc/amd: factor out ACPI_SSDT_PSD_INDEPENDENT to common AMD ACPI KconfigFelix Held
Now that the code using the ACPI_SSDT_PSD_INDEPENDENT Kconfig symbol is moved to soc/amd/common/block/acpi/cpu_power_state.c, also move the Kconfig symbol to the Kconfig file in this directory. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide18111df38d4e9c81f7d183f49107f382385d85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/common/block/acpi/cpu_power_state: introduce get_cstate_io_baseFelix Held
Introduce the get_cstate_io_base helper function that write_cstate_entry can call directly to get the C state control IO base address instead of having get_cstate_info pass this Io address to each write_cstate_entry call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I4cc80ded0a2fbc2dee9ca819e86284d9ffd58685 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.hFelix Held
The bit position of the P state enable bit in the 8 P state MSRs is identical for all AMD chips including the family 16h model 30h APU that lives outside of soc/amd. The other bits in those 8 MSRs are more or less family- and model-specific. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3064_81, previous version being 2523_80.. FSPM: 1. Addition of new UPDs SocTraceHubMode,SocTraceHubMemReg0Size SocTraceHubMemReg1Size. 2. Remove depricated UPD RDODTT. 3. Address offset changes. FSPS: 1. Address offset changes. FspUpd.h: 1.Corrected UPD signatures. BUG=b:TBD Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-08mb/google/rex: Rename touchscreen signals as per latest Rex schematicsEran Mitrani
Touchscreen signals were renamed for Rex schematics dated 21st Dec'22. This CL fixes the comments for those signals. BUG=b:263411413 TEST=None required (changed comments only) Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Ic40ef943d199d9f4a2bec9c0e6d4820224ef6adc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08soc/amd/*/acpi: factor out common get_pstate_info implementationFelix Held
The implementations of get_pstate_info of Picasso, Cezanne, Mendocino, Phoenix and Glinda are identical, so factor it out and move it to the common AMD SoC code. The SoC-specific get_pstate_core_freq and get_pstate_core_power functions remain in the SoC-specific code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe0494f1747f381a75b3dd71a8cc38fdc6dce042 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/*/acpi: factor out common generate_cpu_entries implementationFelix Held
With the exception of the generate_cppc_entries call, the implementations of generate_cpu_entries of Picasso, Cezanne, Mendocino, Phoenix and Glinda are identical, so factor it out and move it to the common AMD SoC code. Since all SoCs that support CPPC already select the SOC_AMD_COMMON_BLOCK_ACPI_CPPC Kconfig option, this can be used to only call generate_cppc_entries for platforms where it is available. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71323d9d071b6f9d82852479b60dc56c24f2b9ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/73504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/phoenix: Allow the amdfw.rom to be split into two partsZheng Bao
Split the big PSP FW data into two parts, head and body. The head needs to be located at original specific location. The body address is more flexible. So the big body will not cover other needed FWs like EC. Give the body a specific named AMDFWBODY, which should be defined in flashmap. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Ia8b318f71632a2c9b97ce67486374dc24d23e63e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/stoneyridge/romstage: pass C state control IO base addressFelix Held
Instead of hoping that the default the C state control IO address in binaryPI won't interfere with any other IO space usage in coreboot, assign the ACPI_CSTATE_CONTROL value to the CStateIoBaseAddress platform config structure element to make sure that binaryPI will use a known address for the IO port based C state control. binaryPI will write this address to the MSR_CSTATE_ADDRESS and will then also use these IO ports in the _CST packages in the PSTATE SSDT, so changing this won't cause a mismatch between those two. The default CStateIoBaseAddress in the FT4 Stoneyridge binaryPI used on Careena is 0x1770, so this didn't collide with any other IO space registers, but it's still much better to tell binaryPI which exact IO addresses to use. TEST=On Careena MSR_CSTATE_ADDRESS now contains the ACPI_CSTATE_CONTROL IO base address 0x420 and the PSTATE SSDT has the IO address 0x421 in the _CST package entry for the second C state which are both the expected values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I207202802427d4bf00f283bcbd83a174ab0a2846 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08amdfwtool: combo: Add combo feature for BIOS tableZheng Bao
It is similar to PSP combo. Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08amdfwtool: Separate two cases of combo and non-combo clearlyZheng Bao
If combo is used, fill the EFS header with address of COMBO header. If not, fill with address of PSP header. The old code fills with PSP headers all the time. Change-Id: I0057165aea553d9dc8e4e719e2804557229a0002 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66855 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08amdfwtool: combo: Create the combo header earlierZheng Bao
There will be a loop to set up the combo layout. The combo header only needs to be created once. This change is actually to move the creation of combo header outside of the loop. Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08amdfwtool: Move the filling of table headers into functionsZheng Bao
It is easier to understand what these statements are about. Change-Id: Ib02c68c9f2ea84020b12682c41fb1a6f8f93d725 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66852 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08mb/asrock/b75m-itx: Make NIC a child device below PCIe port 4Kevin Keijzer
The Realtek RTL8111E NIC is currently not defined as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp3s0 rather than eno0, as is appropriate for on-board ethernet devices. Additionally, the comment in devicetree.cb stating that PCIe port 6 is the ethernet controller is incorrect. It's actually port 4. This patch moves the comment to the right port, and defines the NIC as a child device of said port, so that it's properly defined as an on-board device. Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/TFWNW3Y7IWTFD4KIBVNQYW3DODJ6SSC2/ Change-Id: Ie1e3a757a6bd6c7dd1702ced177d13711978dcc4 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73516 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fabian Groffen <grobian@gentoo.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08soc/amd/glinda/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. The actual values in cstate_cfg_table haven't been checked against the reference code yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5157fc031c5b19d8633132222520f582620208c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/phoenix/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. The actual values in cstate_cfg_table haven't been checked against the reference code yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4f5743dd2e4dfdfeb3ffb2e9b964bdc75c84e6c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/mendocino/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3669c66094f0137081888ebdd1af838e2ea269b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/cezanne/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id97fcb74ff3d48994a3181d9c31cbbeb5a76c60a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/picasso/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6bd8879ce5968b24893b43041be98db55a4c3c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/common/block/acpi/cpu_power_state: use definition for bit_offsetFelix Held
Instead of using a magic constant in the bit_offset field of the C state resource for the C1 state that's entered via the MWAIT instruction, use the existing ACPI_FFIXEDHW_CLASS_MWAIT define. This value is checked by acpi_processor_ffh_cstate_probe in the Linux kernel. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9edc681efab15b5ceba91c8105f7dc6d687d8be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helperFelix Held
Introduce the get_cstate_info helper function that populates the caller- provided cstate_values array with the data returned by the SoC-specific get_cstate_config_data function. From the array get_cstate_config_data returns, only the ctype, latency and power fields are used, so the rest can be left uninitialized. Those 3 fields are compile-time constants. For each entry, write_cstate_entry will generate the corresponding resource information from the given data. In the C1 case where ctype is 1, the state is entered via a MWAIT instruction, while the higher C states are entered by doing an IO read from a specific IO address. This IO address is x - 1 bytes into the IO region starting at MSR_CSTATE_ADDRESS for the Cx state. So for example C2 is entered by reading from the C state IO base address + 1. This resource information is generated during runtime, since the contents of MSR_CSTATE_ADDRESS aren't necessarily known at compile-time. MAX_CSTATE_COUNT is introduced so that the caller can allocate and pass a buffer with space for the maximum number of C state entries. This maximum number corresponds to the number of IO addresses the CPU traps beginning from MSR_CSTATE_ADDRESS. In practice, it's unlikely that more than 3 or maybe 4 C states will be available though. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08mb/lenovo: Enable VBOOT_VBNV_FLASHYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for lenovo boards: t400, t410, t420, t420s, t430, t430s, t520, t530, x131e, x1_carbon_gen1, x60, x200, x201, x220, x230. A 0x2000 RW_NVRAM region is allocated for them, with the COREBOOT size reduced by 0x2000. Also remove the VBOOT_VBNV_OFFSET config, since it's only used for VBOOT_VBNV_CMOS. [1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1 BUG=b:235293589 TEST=./util/abuild/abuild -t LENOVO_T430S -a # with VBOOT enabled Change-Id: I7e29db7eeceec499fbbcf902a26bfe9a2076de40 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08mb/google/brask/var/constitution: update gpio settingsMorris Hsu
Remove GPP_D11,GPP_D12 in ramstage, follow baseboard brask setting. TEST=emerge-brask coreboot make sure HDMIA can display Change-Id: I953170f006699e3dc9d6111ded8234f66b9162c7 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-08mb/{brya,hdaes}/include/ec: Add EC_HOST_EVENT_GPUTarun Tuli
EC_HOST_EVENT_GPU was renamed from EC_HOST_EVENT_USB_CHARGER and thought to no longer be used. It was subsequently removed in I9e3e0e9b45385766343489ae2d8fc43fb0954923 Add back the mask for this event as it is infact required on certain Brya (Agah) and Hades variants. Signed-off-by: Tarun Tuli <taruntuli@google.com> BUG=b:216485035,b:258126464,b:266631157 BRANCH=none TEST=D-notifier events are received again from EC Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73217 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-08mb/google/nissa/var/craask: Extend sd_hold for touchpad/touchscreenTyler Wang
Extend sd_hold to meet touchpad/touchscreen SPEC. touchscreen: tHD > 100 ns touchpad: 900 ns > tHD > 300 ns After applied the change, the tHD meets reqirement. touchscreen: 35 ns --> 260 ns touchpad: 43 ns --> 368 ns BUG=b:271524470 TEST=build and measure the timing meet SPEC Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iec2f72da80ffe8d4dd494caabbe1a97e52a81e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-03-07mb/google/hades: Change memory to SODIMMEric Lai
Add SODIMM support, drop the solderdown based on schematics. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I85ec79c3d8f1147a875c4d04017bb50347121ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-07soc/intel/xeon_sp: Add PM definition for SPR-SPDavid Hendricks
Change-Id: I13ed156a1b967e87fa30b1867feed03c3d17b992 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-07soc/intel/adl: Increase MAX_CPUS to 32 for RPLTim Crawford
Raptor Lake i9 CPUs have 8P+16E cores for a total of 32 threads. Change-Id: I26a729a585e7dc14f38c9092056eb0280726f053 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73514 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-07util/lint: Ignore braces around single line statementsMartin Roth
In a recent coreboot leadership meeting, the decision was made to allow (but not require) braces around single line statements if the author wishes to put them in. This patch removes the checks for single line statement blocks, while still checking for other issues in braces. Just because they're allowed now, please do not reformat the entire codebase to add them. coreboot has a policy of not making widespread changes to the entire codebase unless something actually violates the style guidelines. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I137b10889ec880959c4c1b035dc54bf8ebf32488 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73515 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-07device/xhci: Add struct for capability registersRobert Zieba
The XHCI code does not currently contain a structure that corresponds to the XHCI capability registers. These registers contain various useful information about the controller. Create a`xhci_capability_regs` struct to address this. BRANCH=guybrush BUG=b:186792595 TEST=builds Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-07libpayload: strings.h: Use builtin __ffs instead of included oneThomas Heijligen
Change-Id: Ie4d0b1b19ce6524341449df8bfabc66bff7bd97e Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70118 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-03-07libpayload: bin/lpgcc allow to call without filesThomas Heijligen
When building libflashrom ontop of libpayload, meson calls the lpgcc wrapper with -xc but without a file to obtain information about the C compiler. To make this work guard $_LIBGCC with -xnone in the lpgcc wrapper. -xnone tells the compiler to interpret the following files of libpayload by their suffix, not the privious given -x option. Change-Id: I9e037ff44c0a6d0585d8a6f8aeabae6e651142e2 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70117 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-03-07soc/amd/stoneyridge: request binaryPI to use \_SB_ scope in PSTATE SSDTFelix Held
Instead of having binaryPI generate a PSTATE SSDT that uses \_PR_ as the scope for the CPU objects and patching this SSDT in coreboot to use the \_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the \_SB_ scope instead by setting the late platform configuration option ProcessorScopeInSb to true. TEST=Careena still boots and Linux doesn't show any ACPI errors with this patch applied. With only patch_ssdt_processor_scope removed, but the ProcessorScopeInSb option not set, Linux will complain that it can't resolve the \PR.P00x symbols. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If88820a0f5df923f129e2e3b5335f5f0e38ee7f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-07drivers/intel/fsp2_0: Print `mrc_cache` size in decimalSubrata Banik
This patch updates the print msg of mrc_cache size from hex to decimal for easier understanding while debugging the issue. TEST=Able to build and boot google/rex. Without this patch: [SPEW ] MRC cache found, size ee75 With this patch: [SPEW ] MRC cache found, size 61045 bytes Change-Id: I69feeb36423e47a5992c9f27d9a7042803a492cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-03-07mb/google/geralt: Set +-5.7V to TPS65132s EEPROMyangcong
It is necessary to increase the AVDD/AVEE of TPS65132s PMIC to +-5.7V for powering on BOE_TV110C9M_LL0. So we set the default value to +-5.7V and program the value to the EEPROM when configuring the display at the first time. In this way, TPS65132s could load the correct setting from the EEPROM after booting into kernel. BUG=b:268292556 TEST=test firmware display pass and AVDD/AVEE is +-5.7V on Geralt. Change-Id: I29236818444cac84d42386a371cd8934048ff948 Signed-off-by: yangcong <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73443 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-03-07mb/google/skyrim: Move SPL setting to variantsChris Wang
Move the sustained_power_limit_mW setting from the baseboard to variants. This setting will be needed before STT is enabled, but once STT is enabled, this setting should be removed. BUG=b:265267957 BRANCH=none TEST=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I7b9779600cfa8c7581732e936a714728fd618d20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-07mb/google/brya/var/taeko: Enable Fast VMode for taekoJoey Peng
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:270242461 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I82c2016d9dfb39ff7b372815737d4ae62875340c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73373 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-07mb/google/brya/var/taeko: use RPL FSP headersJoey Peng
To support an RPL SKU on taeko, taeko must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for taeko so that it will use the RPL FSP headers for taeko. BUG=b:270242461 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot taeko to kernel. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Cq-Depend: chrome-internal:5544049, chromium:4302529 Change-Id: Ic97400555dabb237325e7c4a8d5edcbb4779cdb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-06mb/asrock/b75m-itx: Add Sandy/Ivy Bridge board B75M-ITXFabian Groffen
This board is based off b75pro3-m, which is very similar. Compared to it, it just lacks a COM1 header, and the secondary ASMedia SATA3 controller. Tested with: CPUs: - Core i5-3330 - Core i5-3470 - Core i7-3770 RAM: - single bank 4GB CL11 - two banks 4+4GB CL9 - two banks 8+8GB CL10 OS: - Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72) Working: - GRUB2 payload with embedded default config for boot from USB, disk - UEFI EDK2 payload - Intel ME stripped - Native raminit - Integrated graphics with libgfxinit (HDMI, DVI and VGA) - (boot from) SATA2, SATA3, ports - Rear USB 2 and 3 ports (supports boot) - Internal USB 3.0 ports - Realtek GbE NIC - 2.0 channel audio via lineout jack output - ACPI (power button triggers OS event) Untested: - Internal USB 2.0 ports - eSATA port - 7.1 channel audio Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ia6a6eb3e922920f4afbcb7828cd2b779b9caebcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73097 Reviewed-by: Kevin Keijzer Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-06soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUsFelix Held
The legacy ACPI CPU control registers in IO space where the first 4 IO locations control the CPU throttling value don't exist any more on the Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS in set_cstate_io_addr which will cause accesses from the 8 IO addresses beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads from those IO addresses will cause the CPU to enter low C states. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/picasso/include/iomap: add comment about ACPI IO assignmentFelix Held
Finally figured out why ACPI_GPE0_BLK only being 4 bytes after ACPI_CPU_CONTROL won't work and its due to the CPU trapping 8 IO addresses from ACPI_CPU_CONTROL on for C state control. This is set up in set_cstate_io_addr by writing the ACPI_CPU_CONTROL value into MSR_CSTATE_ADDRESS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedf53bbdae6ca65224601aad5cd1163df4b54131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL defineFelix Held
Picasso and newer don't implement the P_CNT register to control the CPU duty cycle and also trap the C state control IO addresses directly in the CPU, so those won't reach the FCH. This register is unused in the Picasso code and not even defined any more in the Cezanne PPR. The Picasso PPR does define this register, but since it's useless and might even just be a leftover form a pre-Zen CPU generation, drop the define. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/*/acpi: drop unnecessary duty_offset/duty_width field writesFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the duty_offset and duty_width FADT field in acpi_fill_fadt for all SoC except Stoneyridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib63b24891d44298841153dfc500b030619e1a5ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/73421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/picasso/acpi: don't announce unimplemented duty cycle controlFelix Held
Picasso neither has the corresponding P_CNT register implemented nor writes a _PTC ACPI object that would specify the P_CNT register. The Picasso UEFI reference code also sets the duty_width FADT entry to 0. This also aligns the Picasso code with the Cezanne code in this regard. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I74645e5c4e54a2ad6bc7f9e72f5f656027a79860 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/*/acpi: drop unneeded pstate_cnt FADT assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the pstate_cnt FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If3ddb466de1d437361d811e45e328a1dbff02fcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/73419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/*/acpi: drop unneeded mon_alrm FADT assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the mon_alrm FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabb5fc7367f1e4e7acea1a58abdb643fc46ca776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06Documentation/sbom: Add SBOM DocumentationMaximilian Brune
Change-Id: I39fbcba60a0fbdbed9f662119ed7692c0a0fd30e Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-05mb/asrock/b75pro3-m: Add CMOS layout/defaults and vbt.binKevin Keijzer
The ASRock B75 Pro3-M port was lacking a cmos.default and cmos.layout, which means nvramtool could not be used to change any nvram values, and the defaults were always being used. I have "borrowed" the files from the similar h77pro4-m port, which work fine for the b75pro3-m. I can now adjust things like gfx_uma_size and power_on_after_fail, which are quite useful to be able to modify. Additionally, this board did not have a data.vbt, so I extracted vbt.bin from the VGABIOS and added it. Change-Id: I40822f2f7b013b7ac0658d66d7972b447066d593 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73451 Reviewed-by: Fabian Groffen <grobian@gentoo.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-05mb/asrock/b75pro3-m: Fix S3 resume and hardware monitoringKevin Keijzer
On the ASRock B75 Pro3-M, resuming from S3 has always been broken; see commit 928c6c6336f2 (mainboard/asrock: add ASRock B75 Pro3-M). This was because 3VSBSW# was not enabled during S3, causing the board to reboot instead of resume. This change enables 3VSBSW# during S3, which leads to S3 resume working normally. Another issue with this board was that hardware monitoring was not working. The nct6775 Linux kernel module could not be loaded, due to the device having a base I/O port of 0. This change also enables the Super I/O properly, so that sensors-detect can find the sensor and the kernel module can be used. Change-Id: I6e504fe4b60da1d7b9830bea5029101bb8cebcb5 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73450 Reviewed-by: Fabian Groffen <grobian@gentoo.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-05mb/google/skyrim: Disable cardbus supportMartin Roth
Skyrim does not have a cardbus socket, so disable it. Maybe cardbus support shouldn't be enabled by default? BUG=None TEST="PC Card (PCMCIA) is supported" no longer shows up in dmidecode output. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic941b075e8b5082b5e61e728a77fd79c0ebba35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05skyrim/overridetree.cb: Remove gpio_keys ACPI nodeTim Van Patten
Only Frostflow supports the stylus, so remove the gpio-keys ACPI node from Skyrim. The Kconfig value DRIVERS_GENERIC_GPIO_KEYS is still enabled for all Skyrim variants, since coreboot will drop the driver from the BIOS image if there are no references to it (in the devicetree). If some other design ends up using the stylus in the future we won't have to bring it back. BUG: none TEST: build_packages --board=skyrim chromeos-bootimage --autosetgov Change-Id: I9ffe215741b72b678d74405769f35167d8ded4b5 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-05mb/google/geralt: Add NAU8318 support for GeraltTrevor Wu
Add a config "USE_NAU8318" to enable NAU8318 support. NAU8318 is another speaker used in Geralt. NAU8318 supports beep function via GPIO control. So we configure the GPIO pins and pass them to the payload. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I21009a20809f398de4628ff0c11bcbd0e7591443 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73413 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/geralt: Add MAX98390 support for GeraltTrevor Wu
Add a config "USE_MAX98390" to enable MAX98390 support. MAX98390 is an I2S smart amplifier used in Geralt. It is also the default speaker for Geralt reference board. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73412 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/geralt: Add mtcmos bus protection for displayLiju-Clr Chen
Enable bus protection for display to avoid bus hang and incomplete bus transaction. BUG=b:264204465 TEST=test firmware and kernel display pass for MIPI panel on geralt. Change-Id: Iac61a69f2b84966dd468442daaa59d83eec775aa Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73411 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/hades: Add baseboard device treeEric Lai
Add minimum device tree. Leave IOs default disable to optimize variant override complexity. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-05soc/mediatek/mt8188: Add bus protection for audio/video mtcmosgarmin chang
Bus protection is a HW mechanism to avoid bus hang and incomplete bus transactions. Bus protection HW must be enabled while the receiver of the transaction is not able to respond. BUG=b:264204465 TEST=build pass Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Signed-off-by: garmin chang <garmin.chang@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73375 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-05device/xhci: Add functions to work with resource pointersRobert Zieba
The XHCI device functions currently use functions that require a access to the device tree. Create variant of these functions that can operate with a resource* as an argument and refactor the existing device*-based functions to operate by calling the resource*-based variants. This is useful for stages like SMM that may not have access to the device tree. BRANCH=guybrush BUG=b:186792595 TEST=Ran on skyrim device, verified that XHCI ACPI tables are still generated correctly. Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05cpu/x86/smm: Add PCI resource store functionalityRobert Zieba
In certain cases data within protected memmory areas like SMRAM could be leaked or modified if an attacker remaps PCI BARs to point within that area. Add support to the existing SMM runtime to allow storing PCI resources in SMRAM and then later retrieving them. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05soc/intel/alderlake: Hook up ucode for RPL-P/H/UTim Crawford
Hook up microcode from 3rdparty repo for: - 06-ba-02 (CPUID signature: 0xb06a2) Change-Id: Icb2fc9350ebc33ef150f1ab5df1006ed956478d6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-04lint/lint-stable-003-whitespace: Fix excludelistMaximilian Brune
Remove the last slash '/' from directories in excludelist, so that they will be correctly filtered by grep. Fixes: grep: util/goswid: Is a directory grep: util/nvidia/cbootimage: Is a directory Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I90cc2cff9a98bbd0af344156332b970bfd6430b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-03-04mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su
Add new ram_id:0011 for Hynix H58G56BK8BX068. Add new ram_id:0100 for Hynix H58G66BK8BX067. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) H58G66BK8BX067 4 (0100) BUG=b:270629852 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73252 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-04spd/lp5: Modify Hynix LPDDR5X memory SpeedJohn Su
Because SPD tool now supports 8533Mbps, so modify speed to regenerate the SPD file for Hynix H58G66BK8BX067 and H58G56BK8BX068. BUG=b:263189532, b:270629852 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73251 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-04mb/google/skyrim/var/frostflow: Update DPTC and STT settingsFrank Wu
According to thermal_table_0215, adjust DPTC and STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04soc/amd/mendocino: Add STT support for dptc tablet modeChris Wang
Add stt settings for dptc tablet mode. BUG=b:257149501 BRANCH=None TEST=Check if the STT value matches the clamshell/tablet mode. Run the WebGL aquarium with 5000 fish and verify that there is no power drop peak. Change-Id: Ib4aad3af8761b20084717b15a462edf4704b83cc Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73205 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-04soc/amd/mendocino: Remove the SPL DPTC parameterChris Wang
The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-03-04xeon/spr: Set ACPI CPU string for 12bitNaresh Solanki
On platforms with more than 255 cores the ACPI CPU string would overflow and generate duplicates. Fix that by changing the string to hex and use 3 digits. Test: Able to boot without ACPI errors on IBM/SBP1 which has 384 actives cores. Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-04mb/system76/adl-p: Add Oryx Pro 10 as a variantTim Crawford
oryp10 is nearly identical to the oryp9, with the differences being: - Uses DDR5 RAM instead of DDR4 RAM - Uses Realtek ALC1306 instead of TI TAS5825M - Has an option for OLED display Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/adl: Add Oryx Pro 9 as a variantTim Crawford
The Oryx Pro 9 (oryp9) is an Alder Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - Both M.2 NVME SSD slots (with MZVL2500HCJQ) - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - Discrete/Hybrid graphics - HDMI output (requires NVIDIA GPU) - Mini DisplayPort output (requires NVIDIA GPU) - Detection of devices in TBT slot on boot Change-Id: I8aac3e83f4423f444cb9ce8aa562ba465eb718c1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04soc/intel/alderlake: Allow channel 0 for memory-downTim Crawford
Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the System76 Lemur Pro 11 (lemp11). Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/adl: Add Lemur Pro 11 as a variantTim Crawford
The Lemur Pro 11 (lemp11) is an Alder Lake-U board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - DIMM slot (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - M.2 SATA SSD (with WDS100T2B0B) - All USB ports - SD card reader - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - On-board RAM: Requires CB:65567 - Detection of devices in TBT slot on boot Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/google/brask/var/moli: Allow USB2/3 wakeups to (un)plug events in dtScott Chao
BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I1c8daf62dabe674a39b1416d886f9e470ae23a5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73174 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04soc/intel/alderlake: Add UWES ASL into xhci.aslScott Chao
Align support for enable wake-on-usb attach/detach as was introduced in Cannon Lake in commit 811284125f0a ("soc/intel/cannonlake: Add UWES ASL into xhci.asl"). This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <Scott_Chao@wistron.com> Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-04security/tpm: add TPM log format as per 2.0 specSergii Dmytruk
Used by default for all boards with TPM2 which don't specify log format explicitly. Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Ticket: https://ticket.coreboot.org/issues/422 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-03-04security/tpm: add TPM log format as per 1.2 specSergii Dmytruk
Used by default for all boards with TPM1 which don't specify log format explicitly. Ticket: https://ticket.coreboot.org/issues/423 Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-03-04mb/system76: Add custom backlight levels for Intel GMATim Crawford
Add custom backlight levels for all models except: - addw1/addw2: Uses an OLED display - bonw14: Does not use the iGPU Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/tgl-u: Leave TBT LSX0 as FSP configuredTim Crawford
Do not reconfigured LSX0 so that the FSP values are used. Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04{ec,mb}/system76: Move smbios_system_wakeup_typeTim Crawford
Move the implementation of smbios_system_wakeup_type from the mainboards to the EC for all models that use System76 EC (everything except KBL). Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/google/brya: remove the skolas baseboardNick Vaccaro
The skolas baseboard is no longer needed, so this change removes the baseboard files for skolas and adjusts the config settings to that variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE. BUG=b:271470530 TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin onto a skolas and verify it boots to kernel. Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-03soc/amd/cezanne/graphics: simplify map_oprom_vendev implementationFelix Held
Phoenix' implementation of map_oprom_vendev uses this simplified implementation, so port this back to Cezanne too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0aa3a0fed37c6cba15a668ada639f5fd0c212d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73387 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-03mb/google/skyrim: Disable USE_SELECTIVE_GOP_INITMartin Roth
This is causing some issues, so disable it until those issues can be resolved. BUG=b:271437658, b:271199389, b:270077971 TEST=Screen always lights up on boot & after S0i3 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-03acpi: Add SRAT x2APIC table supportNaresh Solanki
For platforms using X2APIC mode add SRAT x2APIC table generation. This allows to setup proper SRAT tables. Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-03soc/intel/xeon_sp: Fix CBMEM corruptionPatrick Rudolph
On the 4 socket IBM/SBP1 platform with 384 cores lots of space for ACPI tables is required. Bump MAX_ACPI_TABLE_SIZE_KB to 400 to fix CBMEM corruption. Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>