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2021-05-30mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110Werner Zeh
Already released Linux versions did not have the needed ACPI-extension in the RTC driver. If the ACPI-Support is enabled for the RTC, this older Linux will not be able to use this device as it will be claimed by the PNP-drivers. As there is no way to avoid that an older Linux kernel meets a newer coreboot in the field, we need to disable the ACPI support for the RTC for the mc_apl-based mainboards. Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55004 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI supportWerner Zeh
In commit b64db833d6 a basic ACPI support was added to the driver. With this support an SSDT-entry is created for this RTC and it is now visible to the OS via ACPI. In Linux the PNP-devices, which are reported over ACPI, are scanned rather early and if the entry is found, the device is claimed even if there is no driver available yet. In this case, when the native RTC-driver without ACPI-support is loaded and tries to register this device, the RTC is already blocked by the PNP-drivers and cannot be used anymore. This leads to a non-usable RTC on kernels where the needed ACPI-extension is not yet merged into the RTC driver. This patch provides a way to disable the ACPI-support for the RTC if needed. Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55003 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30cpu/x86/smm: Fix u32 type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:415:42: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'u32' {aka 'unsigned int'} [-Werror=format=] 415 | printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", | ~~^ | | | long unsigned int | %x 416 | __func__, stub_params->stack_top - total_stack_size); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | u32 {aka unsigned int} The size of `size_t` differs between i386-elf (32-bit) and x86_64-elf/x86_64-linux-gnu (64-bit). Unfortunately, coreboot hardcodes src/include/inttypes.h:#define PRIx32 "x" so `PRIx32` cannot be used. There use `z` as length modifier, as size_t should be always big enough to hold the value. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-30cpu/x86/smm: Fix size_t type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_module_setup_stub': src/cpu/x86/smm/smm_module_loader.c:360:70: error: format '%lx' expects argument of type 'long unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=] 360 | printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", | ~~^ | | | long unsigned int | %x As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `l` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. So, use the correct length modifier `z` for the type `size_t`. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I4172e0f4dc40437250da89b7720a5c1e5fbab709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-30cpu/x86/smm: Fix uintptr_t type mismatches in print statementsPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_create_map': src/cpu/x86/smm/smm_module_loader.c:146:19: error: format '%zx' expects argument of type 'size_t', but argument 3 has type 'uintptr_t' {aka 'long unsigned int'} [-Werror=format=] 146 | " smbase %zx entry %zx\n", | ~~^ | | | unsigned int | %lx 147 | cpus[i].smbase, cpus[i].entry); | ~~~~~~~~~~~~~~ | | | uintptr_t {aka long unsigned int} In coreboot `uintptr_t` is defined in `src/include/stdint.h`: typedef unsigned long uintptr_t; As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `z` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. Normally, `PRIxPTR` would need to be used as a length modifier, but as coreboot always defines `uintptr_t` to `unsigned long` (and in `src/include/inttypes.h` also defines `PRIxPTR` as `"lx"`), use the length modifier `l` to make the code more readable. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I32bff397c8a033fe34390e6c1a7dfe773707a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-30mb/intel/adlrvp_m: add ec device entry to devicetreeBora Guvendik
TEST=Boot to OS and verify acpi tables. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/intel/alderlake: Add placeholder SPD fileTim Wawrzynczak
Change-Id: I38eb4bb684c511fff5ae148091c066682e9c35cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-30Update vboot submodule to upstream mainDaisuke Nojiri
Updating from commit id e681c37: change node locked version expectations to commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55026 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30mb/siemens/mc_apl1: Move gpio.c from baseboard to mc_apl1Mario Scheithauer
Variant mc_apl1 is the only one that uses gpio.c from baseboard. For this reason, gpio.c is moved from baseboard to mc_apl1. Change-Id: Ie2ba8181dfe887df9abbbd648f2cbdc6ffc65530 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-30mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configurationMario Scheithauer
With commit 405f229689 (soc/intel/*: drop UART pad configuration from common code) the UART pad configuration was dropped from common SoC code. Through a second commit 5ff17ed393 (mb/siemens/mc_apl1: do UART pad configuration at board-level) the UART pad configuration was made for mc_apl1 baseboard. This change is also needed for all other mc_apl boards. Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-30arch/x86/acpi_bert_storage: change return type of bert_errors_presentFelix Held
The return value is a boolean, so use the bool type. Also add the types.h header to have the bool type defined. Also change type of bert_region_broken static variable to bool. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-30soc/intel/elkhartlake: Update FADT tableTan, Lean Sheng
Update FADT table per relevant PM settings: Fix PM Timer block access size and disable C2 and C3 states for the CPU. Further on, set the century byte offset in FADT to point to the common location in CMOS. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54958 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/intel/elkhartlake: Update FSP-M UPD related configsTan, Lean Sheng
Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-30Apply more uses for Kconfig TPMKyösti Mälkki
Change-Id: I54b296563940cd46fe9da9fe789b746f2fc1987d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-29drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function staticSubrata Banik
fsp_temp_ram_exit() function is only getting called by late_car_teardown() function inside temp_ram_exit.c file. Hence, make function as static and removed from include/fsp/api.h. Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-28mb/kontron/mal10: Use mainboard_ops driver for GPIO configurationFelix Singer
`mainboard_silicon_init_params()` should *only* be used for configuring FSP options which can not be configured anywhere else. Therefore, use the init phase from the mainboard_ops driver for configuring the GPIOs. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ia01091938ac113cb5cf95f046609a1ebf3620806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48143 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger LakeSrinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4133 to include post PRQ UPDs. BUG=b:188452018 BRANCH=none TEST=build voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28arch/x86/timestamp.inc: Remove unused fileArthur Heymans
This is a romcc compiled bootblock leftover. Change-Id: I8d4f8bcdac7e15d60540157e9d2ac98603320977 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55007 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/google/volteer/var/collis: Update DPTF parametersFrankChu
Update the first version DPTF parameters received from the thermal team. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Cq-Depend: chrome-internal:3851737 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28mb/google/dedede: Update Storo setting for PEN detection.Zanxi Chen
Update devicetree and gpio driving of storo that enable stylus Updates the GPIO configuration for GPP_C12 to PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to use WAKEUP_ROUTE_GPIO_IRQ. BUG=b:188519508,b:188365033 BRANCH=dedede TEST=build bios and the pen behavior can be detected. Change-Id: I2ffc969569b3ca29ba76326140f958a9707199f7 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54762 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/amd/bilby,cereme,mandolin: change PSPP policy to balancedFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7571ed92b3c3fa79581e2c7342960ca31451af1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-28Documentation: Fix up toctreePatrick Georgi
Some files weren't properly hooked up, making Sphinx complain. Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55020 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28Documentation: Fix named linkPatrick Georgi
The syntax requires two bracketed fields. Change-Id: I98ebe714e57f50017755eed7888f0dd2637a3066 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-28soc/amd/picasso: fix MCACHE on psp_verstage RO bootKangheui Won
On RW boot path psp_verstage call cbfs_map which calls chain of _cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then cbfs_get_boot_device initializes MCACHE which is used later. However on RO boot path psp_verstage doesn't try to find anything in the CBFS which results RO MCACHE not to be initialized. Add cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery boot. BUG=b:177091575 BRANCH=none TEST=build and boot jelboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28Documentation: Update real time chat optionsPatrick Georgi
Change-Id: I3035266c5e035b954c0d709bd2c09069128c3340 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55010 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/prodrive/hermes: Rename EEPROM access functionsAngel Pons
Change-Id: I84b9ef080f1ac91ea6f7273457b882677abf70d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52885 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/prodrive/hermes: Simplify `read_write_config` signatureAngel Pons
The `write_offset` parameter is always zero. Remove it. Change-Id: Ib63cb25904ad6c1c7424a9c01d8bf1e84c08453b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52884 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28option: Allow mainboards to implement the APIAngel Pons
Some mainboards need a mainboard-specific mechanism to access option values. Allow mainboards to implement the option API. Also, add some documentation about the current option API, and describe when should one reimplement the option API in mainboard code: only when the code is mainboard-specific to comply with externally-imposed constraints. Change-Id: Idccdb9a008b1ebb89821961659f27b1c0b17d29c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28option: Turn CMOS option backend into choiceAngel Pons
In order to add more option backends, transform the current CMOS option backend into a Kconfig choice. Replace the `select` directives, as they cannot be used with choice options. Change-Id: Id3180e9991f0e763b4bae93a92d40668e7fc99bc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28nb/intel/x4x/rcven.c: Guard macro parametersAngel Pons
Add parentheses around macro parameters to avoid operation order issues. Change-Id: I9528f3d6b221854fddd2db6d2b45c63bfdda0092 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54953 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28ec/kontron/kempld: Guard macro parametersAngel Pons
Add parentheses around macro parameters to avoid operation order issues. Change-Id: I2d4552abaeda5702619cc53e9dfae1f17b048e67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28cpu/x86/entry16.S: Make Intel CBnT TOCTOU safeArthur Heymans
Intel CBnT (and Boot Guard) makes the chain of trust TOCTOU safe by setting up NEM (non eviction mode) in the ACM. The CBnT IBB (Initial BootBlock) therefore should not disable caching. Sidenote: the MSR macros are taken from the slimbootloader project. TESTED: ocp/Deltalake boot with and without CBnT and also a broken CBnT setup. Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-28mb/intel/adlrvp_m: Disable unused TBT ports from device treeBernardo Perez Priego
These PCIe and DMA ports are not available for adlrvp_m. BUG=none TEST=Boot device Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28mainboard/google/brya: Add S3/S0ix wake events AC connect/disconnectmadhusudanarao amara
Enabling AC connect/disconnect wake events in brya to meet Chrome OS wake requirements. These changes are similar to Volteer and Shadowmountain. BUG=none BRANCH=None TEST=manual tested DUT wakes for AC connect/disconnect in S0ix Change-Id: I14b3efd429e3aa701af534f150baf35fcdeb9f35 Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54855 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28ec/google/wilco: Extend description of `EC_GOOGLE_WILCO`Paul Menzel
Change-Id: Ia278b538a8904651d16c37d095972fa78e264288 Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/7S5OJMLQUEIU6YK36JTTRINF5OOCI66V/ Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-28mb/intel/ehlcrb: Upload EHL CRB GPIO configsTan, Lean Sheng
Initial upload of the GPIO configs for EHL CRB. This CL also includes the UART GPIO configs in early GPIO table. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-27cbmem: Introduce "early" init hooks for consoleJulius Werner
Over the last couple of years we have continuously added more and more CBMEM init hooks related to different independent components. One disadvantage of the API is that it can not model any dependencies between the different hooks, and their order is essentially undefined (based on link order). For most hooks this is not a problem, and in fact it's probably not a bad thing to discourage implicit dependencies between unrelated components like this... but one resource the components obviously all share is CBMEM, and since many CBMEM init hooks are used to create new CBMEM areas, the arbitrary order means that the order of these areas becomes unpredictable. Generally code using CBMEM should not care where exactly an area is allocated, but one exception is the persistent CBMEM console which relies (on a best effort basis) on always getting allocated at the same address on every boot. This is, technically, a hack, but it's a pretty harmless hack that has served us reasonably well so far and would be difficult to realize in a more robust way (without adding a lot of new infrastructure). Most of the time, coreboot will allocate the same CBMEM areas in the same order with the same sizes on every boot, and this all kinda works out (and since it's only a debug console, we don't need to be afraid of the odd one-in-a-million edge case breaking it). But one reproducible difference we can have between boots is the vboot boot mode (e.g. normal vs. recovery boot), and we had just kinda gotten lucky in the past that we didn't have differences in CBMEM allocations in different boot modes. With the recent addition of the RW_MCACHE (which does not get allocated in recovery mode), this is no longer true, and as a result CBMEM consoles can no longer persist between normal and recovery modes. The somewhat kludgy but simple solution is to just create a new class of specifically "early" CBMEM init hooks that will always run before all the others. While arbitrarily partitioning hooks into "early" and "not early" without any precise definition of what these things mean may seem a bit haphazard, I think it will be good enough in practice for the very few cases where this matters and beats building anything much more complicated (FWIW Linux has been doing something similar for years with device suspend/resume ordering). Since the current use case only relates to CBMEM allocation ordering and you can only really be "first" if you allocate in romstage, the "early" hook is only available in romstage for now (could be expanded later if we find a use case for it). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2c849a89f07a87d448ec1edbad4ce404afb0746 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-27tpm: Remove USER_TPMx options, make TPM1/TPM2 menuconfig visibleJulius Werner
We would like to have an easy way to completely disable TPM support on a board. For boards that don't pre-select a TPM protocol via the MAINBOARD_HAS_TPMx options, this is already possible with the USER_NO_TPM option. In order to make this available for all boards, this patch just removes the whole USER_TPMx option group and directly makes the TPM1 and TPM2 options visible to menuconfig. The MAINBOARD_HAS_TPMx options can still be used to select defaults and to prevent selection of a protocol that the TPM is known to not support, but the NO_TPM option always remains available. Also fix some mainboards that selected TPM2 directly, which they're not supposed to do (that's what MAINBOARD_HAS_TPM2 is for), and add a missing dependency to TPM_CR50 so it is set correctly for a NO_TPM scenario. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib0a73da3c42fa4e8deffecb53f29ee38cbb51a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-27mb/amd/majolica: enable crypto coprocessor PCIe deviceFelix Held
This fixes the following error from the Linux kernel: ccp 0000:03:00.2: ioremap failed ccp 0000:03:00.2: initialization failed ccp: probe of 0000:03:00.2 failed with error -12 BUG=b:186575712,b:189202985 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c6a6cbbdda2cb22e81e2b52b364617d6765e09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54963 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27mb/google/guybrush,mancomb: enable crypto coprocessor PCIe deviceFelix Held
This fixes the following error from the Linux kernel: ccp 0000:03:00.2: ioremap failed ccp 0000:03:00.2: initialization failed ccp: probe of 0000:03:00.2 failed with error -12 BUG=b:186575712,b:189202985 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5cbc620001d3c21c538b62ab2811b6e07269feb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54962 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/amd/common/block: Fix missing include in acp.hRaul E Rangel
We were missing the stdint.h header, and the header was sorted incorrectly in chip.h BUG=non TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I209d3c9c48e5b06b2a56759af51cf2858eb99f51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27Mancomb: Add firmware config CBI definitionsMartin Roth
The firmware config field in CBI lets us control initialization parameters based on the OEM design. BUG=b:188713024 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I56ddc7218688919f20f41e0f143419c39d83849d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-27soc/amd/picasso: add devicetree setting for PSPP policyFelix Held
Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-27drivers/intel/fsp1_1: Drop empty weak functionsAngel Pons
The only FSP 1.1 platform is Braswell. Drop unnecessary functions which only have a weak stub definition. Change-Id: Ie60213e5a6ae67bd8b982ee505f4b512253577c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-05-27lib/hexdump: remove hexdump32 and use hexdump insteadFelix Held
hexdump and hexdump32 do similar things, but hexdump32 is mostly a reimplementation that has additional support to configure the console log level, but has a very unexpected len parameter that isn't in bytes, but in DWORDs. With the move to hexdump() the console log level for the hexdump is changed to BIOS_DEBUG. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6138d17f0ce8e4a14f22d132bf5c64d0c343b80d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54925 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27drivers/intel/fsp1_1: Drop weak function definitionAngel Pons
The only FSP 1.1 platform is Braswell, which has a non-weak definition for the `soc_silicon_init_params` function. This changes the resulting BUILD_TIMELESS=1 coreboot image for Facebook fbg1701, for some reason. Change-Id: I2a1b51cda9eb21d7af8372c16a43195a4bdd9543 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27drivers/intel/fsp1_1: Drop unused weak definitionsAngel Pons
The only FSP 1.1 platform is Braswell. Drop unused weak definitions for functions where a non-weak definition always exists. Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: Ifaf40a1cd661b123911fbeaafeb2b7002559a435 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27drivers/intel/fsp1_1: Drop some MMA leftoversAngel Pons
Commit 736a1028fbaef97d32221cadb1f512c9a8960a76 (drivers/intel/fsp1_1: Drop dead MMA code) dropped FSP 1.1 MMA code, but missed a few things. Change-Id: I556e7125eff21c49609bb1e5e1f23e99e692756f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27mb/google/mancomb: set PSPP policy to balancedFelix Held
Not sure which policy we should select here or if that should be done in the board-specific devicetree overrides instead of the baseboard. BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I792d909ce75cb73571c9fec58c18f749ea3ae029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54933 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27mb/amd/majolica: set PSPP policy to balancedFelix Held
BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27mb/google/guybrush: set PSPP policy to powersaveFelix Held
BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I262c4c3ae90d8d12fdfe71a3620739070a444a55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54931 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/amd/cezanne: add devicetree setting for PSPP policyFelix Held
This allows boards to specify which PSPP policy (basically a dynamic trade-off between power consumption and PCIe link speed) should be used and also makes sure that the boards are using the expected PSPP policy and not just the UPD default from the FSP binary that has already changed once during the development. BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3John Zhao
TBT PowerResource _ON/_OFF methods are currently invoked by _PS0 and _PS3 respectively. It is defined for ACPI driver to call _ON and _OFF methods. This change drops the _PS0 and _PS3 call for _ON/_OFF and returns TBT PowerResource declaration in the _PR0 and _PR3, then ACPI driver will call the TBT PowerResource _ON and _OFF methods. BUG=b:188891878 TEST=Traced both of TBT _ON and _OFF methods invocation and execution at run time. Verified TBT's power_state to be D3Cold. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I398b3f58ec89f98673cbbe633149d31188ec3351 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-27util/cbfstool/fit.c: Fix getting the topswap tableArthur Heymans
There is a function to fetch the fit table at both the regular address and the TS address. So reuse that function instead of attempting to find the TS fit using some pointer aritmetics that is incorrect. Change-Id: I9114f5439202ede7e01cd0fcbb1e3c4cdb8698b0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54680 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27acpi: add SRAT Generic Initiator Affinity structureJonathan Zhang
Generic Initiator Affinity structure is introdcued in ACPI spec 6.3. This structure is used to define NUMA affinity domain which is established by generic initiator (such as by CXL device). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic6ef01c59e02f30dc290f27e741027e16f5d8359 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-05-27cpu/amd/pi/00630F01: Remove unused directory and codeMichał Żygowski
No board currently uses AMD PI 00630F01 so remove it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If270c2a979346029748230952caba78a5e763d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-27nb/amd/pi/00630F01: Remove unused directory and codeAngel Pons
No board uses AMD PI 00630F01, so drop it. And drop a single reference to the now-removed `NORTHBRIDGE_AMD_PI_00630F01` Kconfig option inside the `drivers/amd/agesa/acpi_tables.c` file. Change-Id: Ibc45a4a6041220ed22273c1d41f9b796e1acb901 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27src/intel/microcode: Add support for extended signature tableRizwan Qureshi
Microcode header supports advertising support for only one CPU signature and processor flags. If there are multiple processor families supported by this microcode blob, they are mentioned in the extended signature table. Add support to parse the extended processor signature table to determine if the microcode blob supports the currently running CPU. BUG=b:182234962 TEST=Booted ADL brya system with a processor whose signature/pf are in the extended signature table of a microcode patch. Was able to match and load the patch appropriately. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I1466caf4a4ba1f9a0214bdde19cce57dd65dacbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-26vc/amd/pi/00630F01: Remove unused directory and codeMichał Żygowski
No board currently uses AMD PI 00630F01 so remove it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3f990e44e0f769219a6f80cf1369f6a3c94b3509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/amd/picasso/mca: use MCAX registers instead of legacy MCAFelix Held
This patch also adds the additional 10 MCAX registers to the BERT MSR error record. BUG=b:186038401 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I31912d3b3e77e905f64b6143042f5e7f73db7407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26soc/intel/alderlake: Update soundwire master countSugnan Prabhu S
This patch includes changes to update the soundwire master count. Change-Id: Iffaf90569c19fb5ca3ce4775cc6dc6f8093f7c52 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-26soc/intel/common: Implement TBT firmware authentication validity checkJohn Zhao
After Thunderbolt firmware is downloaded to IMR, its authentication validity needs to be checked. This change implements the valid_tbt_auth function. Thunderbolt DSD and its corresponding IMR_VAID will be present to kernel only if its authentication is successful. BUG=b:188695995 TEST=Validated TGL TBT firmware authentication and its IMR_VALID into SSDT which is properly present to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3c9dda341ae6f19a2a8c85f92edda3dfa08c917a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-26soc/intel/alderlake: Add validity for TBT firmware authenticationJohn Zhao
After Thunderbolt firmware is downloaded to IMR, its authentication validity needs to be checked. This change adds the TBT firmware IMR status register offset and its authentication valid bit for valid_tbt_auth function usage. BUG=b:188695995 TEST=Built coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I742a00b6b58c45c1261f06b06a94346ad0a74829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54888 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/intel/tigerlake: Add validity for TBT firmware authenticationJohn Zhao
After Thunderbolt firmware is downloaded to IMR, its authentication validity needs to be checked. This change adds the TBT firmware IMR status register offset and its authentication valid bit for valid_tbt_auth function usage. BUG=b:188695995 TEST=Built Voxel coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia25827f18a10bf4d2dcabfe81565ac326851af3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54709 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26src/mainboard/google/guybrush: update devicetree with USB settingsJulian Schroeder
All relevant USB phy settings can now be controlled via devicetree. The given values are the AMD default ones. For proper tuning procedure and values contact AMD. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: Ie8d08bde54f8c0cb8202ba111b9c7a9bd33fa03e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26soc/amd/cezanne: add support for the changed AMD FSP API for USB PHYJulian Schroeder
The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-26ec/google/wilco/mailbox: Fix format warning by using size_t length modifierPaul Menzel
Building google/sarien with a 64-bit compiler (x86_64-linux-gnu) fails with the error below. src/ec/google/wilco/mailbox.c: In function 'wilco_ec_transfer': src/ec/google/wilco/mailbox.c:184:43: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 184 | printk(BIOS_ERR, "%s: data too short (%lu bytes, expected %zu)", | ~~^ | | | long unsigned int | %u 185 | __func__, rs.data_size - skip_size, msg->response_size); | ~~~~~~~~~~~~~~~~~~~~~~~~ | | | size_t {aka unsigned int} `data_size` has type `uint16_t`, and `skip_size` has type `size_t`, whose size differs in 32-bit (unsigned int) and 64-bit (unsigned long). So use the length modifier `z` for a `size_t` argument. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Change-Id: Ida27323daeed9b8ff487302d0f3d6fcce0bbb705 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie
2021-05-26vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v3162Tan, Lean Sheng
The FSP-M/S/T related headers added are generated as per FSP v3162. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ie6e6db704bcf86034fc9a3423101f0391ba2327e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54869 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/intel/elkhartlake: Minor fix for SCS & XHCI devices in ACPITan, Lean Sheng
1. Remove the extra UAB devices in xhci.asl 2. Update SD controller ADR in scs.asl 3. Remove the unused SCS PID Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I1906fb4e6893dc5e2b0bc8d85f4a7b2efc85c3a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54867 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/intel/elkhartlake: Update SA & IGD DIDs TableTan, Lean Sheng
Update SA & IGD DIDs table as per latest EDS (Doc no: 601458). Add extra SKUs and fix the mismatched SKU numbers accordingly. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I62fd9e6a7cf0fc6f541f3d6d9edd31d41db7279f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-26tests/lib/memset-test: Add missing malloc check and free on errorJakub Czapiga
Coverity found resource leak in test setup function in error block. Add malloc result check and free in error handling to silence Coverity. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Found-by: Coverity CID 1446760 Change-Id: Icf746df27167047fa3cf8f5df09fced20863f76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-26Add Kconfig TPMKyösti Mälkki
Defined as TPM1 || TPM2. Change-Id: I18c26d6991c2ccf782a515a8e90a3eb82b53b0e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26mb/google/asurada: Allow payloads to enable USB VBUSYu-Ping Wu
Configure GPIO CAM_PDN5 (AP_XHCI_INIT_DONE) as output, so that payloads (for example depthcharge) can assert it to notify EC to enable USB VBUS. BUG=b:187149602 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: I3bf63f91b8057e35be2780024a8b398c3044729b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54902 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26acpi/acpi: fix invalid checksumRocky Phagura
Incorrect size of the einj structure was being used, which created an invalid checksum message by the OS. This patch fixes the issue. Test=Booted to Linux on Deltalake mainboard and verified invalid checksum message is not logged in syslog. Exact message -> 'ACPI BIOS Warning (bug): Incorrect checksum in table [EINJ] - 0xDA, should be 0xD9' Change-Id: I2b1722d6960d4a62d14fb02ac5e8838397e12f92 Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54787 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26option: Decouple API from CMOS backendAngel Pons
Prepare to allow using other backends to store options. Change-Id: I3f838d27bf476207c6dc8f2c1f15c3fa9ae47d87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26option.h: Correct `get_uint_option` return typeAngel Pons
Commit 88dcb3179b4b (src: Retype option API to use unsigned integers) changed the option API to use unsigned integers, but missed this. Change-Id: I5deb17157db41c40cc72078e2af9cf65bdbe0581 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26soc/intel/common/block/smbus: Use `pci_dev_read_resources()` in read resourcesPaul Menzel
scan-build found a dead assignment, that the value stored to `res` is never read. Use `pci_dev_read_resources()` instead, as done in `sb/intel/common/smbus_ops.c` since commit 5f734327 (sb/intel/common/smbus_ops.c: Clean up read resources) avoiding the assignment. Change-Id: Ic59063b05a45dca411bf5b56c1abf3dd66ff0437 Found-by: scan-build (coreboot toolchain v0ad5fbd48d 2020-12-24 - clang version 11.0.0) Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26qemu-q35,xeon_sp: Drop HAVE_SMI_HANDLER conditional with smm-classAngel Pons
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I64bdcb28a996609111861ebafe172493b0650354 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54852 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rocky Phagura Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26mb/lenovo/t430: Do not set unused GNVS fieldsAngel Pons
ACPI code for this mainboard uses none of these values. Change-Id: I429bf8dc229fd830ae662034a8b733c9ee669140 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54851 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26mb/google/dedede: add haboki variantWisley Chen
haboki/habokay is the same design as drawlat/drawcia, and differs only in replacing Cr50 with discrete TPM. BUG=b:187094464 TEST=FW_NAME=haboki emerge-keeby coreboot Cq-Depend: chrome-internal:3850094 Change-Id: Id866927b7041c5bf1c73fb4f0c03798eb61efa79 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54755 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/amd/common/block/espi: Fix typo in espi_setup_periph_channelRaul E Rangel
ESPI_SLAVE_CHANNEL_READY is a read-only bit from the host perspective. It is set when the eSPI peripheral has configured the channel. We actually want to set the ESPI_SLAVE_CHANNEL_ENABLE flag. This never caused an issue before because the peripheral channel is enabled by default after PLTRST# is deasserted. This does fix the case where periph_ch_en == 0. It now properly clears the enable flag. BUG=b:188188172, b:188935533 TEST=Boot guybrush to OS, perform warm reset Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I24e0734d5652601ae9c967da528fec5e3f780991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-26soc/mediatek/mt8195: Initialize MCUPMalex.miao
Load MCUPM firmware and boot up MCUPM in ramstage. TEST=can see MCUPM log from AP console Signed-off-by: alex.miao <alex.miao@mediatek.corp-partner.google.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9e8c45ce7166644b94319ec2e7836d3d3c8008dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/54899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-26soc/mediatek: Move the MT8192 MCUPM driver to commonRex-BC Chen
The MPUCM drivers can be shared by MT8192 and MT8195. TEST=emerge-asurada coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I07a66bcf5a149582f34df1cfd08b5514fc5c2eb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-26soc/mediatek/mt8195: Change fsrc source to ulposcchun-jie.chen
Set fsrc source to ulposc_d10 for 26m off low power scenario. Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com> Change-Id: Ifb02d32820944d7cfbbf23de638e9a0e82b5e84d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54870 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26mb/google/cherry: Support audioTrevor Wu
Add GPIO "beep enable" for switching on and off. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: Iddb781e30fa90f05767cceeb83e623432540dcc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-25mb/google/dedede/var/cret: Generate new SPD ID for new memoryDtrain Hsu
Add new memory MT53E512M32D1NP-046 WT:B in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:183057749 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib797af858e8f7ea275291e552102db74f4724aad Reviewed-on: https://review.coreboot.org/c/coreboot/+/54747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25mb/google/guybrush: Add Goodix touchscreenIvy Jian
Add Goodix touchscreen according to the Programming Guide Rev.0.7 BUG=b:188872893 TEST=build and boot into OS. check dmesg trying to add GDIX0000:00 device. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I38c9bbf6e1c1531bf3524552db58c0bf183acbb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-25soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10msRaul E Rangel
The ChromeEC might take longer than 1ms for the peripheral channel to be enabled. The PLTRST# interrupt handler takes about ~539us. This doesn't account for the time it takes for the interrupt handler to be scheduled. Increasing the timeout to 10ms gives ample time. BUG=b:188188172, b:188935533 TEST=Boot guybrush and no longer see channel enable errors Suggested-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25cpu/intel/fit: Fix top swap fitArthur Heymans
The set_ts_fit_ptr makefile target was never a dependency of another target and therefore not used. Change-Id: Ie6b20164fce0dc406a28b4c1b9f41a79c68c27d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-25cpu/intel/fit: Remove broken ifittool argumentArthur Heymans
'-t' is not needed when setting the FIT pointer and breaks it as '-t' needs an argument so the $(TS_OPTIONS) is not properly decoded. Change-Id: I61a3ac1eda42e04152a7d10953bfb8407813d0f3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-25soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_*Tim Wawrzynczak
Change-Id: I8849f6dd2a9fdb16642de423cc82dcefd5b192ac Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54682 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25autoport: add a go.mod fileIru Cai
Go 1.16 needs this when running `go build` without GO111MODULE=off. Change-Id: I9dcb134a68b7a726f1466a472a415c9558f60524 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25cpu/intel/fit: Make make fit entries depend on fit pointerArthur Heymans
Make sure the fit pointer is set up before entries are added. Change-Id: I285fbb830a52e43cde5e8db9569a64dafb4408df Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-24mb/google/puff/var/dooly: Update CPU PSV to 85 degrees.Tony Huang
BUG=b:189053502 BRANCH=puff TEST=build image and verified by thermal team. Change-Id: Ic2337b9eabef158633c5e6dfa935ed5c8d3d76d1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54718 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24Revert "mb/google/brya/brya0: Manually probe fw_config for DB_LTE"Tim Wawrzynczak
This reverts commit 2f8a7046bb120d96022ada1e74545f859f97521f. Reason for revert: CB:54752 makes this unnecessary Change-Id: I3ad0bcafe50e3eafb9a106720c6c9ea5cb0efc4f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54789 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24device: Consider fw_config probing in `is_dev_enabled()`Furquan Shaikh
With the introduction of fw_config support in coreboot, it is possible for mainboards to control the state of a device (on/off) in ramstage using fw_config probe conditions. However, the device tree in immutable in all other stages and hence `is_dev_enabled()` does not really reflect the true state as in ramstage. This change adds a call to `fw_config_probe_dev()` in `is_dev_enabled()` when device tree is immutable (by checking DEVTREE_EARLY) to first check if device is disabled because of device probe conditions. If so, then it reports device as being disabled. Else, dev->enabled is used to report the device state. This allows early stages (bootblock, romstage) to use `is_dev_enabled()` to get the true state of the device by taking probe conditions into account and eliminates the need for each caller to perform their own separate probing. Change-Id: Ifede6775bda245cba199d3419aebd782dc690f2c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54752 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24fw_config: Add helper function `fw_config_probe_dev`Furquan Shaikh
This change adds a helper function `fw_config_probe_dev()` that allows the caller to check if any of the probe conditions are true for any given device. If device has no probe conditions or a matching probe condition, then it returns true and provides the matching probe condition back to caller (if provided with a valid pointer). Else, it returns false. When fw_config support is disabled, this function always returns true. Change-Id: Ic2dae338e6fbd7755feb23ca86c50c42103f349b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54751 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24sconfig: Emit probe_list in all stagesFurquan Shaikh
`probe_list` member in `struct device` is present in all stages, however, util/sconfig emits the list only when !DEVTREE_EARLY. This change ensures that `probe_list` is emitted in all stages. In follow up changes, this is used to get the correct device state using probe conditions. Change-Id: I61f7e909d48b616ac2127a5a9f36bdf4817a5165 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-24fw_config: Return false in `fw_config_probe` in unprovisioned caseFurquan Shaikh
fw_config is unprovisioned in the factory for the first boot. This is the only case where fw_config is left unprovisioned. On first boot in factory, fw_config gets correctly provisioned by the factory toolkit. When fw_config is unprovisioned, it is not always possible to make a guess which device to enable/disable since there can be certain conflicting devices which can never be enabled at the same time. That is the reason the original implementation of fw_config library kept fw_config as 0 when it was unprovisioned. CB:47956 ("fw_config: Use UNDEFINED_FW_CONFIG to mean unprovisioned") added support for a special unprovisioned value to allow any callers to identify this factory boot condition and take any appropriate action required for this boot (Ideally, this would just involve configuring any boot devices essential to getting to OS. All other non-essential devices can be kept disabled until fw_config is properly provisioned). However, CB:47956 missed handling the `fw_config_probe()` function and resulted in silent change in behavior. This change fixes the regression introduced by CB:47956 and returns `false` in `fw_config_probe()` if fw_config is not provisioned yet. Change-Id: Ic22cd650d3eb3a6016fa2e2775ea8272405ee23b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54750 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-22mb/google/dedede/var/sasukette: Enable ELAN touchpadlizhi7
Add ELAN touchpad into devicetree for sasukette. BUG=b:188376649 BRANCH=dedede TEST=built sasukette firmware and verified touchpad function Signed-off-by: lizhi7 <lizhi7@huaqin.corp-partner.google.com> Change-Id: I898aeda936eb10ef4ead679a1c087060fad71a08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54369 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>