diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-10 09:23:31 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-05-28 09:13:06 +0000 |
| commit | e7266e8393590c5e9012e0f169a99fa4a86ec9db (patch) | |
| tree | ee33bd6e144c36ad598765673f2602c2acf03f8f | |
| parent | e3a079cff89b8101d0b0a3a77938bd1c6ddaf752 (diff) | |
cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
Intel CBnT (and Boot Guard) makes the chain of trust TOCTOU safe by
setting up NEM (non eviction mode) in the ACM. The CBnT IBB (Initial
BootBlock) therefore should not disable caching.
Sidenote: the MSR macros are taken from the slimbootloader project.
TESTED: ocp/Deltalake boot with and without CBnT and also a broken
CBnT setup.
Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
| -rw-r--r-- | src/cpu/x86/entry16.S | 14 | ||||
| -rw-r--r-- | src/include/cpu/intel/msr.h | 10 |
2 files changed, 24 insertions, 0 deletions
diff --git a/src/cpu/x86/entry16.S b/src/cpu/x86/entry16.S index e1bfbf145d..147906fe4d 100644 --- a/src/cpu/x86/entry16.S +++ b/src/cpu/x86/entry16.S @@ -115,10 +115,24 @@ _start16bit: subw %ax, %bx lgdtl %cs:(%bx) +#if CONFIG(INTEL_CBNT_SUPPORT) +#include <cpu/intel/msr.h> + movl $MSR_BOOT_GUARD_SACM_INFO, %ecx + rdmsr + andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax + jz 1f + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x01, %eax /* PE = 1 */ + movl %eax, %cr0 + jmp 2f +#endif +1: movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 +2: /* Restore BIST to %eax */ movl %ebp, %eax diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 935ac30096..9126ccd825 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -14,6 +14,16 @@ #define MSR_PLATFORM_INFO 0xce +#define MSR_BOOT_GUARD_SACM_INFO 0x13a +#define V_TPM_PRESENT_MASK 0x06 +#define B_BOOT_GUARD_SACM_INFO_NEM_ENABLED (1 << 0) +#define B_BOOT_GUARD_SACM_INFO_TPM_SUCCESS (1 << 3) +#define B_BOOT_GUARD_SACM_INFO_MEASURED_BOOT (1 << 5) +#define B_BOOT_GUARD_SACM_INFO_VERIFIED_BOOT (1 << 6) +#define B_BOOT_GUARD_SACM_INFO_REVOKED (1 << 7) +#define B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY (1ull << 32) +#define B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY (1ull << 34) + #define MSR_PKG_C10_RESIDENCY 0x632 #endif /* CPU_INTEL_MSR_H */ |