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For libflashrom we need the delay functions but when including the whole
libpayload.h it has conflicting symbols.
Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Those values need to match with the ones defined in PMC PWRM
GPIO CFG register.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I8e84df83caab794e2fe7186e89e78343c2b55fd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add a new mainboard called fa_ehl which is based on Siemens's
'mc_ehl2'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Moreover a variants
scheme is provided for possible alternative implementations. Follow-up
commits will introduce the needed changes for the new mainboard.
Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a pmc.h file, which is needed for OC watchdog compilation. The PMC
definitions from pm.h are moved to pmc.h.
TEST=Build UP Squared and Intel GLKRVP sucessfully.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Change-Id: I8308ac1d2f3c9a34b55c788797bccd4e7fcefd5c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77348
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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GPT timer init is no longer needed after DRAM blob is switching to ARM
arch timer.
BUG=b:229800119
TEST=boot to kernel
Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 0c11187c:
2023-08-07 11:41:45 +0000 - (vboot_reference: Rename Cr50 to GSC when applicable)
to commit id 24cb127a:
2023-08-22 00:19:10 +0000 - (sign_uefi_unittest.py: Fix long-line lint)
This brings in 24 new commits:
24cb127a sign_uefi_unittest.py: Fix long-line lint
52ac0c71 dump_fmap: Rename format name from 'pretty' to 'parser'
068376d9 dump_fmap: Add description about formats
f67ae949 crossystem: stop supporting legacy chromeos_acpi driver
e6bd72f7 Revert "futility/cmd_vpd: Add vpd listing subcommand"
c7593acc futility: updater: fix build warning 'incompatible function pointer'
394fbfad crossystem: Binary search RW_NVRAM to find the active entry
a5b80353 keygeneration: drop ec_{data,root}_key
1c9b603d futility: updater: Refactor manifest generation
0a4be4a0 futility: updater: Use signer_config for all boards by default
f9d1f0b0 futility: Fix closing file in error path
4dbadfb3 vboot_reference: Remove VB2_RECOVERY_CR50_BOOT_MODE
11bdc1f5 futility: updater: Enable keyset in signer_config based manifest
35e69bcd futility: Change FLMSTR values set by --unlock_me
0ca8212b futility: updater: Use signer_config manifest instead of setvars
0e24a8ef scripts: use new fw updater pack/repack commands
4378179b futility/cmd_vpd: Add vpd listing subcommand
2fc252d8 futility: updater: Remove deprecated Glados platform quirks
3119182d x86/crossystem: Fix snprintf error for hostlib
06a0b9d0 sign_uefi: Remove exception catching
bcfd831e sign_uefi: Clarify comment for removing signatures
4cb7b0e5 crossystem: support new chromeos_acpi driver
eb37f19d vboot: remove trailing newline from sysfs
ec173ee4 vboot: rename ReadFileString() to ReadFileFirstLine()
Change-Id: I6c92791404dc1c6a3efc8bb9046fe5017ba794fb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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According to the schematic, karis does not have a SPI touchscreen,
remove related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The SPDX license header for this file did not match the license text
in the file.
Update the SPDX header and remove the license text.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc0db79e43df6d14b80b0ad3061fe42de17ed90f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77379
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19a69ffdf2c248223569153c00fbc76d5ceb7921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: If3c2e5bd9ee7e0f77d0c39ffe2ca9ad17b77d9bd
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Program the EC GPIOs to enable the DT or M.2 SSD1
PCIe slots based on the config option selected.
Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Set EnforceDdrMemoryFreqPor to 0 for RMT builds. This is needed
for proper functioning when EnforcePopulationPor is set to 1.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Icf4fe01ac9b546830334717dbfa53782d2a85ba1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx",
MT8188G used in ChromeOS project does not support clock hardware
monitor. Thus, we can simplify the initialization flow by removing the
hardware default value check.
BUG=b:292866009
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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When the script is run, it fetches a new copy of the repo, then creates
a tag, signed by GPG. When this signing step runs, a window pops up for
the user to enter their PGP key's passphrase. This window prevents the
user from doing anything else on their desktop, like looking up the
passphrase. It also times out after a while, and causes the script to
fail at that point.
To prevent this annoyance, pause right before the step asking for the
passphrase until the user is ready.
Because the submodules aren't tagged, we can delay their update until
after the tag is created to lower the amount of time needed before the
tag & signing step.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I414dfc0f8944b4408881392278a2bce2a364992b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77366
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This script allows any user with abandon rights to abandon patches that
haven't been touched (reviewed, commented on, rebased, etc) in over a
year.
As a part of the release process, we're now going to run the script to
abandon all of those patches so that we don't get to the point of
needing to abandon 1300 patches again in the future.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4a07c09edf02d9c1858a58322095eefbceb529d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Create the quandiso variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_QUANDISO
Change-Id: I846c39260e2db504d7bec6e81a8317b6824c17f4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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According to the schematic, karis does not have a WWAN temperature
sensor, remove related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ic82c6cfec067faa37d452bed5c4977402a2139a5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77284
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This change are added fine-tuned USB2 PHY parameters to improve the
USB2 eye diagram result.
BUG=b:296493887
BRANCH=firmware-dedede-13606.B
TEST=Local build bios successfully.
And verified the USB2 eye diagram test result.
Change-Id: I915fe689883267901e8faba28632345d8c227c28
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 6f36ebd:
2023-06-13 16:09:19 -0600 - (microcode-20230613 Release)
to commit id 6788bb0:
2023-08-08 12:04:21 -0600 - (microcode-20230808 Release)
This brings in 1 new commits:
6788bb0 microcode-20230808 Release
https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20230808
Change-Id: I2885b0189c4b6e68dc5ae6b2a3f809280ed4507a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77132
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I05c84cae5a050cc69f4d9eecaa0f82caacc85c2d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77345
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Separate constitution and intrepid wifi sar table in variant.c
BUG=b:291859402
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I0f89b3d5f5252a2b55bad4d91ad4ab9ec7519c50
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When using the Windows fast startup mechanism which is enabled by
default, Windows will use a cached version of the ACPI tables during
normal boots after a clean shutdown. Since I've run into this issue and
spent quite a bit of time debugging the wrong issue due to this, better
document this possibly unexpected behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia9e65f6a3aff13fa54abe68c8f5fcbf9bc6efc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add some HDMI-related gpios that are needed for early sign-of-life
to the early_graphics_gpio_table array so that SOL will show up on
HDMI ports.
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds
without error.
Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ice46117ccd3a082e20ce0d18421fd7da92aa3dbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77330
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie3c131db52993d99994e0d9cc04b80f480a72ab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77335
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move specific options under the boolean and remove dummy
SOC_SPECIFIC_OPTIONS.
Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This will include this new commit:
* Add GenoaPI 1.0.0.4 blobs
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I216580653ed22d961fa4d79622fdcc3985c36316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77355
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the schematic, karis does not have a WFC.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I9b4ecf2e96c77c131a60e48614d792370dd33423
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Allows coolstar's Windows overlay drivers to attach, while not affecting
operation under Linux or ChromeOS
TEST=build/boot Win11, Linux 6.x on google/drallion
Change-Id: I30ab2e9da00743c4d7086aac94652be46040f36d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77305
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allows the EC to be properly notified of type-c events like charger
wattage too low (eg),
TEST=build/boot Win11, Linux 6.x on google/drallion
Change-Id: I7a4130cf6f8c24e3f91e327adf1f3e563322c0af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77282
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the USCI device scope to _SB and set HID to USBC000 so Windows
driver attaches. This matches the ACPI used by the non-Chromebook
version of the Dell Latittude 7410 (which uses the same EC).
TEST=build/boot Win11 on google/drallion
Change-Id: If482fa4a4856c7bc085795bc72b35ebefe2f15c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77281
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allows coolstar's Windows drivers to attach.
TEST=build/boot Win11 on google/drallion
Change-Id: Idd339811563cd2cdfc4cc31bc5660a62f4e36a66
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Both Windows and MacOS get cranky if the Mutex synclevel is non-zero,
aborting any Acquire() call with Mutex param that has a non-zero
synclevel.
TEST=build/boot Win11 on google/drallion, verify DPTF driver loaded and
functional.
Change-Id: Ie77e9ed04658b508b2063ae219afcdc0ac465c58
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77279
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The RPL PCH uses a different ACPI Device ID than ADL PCH.
Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835)
Change-Id: I03f47a43ff985213ad617e834db7f974f687d877
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add 4.22 template and update index.
Change-Id: Id44616ca70ba693fc622164469bb748ee269565b
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77277
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The doc.coreboot.org container is several years out of date, using the
three year old Alpine 3.8 as the base image along with Sphinx related
pip packages which are even older. Accordingly, update the documentation
related pip packages in the coreboot-jenkins-node container as well.
- Update doc.coreboot.org to Alpine 3.18.3
- Update documentation related pip packages on coreboot-jenkins-node
and doc.coreboot.org to the latest versions on PyPI
- Update Sphinx to 6.2.1 as the latest version of sphinx_rtd_theme does
not yet support sphinx >= 7
The updates also noticeably improve performance, dropping documentation
build times from ~75 s down to ~42 s on my system from the Alpine+Python
updates alone, and further down to ~35 s with the rest of the updates.
TEST: The documentation builds and renders properly when built using the
updated container.
Change-Id: I38dfd22ee71c3779ab5fd3b3060e4675e9e3fe54
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73159
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If IASL isn't installed, the genbuild script throws a confusing warning.
This can and should be ignored because toolchain.inc will find this and
provide a much better error message.
The trailing >/dev/null was probably intended to do this, but didn't
actually affect anything.
Adding quotes around the IASL command will make "" be the command that
tries to get run instead of `-v` when IASL isn't present. This will
always be a failure, whereas `-v` could theoretically be a valid
command.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ibff93db670766c4de21faa7553f2003450465407
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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TEST=Boot Ubuntu 22.04 on MSI PRO Z790-P (DDR5 variant) with Intel Core
i5-13600K using UEFI Payload.
Change-Id: Id2c77621d24bb097b930342eb1961270854d5f68
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76325
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Similar situation happened last year when IoT FSP for ADL-S came out
before the Client FSP variant: https://github.com/intel/FSP/issues/83
It seems IoT FSP publishes the MemInfoHob.h file much later due to
legal reasons. Hack the missing file to get the builds using RPL-S IoT
FSP from repo working properly.
This change could be merged, subject for later revert (when the header
file is published).
Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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PchPcieClockGating and PchPciePowerGating UPDs are not yet available
in RPL-S IOT FSP. It also looks like those UPDs are not generally
available in all public RaptorLake FSP headers yet, so guard it
against SOC_INTEL_RAPTORLAKE to avoid build errors.
Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This adds a Kconfig option to select memtest86+ version 6 as a secondary
payload and sets that as the default. The coreboot version 5 code may
still be selected and used if desired.
Compiling for 32 bit requires glibc from multilib installed, if the host
system is running on 64 bit, as header files, e.g. gnu/stubs-32.h, are
required from there. So introduce a new choice menu which allows to
choose between 32 and 64 bit.
By default, the stable 6.20 version is selected instead of the top of
the main branch.
TEST=Build both V5 and V6, boot them in QEMU
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Ie0eedc25fcf37b925b072ca809c019a599a20392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The indentation resulted in the following error:
…/Documentation/soc/amd/psp_integration.md:22: ERROR: Unexpected indentation.
Alas, the line number refers to the embedded rst.
Change-Id: I9526d023af5207602c4a4cea7704b547ef1b7bf0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This binutils patch was pushed by the original author using the word
"loosing", which means "to release" instead of "losing", meaning to drop
or misplace.
I did not change the spelling of the commit message inside the patch so
that the patch can still be tracked easily, but wanted to fix the
mistaken spelling which appears when the patch is applied when building
the crossgcc toolchain.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I66fd596a79c9eb331f473d175180cf7bb5a38529
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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- Change delimiter characters to safe characters to keep the output
from getting mangled when imported into a spreadsheet.
- Change hyphens for statistics to asterisks for easier use in the
release notes.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I94f581d697f58cb29a662ac70ef9fd1d8c1e98ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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- Print submodule updates the way we want it for the release.
- Change hyphens on stats to asterisks.
- Add asterisks before authors.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I23e39fa47fe418ee51fb957fcb5fc25b50950e38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77331
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The -f|--fetch option is being added to download and verify the tarballs
without doing a build. This will be used specifically to archive the
toolchain tarballs for the release.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia68dbdcbf2d0fa4bb433511dc5e2f980f6762204
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I21db0474157ba20cdf3eaef086aaf29fde29d6c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76701
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We've had issues in the past where building with a sufficient number of
processors would expose a previously hidden timing issue in the build.
Those have frequently been in the path of a single chip or architecture,
so this adds a few different builds.
I'd like to have a representative sampling without increasing the build
time too much so maybe in the future, we can modify the clang build
targets to be different than the GCC targets.
These can be updated to different targets over time.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I51e39bc1ce6b9b7c257d0170ce3d2b5ab99d35df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The test-abuild target fails since the `scan-build` switch is missing a
dash. Fix it.
Change-Id: Iae10f639c43fed7709698e620e732cddce5658d8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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scanbuild and ccache don't work together, so separate ccache from the
rest of the abuild options. All of the other tests get ccache, but
scanbuild never does.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If057ed20c687ac8b501d20c6b4af91f8c0ab84b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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When installing the python modules with pip3 as root, the installer
throws a lot of warnings about conflicts and recommends that it not
be run that way. This change installs the python modules as the
coreboot user instead. The --break-system-packages argument can now
be removed.
It takes along some other changes made to the coreboot home directory
which also don't need to be run as root, and now adds the .local/bin
directory into the path.
The trailing docker PATH configuration is discarded as cleanup - it
doesn't have any effect. Nothing uses it in the Dockerfile, and it
doesn't end up updating the path, which is set by /etc/profile.
Change-Id: Ie8273009bb527e267584bba84504191aa7294ca3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76855
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The libfreetype6-dev has been a transitional package pointing at
libfreetype-dev for a while now. The libfreetype6-dev package is
currently out of date in debian sid, so it's a good time to switch
away from it.
TEST=Rebuild coreboot-sdk
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If40e9eacf871d3840745ea18ec2ff5975cc62da7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77328
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Line is a duplicate, commented out. Drop it as it serves no purpose.
Change-Id: Id35bdea0915ca47cac4f38ede6ccbf2f2fb59f47
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77304
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Registering Clock Driver (RCD) is responsible for driving address and
control nets on RDIMM and LRDIMM applications. Its operation is
configurable by a set of Register Control Words (RCWs). There are two
ways of accessing RCWs: in-band on the memory channel as MRS commands
("MR7") or through I2C.
Access through I2C is generic, while MRS commands are passed to memory
controller registers in an implementation-specific way.
See JESD82-31 JEDEC standard for full details.
Change-Id: Ie4e6cfaeae16aba1853b33d527eddebadfbd3887
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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Change-Id: I6f2dc0fcc4392f77b8011221c0cf22af5da45172
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The default branch for the board-status repo was renamed to main, and
thus the -u option for board_status.sh no longer works as it tries to
push to master. Update the branch accordingly.
TEST: board_status.sh is able to upload results to review.coreboot.org
using the -u flag.
Change-Id: Ic90e95d8701e21c4ae30a7ac85560eebe7658d79
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The EFER MSR is in the SMM save state and RSM properly restores it.
Returning to 32bit mode was only done so that fxsave was done in the
same mode as fxrstor, but this is no longer done.
See commit 1efca4d570 (cpu/x86/smm: Drop fxsave/fxrstor logic)
TESTED on qemu: the smihandler works fine.
Change-Id: Ie0e9584afd1f08f51ca57da5c4350042699f130d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68895
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I83e3c383faec0fd7b2cf768b7a4c237edd986666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76469
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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Change-Id: I9d4f048c859bc89897d50a5a07468c3375aa1dcf
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This patch adds the PsysPmax Upd to FSPM header file.
FSPM:
1. Add 'PsysPmax' UPD
2. Address offset changes
BUG=b:295126631
TEST=Able to build and boot google/rex to ChromeOS.
Change-Id: I892b8c2d75e58a42d3f85006237827da01426ea7
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77244
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Remove unused HPET_BASE_ADDRESS.
It is already defined at <arch/hpet.h>.
Change-Id: I8c517283e56915873b8e1798571642fd9d8a5764
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Change-Id: Id0adfd0e25806aef836f75e83ff86a55a5d799d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Excluding the "recommended" packages reduces the size of the container
image from ~8.40GB to ~7.23GB.
Install the following packages in addition as they are useful for one or
the other case, or at some point even required:
* ca-certificates
* less
* neovim
* openssh-client
Change-Id: Ic38ba75765e3a0c21bbfe3f380880c9ac575d0d2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76085
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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While Debian Sid provides GCC version 13, GNAT is still on version 12.
To keep them in sync, install GNAT 13 explicitly instead of the meta
package that is still referring to GNAT 12.
The coreboot toolchain including GNAT still compiles fine.
Change-Id: Ifb2b4c5fbaf3c0a8a78f6ebe244e2ccfec664b41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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broadwell/pch/Kconfig is sourced if SOC_INTEL_BROADWELL is true. So
remove 'if SOC_INTEL_BROADWELL' condition and duplicated
'INTEL_LYNXPOINT_LP'
Change-Id: I9b5676fd232b47e9d5f89f7faffdfd5d2c76984e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76699
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove dummy ARCH_SPECIFIC_OPTIONS.
Change-Id: Ia71021b8597b1d6a227292b6568351e994ad62b0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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While debugging lack of battery status under Windows, it was discovered
that the read/write flags in the args to the EC RAM 'ECRW' method were
not being correctly identified. Force set them from the R() and W()
methods which call ECRW() so those calls are processed properly.
TEST=build/boot Windows on google/drallion, verify battery status,
charging, etc are all reported properly.
Change-Id: I2a40b8d50ba65213813c781e53b56cc1a8b8debf
Signed-off-by: Coolstar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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IOE_PMC support was not enabled on Meteor Lake platforms. This patch
adds the bare minimum hooks to initialize and allocate a memory region
for IOE operations. Additionally, this patch moves those IOE operations
to a newly included IOE-specific file, Previously, PMC was responsible
for these operations.
BUG=b:287419766
TEST=build and verified on google/rex.
Change-Id: I8bbc0b8a3e32dad5404c80bc7717ef07e3ec60b9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77261
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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C1-state auto demotion feature allows hardware to determine C1-state
as per platform policy. Since platform sets performance policy to
balanced from hardware, auto demotion can be disabled without
performance impact.
Also, disabling this feature results soc to enter PC2 and lower
state in camera preview case and save platform power.
Note: C1 demotion heuristics used EPB parameter to balance between power
and performance, i.e. low threshold when EPB is low in-order to get C1
demotion faster and vice-versa. ChromeOS operates at default EPB=0x7
(low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits
than expected (similar to AC mode) and losing power respectively.
ref. https://review.coreboot.org/c/coreboot/+/76827
BUG=b:286328295
TEST=Code compiles and correct value of c1-state auto demotion is
passed to FSP. Also verified PC residency improvement ~10% in
camera preview case.
Change-Id: I1b2db634176f0072c535608c5600846a9086fef1
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: Ic7d51037d527f95e8664ad04e328fc27901cacde
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71993
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Existing code did not include the HID over SPI for rex4es.
This CL corrects this issue.
BUG=None
TEST=Tested on Rex
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I02f7c4b68cfee2ebb202581c9f031af99ab4b6f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77245
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow users of Alderlake N processors to use the microcode repository
and also add their related microcode blob to the list of microcodes
which should be included in the coreboot rom.
Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Newer versions of Sphinx complain about the language being set to None,
so explicitly set it to 'en'. The syntax that is currently used to
enable custom CSS styling for tables [1] also no longer works, resulting
in the docs rendering without CSS. Fix this using the html_css_files
option instead.
TEST: The documentation builds and renders correctly with both Sphinx
1.8.3 in from the doc.coreboot.org Docker container and Sphinx 7.2.2
from distro packages.
[1] Commit a78e66e5f4: Documentation: Add static CSS file to fix tables
Change-Id: I036b1cad3cfa533c0c3a037bac649caa2d968d4b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Fix the issue by adding the "ifeq" keyword which makes the extraneous
text a correct conditional directive.
Change-Id: Id8a8aa7acfdaeb0549f417fb013b2535a7298045
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77286
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I551d71d968abb6a9cadbc0f87bc9258768db1fca
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77275
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7ed982c9dcf755c97f26cc43b3dc05b898e4150a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77274
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add data.vbt files for all variants supported by current brya, brask,
and nissa recovery images. Select INTEL_GMA_HAVE_VBT for all variants
which currently have a VBT file.
TEST=build/boot various brya variants (banshee, osiris, redrix)
Change-Id: Ic66f91e264d37c3742cb17994f637604d77a1576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77144
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes unused CBMEM ID named
`CBMEM_ID_CSE_PARTITION_VERSION`.
BUG=b:285405031
TEST=Able to build and boot google/rex w/o any compilation error.
Change-Id: I83f53b7f64bdef62a8ee2061d5a9c9e22bc4b8a4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77179
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch selects `SOC_INTEL_STORE_ISH_FW_VERSION` config to dump
the ISH version as part of the .final hook.
BUG=b:285405031
TEST=Able to build and boot google/rex_ec_ish. Verify the ISH version
is same as MFIT ISH version section.
> cbmem -c | grep "ISH"
[DEBUG] ISH version: 5.6.0.28821
Change-Id: I052af85ad836ab81ff6c510bb74e042b11940a65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77178
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch implements `soc_is_ish_partition_enabled()` override to
uniquely identify the SKU type between ISH and non-ISH to conclude
if ISH partition is enabled and need to retrieve the ISH version from
CSE FPT by sending a HECI command.
BUG=b:285405031
TEST=Able to uniquely identify the ISH SKUs while booting
to google/rex_ec_ish to dump the ISH version.
Change-Id: I48358ad9e2e582e8b2274cbf4655de01f8792e6c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77177
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses the CSE firmware specific data to store Intel
ISH firmware related information. Sending an ISH partition version
information command on every boot cycle would impact the overall boot
performance.
This information is used by the auto-test framework to ensure the ISH
firmware update is proper for in-field devices.
BUG=b:285405031
TEST=Able to build and boot google/rex. Verified ISH FW version is
getting displayed across warm resets without impacting the boot time.
Change-Id: I0242c26dd90d834815799f54740d8147ff9d45b7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch selects SOC_INTEL_STORE_CSE_FW_VERSION config by default
for CSE LITE SKU. It helps to dump the CSE RW firmware version which
further consumed by auto-test infrastructure to ensure CSE RW firmware
update is successful.
BUG=b:285405031
TEST=Able to build and boot google/rex.
Verified CSE RW FW version (for LITE SKU) is getting displayed without
impacting the boot time.
Change-Id: Iba5903c73c0a45b01e6473714e0d5f759c061825
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77175
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch introduces a CSE firmware specific data in order
to store Intel CSE and associated firmware related information which
requires a sync between Pre-RAM and Post-RAM phase.
This information will be used further to retrieve currently running
CSE RW firmware instead of fetching the version information by sending
a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational
state).
Current implementation attempts to simply the CSE RW FW version store
and retrieval operations as below
* CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store
the CSE info data in absence of real physical memory and sync back into
the CBMEM once available (after FSP-M exits).
* CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW
version into the CBMEM (as CBMEM is online).
BUG=b:285405031
TEST=Able to build and boot google/rex. Verified CSE RW FW version
(for LITE SKU) is getting displayed without impacting the boot time.
w/o this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
w/ this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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