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2021-06-04Revert "util/vboot_lib: Add description.md"Angel Pons
This reverts commit 255b6f8646903594fb728f8228908792bad766f0. No longer needed after commit dd01e0131a8ba901bedec48844502fe85663390a (Revert "util/lint: Add test for documentation in util dirs") has been submitted. Plus, `util/vboot_lib/description.md` gets deleted whenever one runs `make -C util/cbfstool clean`, which is rather annoying. Change-Id: Ic93da096b6186d1d2af12243a74ec597694960c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55162 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04util/cbfstool/linux_trampoline.h: Fix typo in commentAngel Pons
inlucde ---> include Change-Id: I38987119ddabb08c457c9a7c8aecb8025fe2d9d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55161 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc/mediatek/mt8195: add SPM loaderDawei Chien
This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value after booting up. Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55140 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc/mediatek: Extract spm_parse_firmware to commonRex-BC Chen
spm_parse_firmware can be shared by MT8192 and MT8195. TEST=emerge-asurada coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I54d9672aa9ee9078ec9fe3fa4f2e9fe860a50636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55139 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc/intel/elkhartlake: Update FSP-S storage related configsLean Sheng Tan
Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-04soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configsLean Sheng Tan
Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04mb/google/dedede/var/cret: Add new Elan touchscreenDtrain Hsu
Add Elan eKTH7D18 touchscreen into devicetree for cret. BUG=b:180547935, b:187484857 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iab87ddfc7b46420439efa3e7e55c88ad4c27155d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-04soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipsetLean Sheng Tan
Further add initial silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-04mb/google/dedede/var/storo: Modify I2C times for touchpadZanxi Chen
Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately (380<frequency<400 kHz). Measured touchpad I2C frequency is 394 kHz BUG=b:189740533 BRANCH=dedede TEST=Build bios and make sure frequency meets specification. Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-03mb/google/dedede/var/sasukette: Modify the touch pad I2C addressTao Xia
There are two touch pads that Sasukette used have the same I2C address. It will show "/dev/input/event4: SPPT2600:00 06CB:CE9D Touchpad" when the Synaptics touch pad is connected after running evtest under VT2. BUG=b:189520603 BRANCH=dedede TEST=It will show "/dev/input/event4: SYNA0A00:00 06CB:CE9D Touchpad" when the Synaptics touch pad is connected after running evtest under VT2. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: If0bd80baa27dfeb7bcb43f0ca4b02e1228e372a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55035 Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03mb/google/brya: Create primus variantScott Chao
Create the primus variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0) BUG=b:188272162 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PRIMUS Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I26787f296793b281b7f1ee1a7d240006163c6015 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-03mb/google/brya: Add support for 2 new DRAM partsAmanda Huang
1) Hynix H9HCNNNCPMMLXR-NEE 2) Micron MT53E1G32D2NP-046 WT:B BUG=b:186616388, b:181736400 Change-Id: I56bfe8aa4f8d8aab2011fa8d17b3b2c8659658e3 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54951 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03soc/intel/alderlake: Add new memory parts for ADL boardsAmanda Huang
Use currently global_lp4x_mem_parts.json.txt to regenerate SPD files for LP4x memory parts that can be used with ADL-based mainboards. BUG=b:186616388 Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-03util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 configAmanda Huang
CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-03mb/google/brya: move MIPI camera setting into overridetreeScott Chao
In order to support no MIPI camera variant, move related configuration into variant folder. BUG=b:188272162 BRANCH=none TEST=build no MIPI camera variant without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-03soc/mediatek: Initialize SSPMRex-BC Chen
Load SSPM firmware and boot up SSPM in ramstage. This adds 23ms to the boot time. TEST=Load SSPM blob ok, and we can see some logs of SSPM from AP. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-02soc/amd/picasso: remove warm reset flag codeFelix Held
Since the MCA(X) registers have defined values on the cold boot path, the is_warm_reset check can be dropped. Also the warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register or the machine went through a warm reset cycle, the NCP_WARM_BOOT bit never got set. [1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO) #55570 Rev 3.15 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-02cbfstool/linux_trampoline.S: Fix up the e820 tableArthur Heymans
The e820 type don't fully match the LB_TAG_MEMORY types, so change all unknown types to e820 to '2', reserved memory. TESTED with Linuxboot: e820 now shows the CBMEM region as reserved. Change-Id: Ie0e41c66e002919e41590327afe0f543e0037369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55074 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Rocky Phagura Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-02mb/google/volteer/var/volet: Update gpio and devicetree settingsSheng-Liang Pan
Based on schematic and gpio table of volet, update gpio and devicetree settings for volet Proto. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55113 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-02mb/google/volteer/var/volet: add volet memory configuration.Sheng-Liang Pan
volet use same memory configuration from Voxel, copy voxel setting to volet. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55096 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01mb/intel/adlrvp_m: Enable LTR for PCIEBernardo Perez Priego
BUG=none TEST=Use command $ lspci -vv LTR+ is listed on DevCtl2 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492 Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01mb/google/brya: Enable WFCMeera Ravindranath
1. Add 1 port and 1 endpoint 2. Add support for OVTI8856 WFC is on I2C0 BUG=None BRANCH=None TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-01drivers/intel/mipi_camera: Add macros to increase code readabilityVarshit B Pandya
This will be used to pass information to driver through ACPI in devicetree. Example https://review.coreboot.org/c/coreboot/+/52013 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" TEST=Add these macros in devicetree, build and check static.c for consistency Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.corp-partner.google.com> Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/55097 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01soc/amd/cezanne/include/iomap: properly align definesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14647b3d88146602b96fc1dff2347a293bab0c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for remaining PCIe devicesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01soc/amd/picasso: introduce and use chipset device treeFelix Held
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01tests: Add lib/cbmem_stage_cache-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie6851b9473b225beb5ba51e26f44e21ea5919a64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-06-01acpi: drop unused parameter from acpi_soc_fill_bertFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-06-01util/cbfstool/Makefile: Check out vboot before trying to use itPatrick Georgi
Change-Id: Ie2044d73b97663f7816964c4d908a46570aafdbc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-01soc/mediatek: Move the SSPM driver to commonRex-BC Chen
The SSPM driver can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{asurada, kukui} coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If9779853becb298eeeabb3dc6096bc474baae202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55050 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01Documentation/community: Add link to the OSF SlackArthur Heymans
We are also present on Slack so advertise that. Change-Id: I7d9887e524e47e6f42a5013e9f696881ef54a631 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-01Documentation/community: Add Discord to forumsPatrick Georgi
Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-06-01configs: Update configs for OCP Delta Lake LinuxBoot payloadJohnny Lin
OCP Delta Lake is developed and validated against LinuxBoot payload. Need to put the respective binary blobs in site-local/deltalake to build the final coreboot image. Add LINUX_COMMAND_LINE for LinuxBoot payload kernel cmdline, CPU_UCODE_BINARIES for CPU microcode binary, CONSOLE_SERIAL_57600 is the serial baud rate used by OCP Delta Lake, DEFAULT_CONSOLE_LOGLEVEL_4 is for a faster boot time. Tested=On OCP Delta Lake it can boot up target CentOS 8 GNU/Linux OS. Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55058 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01soc/intel/elkhartlake: Update FSP-S UPD LPSS related configsTan, Lean Sheng
Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-01cpu/intel/car/romstage.c: Drop unused function argumentArthur Heymans
This is a leftover when migrating to C_ENV_BOOTBLOCK Change-Id: Ibc610cd15448632dc13d87094853d9b981e2679b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-31soc/amd/cezanne: Add pre-FSPM call to the mainboardMartin Roth
The Guybrush platform needs to set up some GPIOs immediately before the FSP-M runs. Add a platform specific call. This will be used in a follow-on commit. BUG=b:184796302, b:184598323 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I37d2625ff426347852e98a9a50f15368e0213449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54638 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/amd/common/block/espi: Explicitly assert PLTRST#Raul E Rangel
PLTRST# is currently asserted and latched when eSPI_RST# gets asserted. If eSPI_RST# isn't used on a platform or it doesn't properly assert in all cases, then PLTRST# will never be asserted. This could result in the AP and EC being out of sync. BUG=b:188188172, b:188935533 TEST=Warm reset guybrush with partial #22 rework. Verify that peripheral channel is correctly reset. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I20d12edf3efc6100096e24aa8d1aec76bbde264f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-30tests/Makefile.inc: Move generated headers to corresponding build dirJakub Czapiga
Test-local config override headers were generated to paths missing /tests/ infix, thus creating divergent tree in build output directory. This patch fixes it moving generated config headers to the test-local build directory. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ic5f3ba287ba3e9f5897cbaac64e88c2809f52d73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-30drivers/pc80/mc146818rtc: Check date and time for sanityWerner Zeh
There are cases where the RTC_VRT bit in register D stays set after a power failure while the real date and time registers can contain rubbish values (can happen when RTC is not buffered). If we do not detect this invalid date and/or time here and keep it, Linux will use these bad values for the initial timekeeper init. This in turn can lead to dates before 1970 in user land which can break a lot assumptions. To fix this, check date and time sanity when the RTC is initialized and reset the values if needed. Change-Id: I5bc600c78bab50c70372600347f63156df127012 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54914 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30lib/rtc: Add sanity check for time and dateWerner Zeh
Add a function to check sanity of a given RTC date and time. Invalid values in terms of overrun ranges of the registers can lead to strange issues in the OS. Change-Id: I0a381d445c894eee4f82b50fe86dad22cc587605 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-30mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110Werner Zeh
Already released Linux versions did not have the needed ACPI-extension in the RTC driver. If the ACPI-Support is enabled for the RTC, this older Linux will not be able to use this device as it will be claimed by the PNP-drivers. As there is no way to avoid that an older Linux kernel meets a newer coreboot in the field, we need to disable the ACPI support for the RTC for the mc_apl-based mainboards. Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55004 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI supportWerner Zeh
In commit b64db833d6 a basic ACPI support was added to the driver. With this support an SSDT-entry is created for this RTC and it is now visible to the OS via ACPI. In Linux the PNP-devices, which are reported over ACPI, are scanned rather early and if the entry is found, the device is claimed even if there is no driver available yet. In this case, when the native RTC-driver without ACPI-support is loaded and tries to register this device, the RTC is already blocked by the PNP-drivers and cannot be used anymore. This leads to a non-usable RTC on kernels where the needed ACPI-extension is not yet merged into the RTC driver. This patch provides a way to disable the ACPI-support for the RTC if needed. Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55003 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30cpu/x86/smm: Fix u32 type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:415:42: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'u32' {aka 'unsigned int'} [-Werror=format=] 415 | printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", | ~~^ | | | long unsigned int | %x 416 | __func__, stub_params->stack_top - total_stack_size); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | u32 {aka unsigned int} The size of `size_t` differs between i386-elf (32-bit) and x86_64-elf/x86_64-linux-gnu (64-bit). Unfortunately, coreboot hardcodes src/include/inttypes.h:#define PRIx32 "x" so `PRIx32` cannot be used. There use `z` as length modifier, as size_t should be always big enough to hold the value. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-30cpu/x86/smm: Fix size_t type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_module_setup_stub': src/cpu/x86/smm/smm_module_loader.c:360:70: error: format '%lx' expects argument of type 'long unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=] 360 | printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", | ~~^ | | | long unsigned int | %x As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `l` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. So, use the correct length modifier `z` for the type `size_t`. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I4172e0f4dc40437250da89b7720a5c1e5fbab709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-30cpu/x86/smm: Fix uintptr_t type mismatches in print statementsPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_create_map': src/cpu/x86/smm/smm_module_loader.c:146:19: error: format '%zx' expects argument of type 'size_t', but argument 3 has type 'uintptr_t' {aka 'long unsigned int'} [-Werror=format=] 146 | " smbase %zx entry %zx\n", | ~~^ | | | unsigned int | %lx 147 | cpus[i].smbase, cpus[i].entry); | ~~~~~~~~~~~~~~ | | | uintptr_t {aka long unsigned int} In coreboot `uintptr_t` is defined in `src/include/stdint.h`: typedef unsigned long uintptr_t; As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `z` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. Normally, `PRIxPTR` would need to be used as a length modifier, but as coreboot always defines `uintptr_t` to `unsigned long` (and in `src/include/inttypes.h` also defines `PRIxPTR` as `"lx"`), use the length modifier `l` to make the code more readable. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I32bff397c8a033fe34390e6c1a7dfe773707a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-30mb/intel/adlrvp_m: add ec device entry to devicetreeBora Guvendik
TEST=Boot to OS and verify acpi tables. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/intel/alderlake: Add placeholder SPD fileTim Wawrzynczak
Change-Id: I38eb4bb684c511fff5ae148091c066682e9c35cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-30Update vboot submodule to upstream mainDaisuke Nojiri
Updating from commit id e681c37: change node locked version expectations to commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55026 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30mb/siemens/mc_apl1: Move gpio.c from baseboard to mc_apl1Mario Scheithauer
Variant mc_apl1 is the only one that uses gpio.c from baseboard. For this reason, gpio.c is moved from baseboard to mc_apl1. Change-Id: Ie2ba8181dfe887df9abbbd648f2cbdc6ffc65530 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-30mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configurationMario Scheithauer
With commit 405f229689 (soc/intel/*: drop UART pad configuration from common code) the UART pad configuration was dropped from common SoC code. Through a second commit 5ff17ed393 (mb/siemens/mc_apl1: do UART pad configuration at board-level) the UART pad configuration was made for mc_apl1 baseboard. This change is also needed for all other mc_apl boards. Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-30arch/x86/acpi_bert_storage: change return type of bert_errors_presentFelix Held
The return value is a boolean, so use the bool type. Also add the types.h header to have the bool type defined. Also change type of bert_region_broken static variable to bool. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-30soc/intel/elkhartlake: Update FADT tableTan, Lean Sheng
Update FADT table per relevant PM settings: Fix PM Timer block access size and disable C2 and C3 states for the CPU. Further on, set the century byte offset in FADT to point to the common location in CMOS. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54958 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/intel/elkhartlake: Update FSP-M UPD related configsTan, Lean Sheng
Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-30Apply more uses for Kconfig TPMKyösti Mälkki
Change-Id: I54b296563940cd46fe9da9fe789b746f2fc1987d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-29drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function staticSubrata Banik
fsp_temp_ram_exit() function is only getting called by late_car_teardown() function inside temp_ram_exit.c file. Hence, make function as static and removed from include/fsp/api.h. Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-28mb/kontron/mal10: Use mainboard_ops driver for GPIO configurationFelix Singer
`mainboard_silicon_init_params()` should *only* be used for configuring FSP options which can not be configured anywhere else. Therefore, use the init phase from the mainboard_ops driver for configuring the GPIOs. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ia01091938ac113cb5cf95f046609a1ebf3620806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48143 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger LakeSrinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4133 to include post PRQ UPDs. BUG=b:188452018 BRANCH=none TEST=build voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28arch/x86/timestamp.inc: Remove unused fileArthur Heymans
This is a romcc compiled bootblock leftover. Change-Id: I8d4f8bcdac7e15d60540157e9d2ac98603320977 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55007 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/google/volteer/var/collis: Update DPTF parametersFrankChu
Update the first version DPTF parameters received from the thermal team. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Cq-Depend: chrome-internal:3851737 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28mb/google/dedede: Update Storo setting for PEN detection.Zanxi Chen
Update devicetree and gpio driving of storo that enable stylus Updates the GPIO configuration for GPP_C12 to PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to use WAKEUP_ROUTE_GPIO_IRQ. BUG=b:188519508,b:188365033 BRANCH=dedede TEST=build bios and the pen behavior can be detected. Change-Id: I2ffc969569b3ca29ba76326140f958a9707199f7 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54762 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/amd/bilby,cereme,mandolin: change PSPP policy to balancedFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7571ed92b3c3fa79581e2c7342960ca31451af1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-28Documentation: Fix up toctreePatrick Georgi
Some files weren't properly hooked up, making Sphinx complain. Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55020 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28Documentation: Fix named linkPatrick Georgi
The syntax requires two bracketed fields. Change-Id: I98ebe714e57f50017755eed7888f0dd2637a3066 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-28soc/amd/picasso: fix MCACHE on psp_verstage RO bootKangheui Won
On RW boot path psp_verstage call cbfs_map which calls chain of _cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then cbfs_get_boot_device initializes MCACHE which is used later. However on RO boot path psp_verstage doesn't try to find anything in the CBFS which results RO MCACHE not to be initialized. Add cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery boot. BUG=b:177091575 BRANCH=none TEST=build and boot jelboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28Documentation: Update real time chat optionsPatrick Georgi
Change-Id: I3035266c5e035b954c0d709bd2c09069128c3340 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55010 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/prodrive/hermes: Rename EEPROM access functionsAngel Pons
Change-Id: I84b9ef080f1ac91ea6f7273457b882677abf70d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52885 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/prodrive/hermes: Simplify `read_write_config` signatureAngel Pons
The `write_offset` parameter is always zero. Remove it. Change-Id: Ib63cb25904ad6c1c7424a9c01d8bf1e84c08453b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52884 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28option: Allow mainboards to implement the APIAngel Pons
Some mainboards need a mainboard-specific mechanism to access option values. Allow mainboards to implement the option API. Also, add some documentation about the current option API, and describe when should one reimplement the option API in mainboard code: only when the code is mainboard-specific to comply with externally-imposed constraints. Change-Id: Idccdb9a008b1ebb89821961659f27b1c0b17d29c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28option: Turn CMOS option backend into choiceAngel Pons
In order to add more option backends, transform the current CMOS option backend into a Kconfig choice. Replace the `select` directives, as they cannot be used with choice options. Change-Id: Id3180e9991f0e763b4bae93a92d40668e7fc99bc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28nb/intel/x4x/rcven.c: Guard macro parametersAngel Pons
Add parentheses around macro parameters to avoid operation order issues. Change-Id: I9528f3d6b221854fddd2db6d2b45c63bfdda0092 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54953 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28ec/kontron/kempld: Guard macro parametersAngel Pons
Add parentheses around macro parameters to avoid operation order issues. Change-Id: I2d4552abaeda5702619cc53e9dfae1f17b048e67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28cpu/x86/entry16.S: Make Intel CBnT TOCTOU safeArthur Heymans
Intel CBnT (and Boot Guard) makes the chain of trust TOCTOU safe by setting up NEM (non eviction mode) in the ACM. The CBnT IBB (Initial BootBlock) therefore should not disable caching. Sidenote: the MSR macros are taken from the slimbootloader project. TESTED: ocp/Deltalake boot with and without CBnT and also a broken CBnT setup. Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-28mb/intel/adlrvp_m: Disable unused TBT ports from device treeBernardo Perez Priego
These PCIe and DMA ports are not available for adlrvp_m. BUG=none TEST=Boot device Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28mainboard/google/brya: Add S3/S0ix wake events AC connect/disconnectmadhusudanarao amara
Enabling AC connect/disconnect wake events in brya to meet Chrome OS wake requirements. These changes are similar to Volteer and Shadowmountain. BUG=none BRANCH=None TEST=manual tested DUT wakes for AC connect/disconnect in S0ix Change-Id: I14b3efd429e3aa701af534f150baf35fcdeb9f35 Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54855 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28ec/google/wilco: Extend description of `EC_GOOGLE_WILCO`Paul Menzel
Change-Id: Ia278b538a8904651d16c37d095972fa78e264288 Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/7S5OJMLQUEIU6YK36JTTRINF5OOCI66V/ Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-28mb/intel/ehlcrb: Upload EHL CRB GPIO configsTan, Lean Sheng
Initial upload of the GPIO configs for EHL CRB. This CL also includes the UART GPIO configs in early GPIO table. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-27cbmem: Introduce "early" init hooks for consoleJulius Werner
Over the last couple of years we have continuously added more and more CBMEM init hooks related to different independent components. One disadvantage of the API is that it can not model any dependencies between the different hooks, and their order is essentially undefined (based on link order). For most hooks this is not a problem, and in fact it's probably not a bad thing to discourage implicit dependencies between unrelated components like this... but one resource the components obviously all share is CBMEM, and since many CBMEM init hooks are used to create new CBMEM areas, the arbitrary order means that the order of these areas becomes unpredictable. Generally code using CBMEM should not care where exactly an area is allocated, but one exception is the persistent CBMEM console which relies (on a best effort basis) on always getting allocated at the same address on every boot. This is, technically, a hack, but it's a pretty harmless hack that has served us reasonably well so far and would be difficult to realize in a more robust way (without adding a lot of new infrastructure). Most of the time, coreboot will allocate the same CBMEM areas in the same order with the same sizes on every boot, and this all kinda works out (and since it's only a debug console, we don't need to be afraid of the odd one-in-a-million edge case breaking it). But one reproducible difference we can have between boots is the vboot boot mode (e.g. normal vs. recovery boot), and we had just kinda gotten lucky in the past that we didn't have differences in CBMEM allocations in different boot modes. With the recent addition of the RW_MCACHE (which does not get allocated in recovery mode), this is no longer true, and as a result CBMEM consoles can no longer persist between normal and recovery modes. The somewhat kludgy but simple solution is to just create a new class of specifically "early" CBMEM init hooks that will always run before all the others. While arbitrarily partitioning hooks into "early" and "not early" without any precise definition of what these things mean may seem a bit haphazard, I think it will be good enough in practice for the very few cases where this matters and beats building anything much more complicated (FWIW Linux has been doing something similar for years with device suspend/resume ordering). Since the current use case only relates to CBMEM allocation ordering and you can only really be "first" if you allocate in romstage, the "early" hook is only available in romstage for now (could be expanded later if we find a use case for it). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2c849a89f07a87d448ec1edbad4ce404afb0746 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-27tpm: Remove USER_TPMx options, make TPM1/TPM2 menuconfig visibleJulius Werner
We would like to have an easy way to completely disable TPM support on a board. For boards that don't pre-select a TPM protocol via the MAINBOARD_HAS_TPMx options, this is already possible with the USER_NO_TPM option. In order to make this available for all boards, this patch just removes the whole USER_TPMx option group and directly makes the TPM1 and TPM2 options visible to menuconfig. The MAINBOARD_HAS_TPMx options can still be used to select defaults and to prevent selection of a protocol that the TPM is known to not support, but the NO_TPM option always remains available. Also fix some mainboards that selected TPM2 directly, which they're not supposed to do (that's what MAINBOARD_HAS_TPM2 is for), and add a missing dependency to TPM_CR50 so it is set correctly for a NO_TPM scenario. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib0a73da3c42fa4e8deffecb53f29ee38cbb51a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-27mb/amd/majolica: enable crypto coprocessor PCIe deviceFelix Held
This fixes the following error from the Linux kernel: ccp 0000:03:00.2: ioremap failed ccp 0000:03:00.2: initialization failed ccp: probe of 0000:03:00.2 failed with error -12 BUG=b:186575712,b:189202985 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c6a6cbbdda2cb22e81e2b52b364617d6765e09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54963 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27mb/google/guybrush,mancomb: enable crypto coprocessor PCIe deviceFelix Held
This fixes the following error from the Linux kernel: ccp 0000:03:00.2: ioremap failed ccp 0000:03:00.2: initialization failed ccp: probe of 0000:03:00.2 failed with error -12 BUG=b:186575712,b:189202985 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5cbc620001d3c21c538b62ab2811b6e07269feb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54962 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/amd/common/block: Fix missing include in acp.hRaul E Rangel
We were missing the stdint.h header, and the header was sorted incorrectly in chip.h BUG=non TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I209d3c9c48e5b06b2a56759af51cf2858eb99f51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27Mancomb: Add firmware config CBI definitionsMartin Roth
The firmware config field in CBI lets us control initialization parameters based on the OEM design. BUG=b:188713024 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I56ddc7218688919f20f41e0f143419c39d83849d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-27soc/amd/picasso: add devicetree setting for PSPP policyFelix Held
Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-27drivers/intel/fsp1_1: Drop empty weak functionsAngel Pons
The only FSP 1.1 platform is Braswell. Drop unnecessary functions which only have a weak stub definition. Change-Id: Ie60213e5a6ae67bd8b982ee505f4b512253577c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-05-27lib/hexdump: remove hexdump32 and use hexdump insteadFelix Held
hexdump and hexdump32 do similar things, but hexdump32 is mostly a reimplementation that has additional support to configure the console log level, but has a very unexpected len parameter that isn't in bytes, but in DWORDs. With the move to hexdump() the console log level for the hexdump is changed to BIOS_DEBUG. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6138d17f0ce8e4a14f22d132bf5c64d0c343b80d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54925 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27drivers/intel/fsp1_1: Drop weak function definitionAngel Pons
The only FSP 1.1 platform is Braswell, which has a non-weak definition for the `soc_silicon_init_params` function. This changes the resulting BUILD_TIMELESS=1 coreboot image for Facebook fbg1701, for some reason. Change-Id: I2a1b51cda9eb21d7af8372c16a43195a4bdd9543 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27drivers/intel/fsp1_1: Drop unused weak definitionsAngel Pons
The only FSP 1.1 platform is Braswell. Drop unused weak definitions for functions where a non-weak definition always exists. Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: Ifaf40a1cd661b123911fbeaafeb2b7002559a435 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27drivers/intel/fsp1_1: Drop some MMA leftoversAngel Pons
Commit 736a1028fbaef97d32221cadb1f512c9a8960a76 (drivers/intel/fsp1_1: Drop dead MMA code) dropped FSP 1.1 MMA code, but missed a few things. Change-Id: I556e7125eff21c49609bb1e5e1f23e99e692756f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27mb/google/mancomb: set PSPP policy to balancedFelix Held
Not sure which policy we should select here or if that should be done in the board-specific devicetree overrides instead of the baseboard. BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I792d909ce75cb73571c9fec58c18f749ea3ae029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54933 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27mb/amd/majolica: set PSPP policy to balancedFelix Held
BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27mb/google/guybrush: set PSPP policy to powersaveFelix Held
BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I262c4c3ae90d8d12fdfe71a3620739070a444a55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54931 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/amd/cezanne: add devicetree setting for PSPP policyFelix Held
This allows boards to specify which PSPP policy (basically a dynamic trade-off between power consumption and PCIe link speed) should be used and also makes sure that the boards are using the expected PSPP policy and not just the UPD default from the FSP binary that has already changed once during the development. BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3John Zhao
TBT PowerResource _ON/_OFF methods are currently invoked by _PS0 and _PS3 respectively. It is defined for ACPI driver to call _ON and _OFF methods. This change drops the _PS0 and _PS3 call for _ON/_OFF and returns TBT PowerResource declaration in the _PR0 and _PR3, then ACPI driver will call the TBT PowerResource _ON and _OFF methods. BUG=b:188891878 TEST=Traced both of TBT _ON and _OFF methods invocation and execution at run time. Verified TBT's power_state to be D3Cold. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I398b3f58ec89f98673cbbe633149d31188ec3351 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-27util/cbfstool/fit.c: Fix getting the topswap tableArthur Heymans
There is a function to fetch the fit table at both the regular address and the TS address. So reuse that function instead of attempting to find the TS fit using some pointer aritmetics that is incorrect. Change-Id: I9114f5439202ede7e01cd0fcbb1e3c4cdb8698b0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54680 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27acpi: add SRAT Generic Initiator Affinity structureJonathan Zhang
Generic Initiator Affinity structure is introdcued in ACPI spec 6.3. This structure is used to define NUMA affinity domain which is established by generic initiator (such as by CXL device). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic6ef01c59e02f30dc290f27e741027e16f5d8359 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-05-27cpu/amd/pi/00630F01: Remove unused directory and codeMichał Żygowski
No board currently uses AMD PI 00630F01 so remove it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If270c2a979346029748230952caba78a5e763d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-27nb/amd/pi/00630F01: Remove unused directory and codeAngel Pons
No board uses AMD PI 00630F01, so drop it. And drop a single reference to the now-removed `NORTHBRIDGE_AMD_PI_00630F01` Kconfig option inside the `drivers/amd/agesa/acpi_tables.c` file. Change-Id: Ibc45a4a6041220ed22273c1d41f9b796e1acb901 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27src/intel/microcode: Add support for extended signature tableRizwan Qureshi
Microcode header supports advertising support for only one CPU signature and processor flags. If there are multiple processor families supported by this microcode blob, they are mentioned in the extended signature table. Add support to parse the extended processor signature table to determine if the microcode blob supports the currently running CPU. BUG=b:182234962 TEST=Booted ADL brya system with a processor whose signature/pf are in the extended signature table of a microcode patch. Was able to match and load the patch appropriately. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I1466caf4a4ba1f9a0214bdde19cce57dd65dacbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-26vc/amd/pi/00630F01: Remove unused directory and codeMichał Żygowski
No board currently uses AMD PI 00630F01 so remove it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3f990e44e0f769219a6f80cf1369f6a3c94b3509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>