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2024-07-18soc/intel/alderlake: Switch to common eSPI headerSubrata Banik
This patch updates Alder Lake code to use the common eSPI header file (`intelpch/espi.h`) instead of the SoC-specific one. BUG=none TEST=Builds successfully for google/redrix. Change-Id: Ib4452547325042de48ee4fca3d3910a031b56b64 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83484 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/cmn/pch: Consolidate eSPI.h into IA common codeSubrata Banik
This patch moves the SoC-specific `eSPI.h` file into the IA common code to promote code reuse and reduce duplication across different SoC generations. TEST=Builds successfully for google/rex. Change-Id: Icb09421eec45c1ef8ab50252543b000078f18b21 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/meteorlake: Use common CAR API for cache reportingSubrata Banik
Replace the SoC-specific `report_cache_info()` function with the common `car_report_cache_info()` API from `car_lib`. This promotes code reuse and reduces SoC-specific implementation for cache reporting. BUG=none TEST=Builds and boots successfully on google/rex platform. Change-Id: Id5ffcab54232294ffa101f975d0ec51ac63f1910 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/alderlake: Use common CAR API for cache reportingSubrata Banik
Replace the SoC-specific `report_cache_info()` function with the common `car_report_cache_info()` API from `car_lib`. This promotes code reuse and reduces SoC-specific implementation for cache reporting. BUG=none TEST=Builds and boots successfully on google/marasov platform. Change-Id: I18be2c33dbe5186643af52823eb2fb185a296909 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83481 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/cmn/cpu: Introduce common CAR APIsSubrata Banik
This patch adds `car_lib.c` to the IA common code to consolidate SoC-agnostic CAR APIs. Initially, it includes `car_report_cache_info()` to provide a unified way to read cache information, reducing the need for SoC-specific implementations. TEST=Builds successfully for google/rex. Change-Id: I2ff84b27736057d19d4ec68c9afcb9b22e778f55 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/mtl: Enable eSOL for x86_64 archSubrata Banik
This change removes the condition that SOC_INTEL_METEORLAKE_SIGN_OF_LIFE is only enabled for x86_32 arch. Now, it is safe to enable eSOL for x86_64 platform as well. BUG=b:346682156 TEST=Able to see eSOL on google/rex64. Change-Id: I825c988800ec303a8f37141f6487115b1c7c5d3a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83498 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya: Add config options for TRULO boardSubrata Banik
This change adds the necessary Kconfig options to enable support for the TRULO board, including selecting the appropriate baseboard, HDA verb table, and TCSS configuration. Additionally, corrected the TPM_TIS_ACPI_INTERRUPT from `13` to `17` for Trulo as applicable. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I5c1cbd56cf2734058aced35868ae42c1c160f62e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83500 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya/variants/trulo: Include hda_verb.cSubrata Banik
This change adds hda_verb.c to the ramstage build, but only when the CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB config option is enabled. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I9b17126ff1493b5714d6ae715ad2863bdff4ed46 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83499 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya: Standardize TPM TIS ACPI interrupt configurationSubrata Banik
This patch sets a default value of 13 (GPE0_DW0_13/GPP_A13_IRQ) for the `TPM_TIS_ACPI_INTERRUPT` configuration option across most Google Brya variants. The HADES board uses interrupt 20 (GPE0_DW0_20/ GPP_A20_IRQ), and the ORISA board uses interrupt 17 (GPE0_DW0_17/ GPP_A17_IRQ). This refactoring simplifies future additions of board-specific TPM interrupt configurations, improving maintainability. BUG=none TEST=The timeless builds with this patch for both Nissa and Brya devices produce the same binaries. Change-Id: I9d913bf3da6957ab5c700dd746bc4b5350427d73 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83493 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-16mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinterEmilie Roberts
Fixes a pmc_mux port mapping error introduced in coreboot commit 4fa8354 Mithrax and felwinter do not have sequential mux_conn[X] to connY mappings which led to the kernel subsystem linking between Type C connectors and USB muxes to be incorrect. The previous patch attempted to fix this by changing the custom_pld layout. However this broke USB usage except for charging. This patch reverts the custom_pld layout and instead changes the pmc hidden and tcss_xhci port mappings to match the hardware layout. BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406 TEST=emerge-${BOARD} coreboot TEST=Manually check that usb-role-switches are mapped to the correct port. Attach USB 3 A to C cable from development machine to left port of DUT. Attach nothing to right-hand port. ectool commands below are only for felwinter as a workaround for devices without a firmware patch to connect superspeed lines. ectool usbpd 0 none ectool usbpd 0 usb ectool usbpd 1 none ectool usbpd 1 usb echo host > /sys/class/typec/port0/usb-role-switch/role (should succeed) ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch) echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed) echo host > /sys/class/typec/port1/usb-role-switch/role (should fail as no cable attached) ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch) echo host > /sys/class/usb_role/CONY-role-switch/role (should fail as no cable attached) BRANCH=firmware-brya-14505.B Change-Id: Iebd259842d3affa259069cd776b46759c1c60712 Signed-off-by: Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83472 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-16util/liveiso/nixos: Install TPM related toolsFelix Singer
Change-Id: Idbf4f40f495fac6c08a9017bfbff25043d7fbb82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-07-16util/cbfstool: Add eventLog support for ELOG_TYPE_FW_LATE_SOLSubrata Banik
In order to support logging events for when we show early signs of life to the user during CSE FW syncs add support for the ELOG_TYPE_FW_LATE_SOL type. BUG=b:305898363 TEST=verify event shows in eventlog CSE sync. Change-Id: I862db946f6ff622ac83072e6bf27832732c0c318 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-16commonlib: Add ELOG_TYPE_FW_LATE_SOL eventLog typeSubrata Banik
Add a new eventLog type of ELOG_TYPE_FW_LATE_SOL to support logging when we show late (from payload) Signs Of Life (SOL) to the user. BUG=b:305898363 TEST=Event shows in eventlog tool after CSE sync: ``` Late Sign of Life | CSE Sync Late SOL Screen Shown ``` Change-Id: Ibbe9f37a791e5c2a0c6e982942cf3043a2bd4b45 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-15drivers/wifi: Support Radio Frequency Interference MitigationJeremy Compostella
The 'Radio Frequency Interference Mitigation' DSM function 11 provides the desired status of the RFI mitigation. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:352768410 TEST=ACPI DSM Function 11 reflects the value of the SAR binary Change-Id: I02808b0ce6a0a380845612e774e326c698ad1adc Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-15drivers/wifi: Support Energy Detection ThresholdJeremy Compostella
The 'Energy Detection Threshold' DSM function 10 provides the desired status of the EDT optimizations. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:352788465 TEST=ACPI DSM Function 10 reflects the value of the SAR binary Change-Id: I2e2e9d4f5420020bd7540cb36fa8aebfedf62285 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-07-15soc/amd/phoenix/include/gpio: update GPIO HID to AMDI0030Felix Held
The UEFI reference firmware uses AMDI0030 instead of AMD0030 as HID for the GPIO controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a6fa1acdca0ee5b6e1358b6279b7c501d3dfd16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-07-15soc/amd/glinda/include/gpio: update GPIO HID to AMDI0030Felix Held
The UEFI reference firmware uses AMDI0030 instead of AMD0030 as HID for the GPIO controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8dd48d7d9cf3f6d75853bb825e5ddc32bba430b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-07-15soc/amd/glinda/include/gpio: update to match hardwareFelix Held
The table "IOMUX Functional Table" in PPR #57254 rev. 1.60 was used as a reference. This should fix the ESPI_ALERT_D1 IOMUX setting for the boards using the Glinda SoC which previously didn't match the hardware. Compared to Phoenix, Glinda has two more chip select outputs for the SPI2 controller and an additional ZST_STUTTER_RAIL IOMUX function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9adfbe0c7aee90d6fe990f239d82a1d013e7f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83437 Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-07-15mb/lenovo/t420: Use vendor default power limitsAnastasios Koutian
Also set the vendor default TCC offset temperature Change-Id: Ia187b67ae28fbcda7d5d0e35ec64a3b21d97a21b Signed-off-by: Anastasios Koutian <akoutian2@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-15cpu/intel/model_206ax: Allow turbo boost ratio limit configurationAnastasios Koutian
Tested on ThinkPad T420 with the i7-3940XM. Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad Signed-off-by: Anastasios Koutian <akoutian2@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-15cpu/intel/model_206ax: Allow package power limit clampingAnastasios Koutian
Setting the clamp bit allows the CPU to operate below the highest non-turbo frequency in order to obey the power limit. Tested on ThinkPad T420 with the i7-3940XM. Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Signed-off-by: Anastasios Koutian <akoutian2@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-15mb/clevo/cml-u/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: Ifc882c2ac9d4e9ce2ed4305bdd6859a5d1e1b09c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-07-15util: Add hda-decoderNicholas Sudsgaard
This tool helps take off the burden of manually decoding default configuration registers. Using decoded values can make code more self-documenting compared to shrouding it with magic numbers. This is also written as a module which allows easy integration with other tools written in Go (e.g. autoport). Change-Id: Ib4fb652e178517b2b7aceaac8be005c5b2d3b03e Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-07-15mb/google/poppy: Drop superfluous devices from devicetreeFelix Singer
In order to clean up a bit, drop devices which are equivalent to the ones from chipset devicetree. Change-Id: Ief199db47fc529c510709ac37be6014b63244e84 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-14autoport: Add support for Haswell-Lynx Point platformIru Cai
Tested with the following devices (not exhaustive): - Dell Latitude E7240 - Dell Precision M6800 and M4800 - Asrock Z87E-ITX - Asrock Z87M OC Formula - Asrock Fatal1ty Z87 Professional Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Signed-off-by: Iru Cai <mytbk920423@gmail.com> Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-13cfl/cml/whl mainboards: Drop superfluous cpu_cluster deviceFelix Singer
The cpu_cluster device is defined in the chipset devicetree. So drop it from the mainboards. Change-Id: I65bfeaf0b8771c123c0615531c2cc608b222949b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83440 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13mb/google/byra: Add VBTs for variants missing themMatt DeVillier
Several brya variants were missing VBT files, add and select them in Kconfig. Also select in Kconfig for VELL, which already had a VBT but was not using/selecting it. TEST=build/boot google/brya (marasov), verify display init functional / payload screen shown. Change-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83434 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13mb/google/hatch/var/jinlon: Replace hardcoded address with device typeMatt DeVillier
Eliminates the use of a magic number, and the resulting DID entry in the _DOD method is the same. The first entry was already changed in commit 1810a1841528 ("mb/google/*: Replace use of gfx/generic addr field with display type"), this one was missed. TEST=build/boot google/jinlon w/o privacy screen, dump SSDT and verify DID entry is unchanged but _ADR is now correct (since the DID flags are not part of the address field). Change-Id: Ief22928ea831d4cb5b483406ac388218a97ad98b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-13mb/system76/whl-u/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: Iebe5f8729d463767f5a1b52c375d11bb9d413144 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-07-13mb/system76/oryp5/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: I4769f255ce5652a9969ad6535c997ec1ad0be8d2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-07-13mb/system76/cml-u/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: Ic33bf07041a8c966dce66109c577621513147609 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78838 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13mb/system76/addw1/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: Ide536c74683416b34b0984fe1bddb250e72b045b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-07-13mb/system76/oryp6/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: Id3605e8e05d9d97a73af966459692276265df8bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78836 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13mb/system76/bonw14/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: I2b0e19581e0f0111a56bc57185acfcdd70588141 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78835 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13mb/system76/gaze15/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: I290fcfdd7b2cff61c4f6cd153133c5205c6fd6d1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-07-13libpayload: Unconditionally handle "CBMEM_ID_CSE_*" entriesSubrata Banik
This change removes the unnecessary conditional compilation around CBMEM_ID_CSE_BP_INFO and CBMEM_ID_CSE_INFO handling in cb_parse_cbmem_entry. These CBMEM IDs are only relevant on platforms with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD enabled, and platforms without this config option won't encounter these IDs when calling cb_parse_cbmem_entry(). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Icf056f8426015e99509be5f5a67cb66468645cd9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-07-13soc/intel/alderlake: Fix system hang by enabling SMI handlingJamie Chen
Issue: System hang occurred due to unhandled SPI synchronous SMI, triggered by LOCK_ENABLE bit and WPD assertion. Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration to allow the system to handle and clear SPI synchronous SMI. BUG=b:350623902 TEST=reboot test on 40 google/xol by ODM, all passed w/o hang. Change-Id: I4c14b1e3d537e46e671e950c91c9d0042fe26836 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83432 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Edward Doan <edoan@chromium.org>
2024-07-13mb/google/brask/var/bujia: remove DPTF fan controlShon
Fan control is assign to EC handle now. Remove relate setting on coreboot. BUG=b:351917517 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: Iff0776ce3db6f27e250162357abb3c7e9b1a0dc3 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83380 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-12skl/kbl mainboards: Move PCIe related settings into their device scopeFelix Singer
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-07-12soc/intel: Adapt crashlog IP to also support 64-bitSowmya Aralguppe
This patch extends the crashlog IP support beyond 32-bit mode to support Intel future generation SoCs, which may require crashlog support for 64-bit architectures. uintptr_t data type is used for Address pointers and void* for dereferencing BUG=b:346676856 TEST=Successfully built Meteor Lake (rex) and tested for google/rex0 and google/rex64 images. Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12mb/google/brox/var/lotso: Add FW_CONFIG for FPWentao Qin
This patch adds FW_CONFIG to accommodate different Lotso BoM components across various SKUs. 1. Fingerprint sensor - FP Present/Absent BUG=b:350360162 BRANCH=None TEST=Boot image on SKU2 and check FP working. Change-Id: I1ee5fcd1c29099bdbee741ef76c00cf45fcc1189 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83388 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12mb/intel/mtlrvp: Set USB2-10 as cnvi_wifi bluetooth companion deviceJeremy Compostella
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. This commit also updates the USB2 port 10 description and set its type to the more appropriate `UPC_TYPE_INTERNAL' type. BUG=b:348345301 TEST=BRDS method is added to the CNVW device and returns the data supplied by the SAR binary blob Change-Id: I66c9b75d2aaa1b221313b037defcd2c579fd6b61 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com>
2024-07-12amdfwtool: make fields unsignedGeorge Burgess IV
The value stored in `gen` is only ever `1` or `0`. Storing `1` causes Clang to warn, since the only valid values for a 1-bit int are -1 and 0: ``` amdfwtool.c:1487:27: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] 1487 | amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; ``` TEST=Rebuilt coreboot; no warning was emitted. Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Signed-off-by: George Burgess IV <gbiv@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83412 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2024-07-12mb/google/nissa/var/riven: add fw_config probe for storage devicesDavid Wu
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices, this is used for the first boot in factory. 2. Add fw_config probe to enable/disable devices in devicetree instead of variant.c, it can avoid suspend(s0ix) fail issue. BUG=b:328580882 TEST=On riven eMMC and UFS SKUs, boot to OS and run `suspend_stress_test -c 10` pass. Change-Id: I518f1a5955fb88f304663112f1e3d4c744bde183 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83405 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12mb/google/brask/var/bujia: Disable thunderboltShon
Bujia does not support Thunderbolt anymore, therefore disable related TBT setting. The bujia fit image CL, cf. chrome-internal:7468938. BUG=b:349923139 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. Change-Id: I4301a1f744aa9d4de9f0eba4147c49a4bb3ed922 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83402 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12soc/intel/cmn/cse: Correct CMOS error message for CSE partition firmwareSubrata Banik
The CMOS entry for CSE partition firmware was incorrectly labeled as `ramtop` and `partition firmware` in the error messages. This patch corrects the messages to accurately refer to `CSE partition firmware`. Additionally, the alignment and size check comments are updated to reflect this change. Change-Id: Ib3a7fb88f52c4d0c47d828bcd1c4649e62d19654 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-11Update amd_blobs submodule to upstream mainMatt DeVillier
Updating from commit id ae5fc7d: 2024-03-15 19:58:57 +0100 - (picasso: Update PSP fw to version 00.08.14.7B) to commit id 26c5729: 2024-07-10 10:10:50 -0500 - (CZN: Update SMU fw to 64.72.0) This brings in 2 new commits: 26c5729 CZN: Update SMU fw to 64.72.0 942adff Add VanGogh blobs Change-Id: I4c699379a196a0819201f7a6c9f1b3319edef4ff Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-11libpayload/x86: Add x86-64 support to rdtsc()Subrata Banik
This patch adds support for x86-64 to the rdtsc() function, allowing it to correctly read the Time Stamp Counter (TSC) on both 32-bit and 64-bit x86 architectures. BUG=b:242829490, b:351851626 TEST=Builds and boots on google/rex0 and google/rex64 systems and manually verified correct TSC readings on x86-32 and x86-64 hardware. Change-Id: I0afac3db2e82a245a37c2e5cf2302bf1dad62c01 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-11soc/intel/cmn/cse: Refine boot partition loggingSubrata Banik
This patch ensures CSE boot partition (RO/RW) version information only log when the status is "success". If the status is not successful, log an error message indicating the failure and status code. This change avoids logging potentially incorrect version information when the boot partition is not valid. BUG=b:305898363 TEST=Builds successfully for google/rex variants. Change-Id: I1932302b145326a1131d64b04af1cbfd6d050b7b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11mb/google/rex: Refactor CSE config options for model-specific settingsSubrata Banik
This patch refactors CSE config options, moving the selection of: * `SOC_INTEL_CSE_LITE_SKU` * `SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2` * `SOC_INTEL_CSE_SEND_EOP_ASYNC` from the generic `BOARD_GOOGLE_REX_COMMON` to individual board models. This enables finer-grained control over CSE features and sync behavior on different Rex and variants platforms. Specifically: * `google/rex0`: Selects `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot. * `google/rex64`: Selects `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` and `SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD` to defer CSE sync to the payload. BUG=b:305898363 TEST=Builds successfully for google/rex variants. Change-Id: Ib5957496b1e1dad8d135b3e10541cb83dd339539 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83397 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/intel/meteorlake: Conditional selection of CSE Lite PSRSubrata Banik
This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being enabled. This ensures that CSE Lite PSR is only active when both ChromeOS is the target platform and CSE sync is performed inside coreboot. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/intel: Extend CSE RW Update and ME read access for payload syncSubrata Banik
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and `ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`. This allows these features to be enabled even when CSE sync is performed in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU` config is enabled). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-MSubrata Banik
This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibilitySubrata Banik
This patch refactors the handling of CSE CBMEM IDs to enable platforms to choose whether to perform CSE sync operations within coreboot or defer it to the payload. This separation improves code organization, ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks. Now, platforms can select: * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync This change ensures mutually exclusive options, avoiding unnecessary SPI flash size increases. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11mainboard/dell: Add new mainboard XPS 8300 (Sandy Bridge)Ronald Claveau
Mainboard is identified as 0Y2MRG. The version tested is with Nvidia dGPU (gfx 560ti). The flash is a 4MiB Winbond W25Q32BVSIG. It can be flashed internally with flashrom. Add a strap on the service mode pin of the mainboard for internal flash. Tested working: - SeaBIOS - All USB ports - SATA - dGPU - Ethernet - Environment control - GPIOs - S3 Sleep mode - WakeOnLan Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059 Signed-off-by: Ronald Claveau <sousmangoosta@aliel.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-11drivers/qemu: Clarify config option name for QEMU display resolutionAlper Nebi Yasak
A previous commit splits out Cirrus display support from Bochs display support, with both using the pre-existing Bochs config options for the requested display resolution. Rename these config names to clarify they are not only specific to the Bochs display driver. Change-Id: Ie0a5e75731231bb768d7728867196c9ab5c53a00 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-11drivers/qemu: Split Cirrus display support from Bochs display supportAlper Nebi Yasak
QEMU's Cirrus display device is supported along with the Bochs driver since commit 7905f9254ebc ("qemu: cirrus native video init"). It is no longer the default since QEMU 2.2. The code supporting it can work independently of the Bochs display driver and depends more heavily on port I/O and VGA support code, so split it from that code to make it easier to support the Bochs driver in other architectures. Change-Id: Ic9492b501ed4fdcbda6886db60b1e5348715e667 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-11mainboard/qemu-aarch64: Set CONFIG_PCI_IOBASE to 0x3eff0000Alper Nebi Yasak
Define the PCI I/O base address necessary to use port I/O functions on the qemu-aarch64 mainboard, so that we can get the VGA display devices working. The config value is from hw/arm/virt.c [1]: [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, [1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.3/hw/arm/virt.c#L164 Change-Id: I85439ba68740d64f789983b37d9c95f849ce4f72 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82059 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11sconfig: Provide simple constants for aliased devicesNico Huber
Expose aliased PCI and PNP devices as `pci_/pnp_devfn_t` constants in <static_devices.h>. They will be named `_sdev_<alias>` to have a underscore prefix for consistency and to not collide with the `struct device` objects (with `_dev_` prefix). Change-Id: I2d1cfe12b1e7309f8235c84dd220bd090ebfe1b5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-11sb/intel/smbus: Implement smbus_send_byte()Nico Huber
Allows to use this driver for the SMBus console without sending an index byte for every sent char (i.e. !CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER). Tested with WiP VIA CX700-M2 port and FT4222H as receiver. Change-Id: Ic368ef379039b104064c9a91474b188646388dd2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/amd/phoenix: Fix APOB NV size/base for non-vboot buildsMatt DeVillier
The APOB NV size/base are embedded into the amdfw binary and read by the PSP. These need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Myst boards. TEST=untested, but same change as made for Mendocino Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-07-11soc/amd/mendocino: Fix APOB NV size/base for non-vboot buildsMatt DeVillier
The APOB NV size/base are embedded into the amdfw binary and read by the PSP. These need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Skyrim boards. TEST=build/boot Skyrim (Frostflow), verify RAM training only run on first boot after flashing. Change-Id: I9be1699d675331b46ee9c42570700c2b72588025 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83400 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-07-11console/i2c_smbus: Allow to send data w/o register offsetNico Huber
Not every I2C target requires a register address. Not sending one for every console char saves us a lot of overhead. Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82762 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10autoport: Drop ioapic, ioapic_irq, and lapic handling for devicetreeNicholas Chin
The ioapic and ioapic_irq keywords are no longer valid tokens as of commit e84b095d3a23 (util/sconfig: Remove unused ioapic and irq keywords), and the associated driver had previously been removed in commit ca5a793ec31c (drivers/generic/ioapic: Drop poor implementation). Thus, drop them from autoport. Also, the IOAPICIRQs map that this code relied on to generate ioapic_irq entries never seems to have been populated by any code in any previous commit, so this appears to have been dead code since autoport was created. The lapic keyword was removed from sconfig in commit 15d5183e4af7 (util/sconfig: Remove lapic devices from devicetree parsers) so remove autoport handling for it as well. Change-Id: Icf2582594b244cf5f726c722eb3a3c12573a2662 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-10console: Fix I2C/SMBus console if it's the only slow oneNico Huber
Change-Id: Ie44fdac6904a4467e408882bb8a5e08e6ff73f32 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82761 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-10cbmem_top: Change the return value to uintptr_tElyes Haouas
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10mb/google/brask/var/bujia: Add wireless and memory thermal sensorShon Wang
Bujia has 4 thermal sensors, so add two missing sensors settings. BUG=b:351917517 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. check ACPI SSDT table have new TSR info. $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT check SSDT.dsl Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-10emulation/qemu-q35: Remove redefine TSEG_SZ_MASKElyes Haouas
TSEG_SZ_MASK is already defined in "q35.h" Change-Id: I32ea08c18e1c41d16137ea14a1643f8c8d527722 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83386 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10Documentation: Use pkgconf over pkg-configElyes Haouas
Change-Id: I3e9a92d019854214a5760f705b9cbe3cabe6d2e8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-07-10xcompile: Use one line per CLANG_CFLAGS_${TARCH} flagElyes Haouas
Change-Id: I5c649898218a9c5d51d18a35264e9636e3dee179 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-09ec/google/chromeec: Stop checking CBI for UCSIAbhishek Pandit-Subedi
The ucsi_enabled flag is no longer used by the EC. Update coreboot to only use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled. BUG=b:319124515 TEST=emerge-brox coreboot chromeos-bootimage Cq-Depend: chromium:5664227 Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7 Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83252 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Forest Mittelberg <bmbm@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-09releases/coreboot-24.08: Remove ACPICA lineElyes Haouas
ACPICA reverted from 20240321 to 20230628 (commit 7c1813c1). Change-Id: Id238f77c6a0b4052ae3d835caf98aaf26a7e570f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-09Documentation/Makefile: Fix test targetNicholas Chin
The test target called make with the `-K` flag, which is not valid. Change it to `-k` (keep going if some targets fail) which is what was probably intended. It also tried to build the `doctest` target from Makefile.sphinx, which results in an error. Further investigation reveals that this is because the sphinx doctest extension was not enabled in conf.py. However, from the documentation of doctest [1], it seems like it is intended to ensure that documentation containing Python snippets along with the expected output of the snippet remain in sync, which is something that we probably don't need. So, remove the call to it. [1] https://www.sphinx-doc.org/en/master/usage/extensions/doctest.html" Change-Id: Id514950b4486ed8644d078af222c96ed711fc8f9 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83381 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-07-09Documentation: Fix header levelsNicholas Chin
This fixes the following MyST Parser warnings: - Non-consecutive header level increase - Document headings start at H2, not H1 The header levels (the number of "#" characters before a heading) are intended to form a logical hierarchy of each section and subsection in a document. A subsection typically should have a header level one more than its parent section. Most of these warnings are caused by extra "#" characters, which were simply removed, or sections missing a "#" character to make it fall under its parent section. Notable changes: getting_started/kconfig.md: Changed the header level of the "Keywords" section from 2 to 3 to fall under "Kconfig Language" (level 2), and increased the level of each keyword from 3 to 4 to remain under "Keywords". This also fixes the warnings of "H3 to H5" increases, since the Usage/Example/Notes/Restrictions sections for each keyword had a level of 5. soc/intel/cse_fw_update/cse_fw_update.md: Changed the first line to a top level header acting as the title of the document. Without this soc/intel/index.md displays all the level 2 headers in this document instead of a single link to cse_fw_update.md. Change-Id: Ia1f8b52e39b7b6524bef89a95365541235b5b1b9 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83382 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-07-09Docs: Fix paths in references to other markdown documentsNicholas Chin
This fixes a few "cross-reference target not found" warnings from MyST parser. In these cases, the relative path to the target markdown document was incorrect. Change-Id: I5d01deacc3ba7401faba30fc832e2357d4aedad8 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83383 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-09mb/asrock/z97_extreme6: Fix EDID mapping for DVI-IAngel Pons
This board has a DVI-I connector, which supports both digital and analog display outputs. The I2C bus to retrieve the EDID is shared between both outputs, so `select GFX_GMA_ANALOG_I2C_HDMI_B` to describe this. Can't currently test this due to lack of hardware. Change-Id: Ib8239917e2f7ee5bb982621752ec406c2d3ca302 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82753 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-09Documentation: Remove explicit install of 'm4'Elyes Haouas
Remove m4 as it will be installed automatically by flex and bison. Change-Id: Ifb748e5aaabb96825813ddb92cf28d2ea7bdcbf9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-07-09Doc/tutorial/part1.md: Correct libncurses-dev pkg name for debianElyes Haouas
Change-Id: I5a71b914d40a9ea45be87f4581ff0072605e8c00 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-07-09payloads/ipxe/kconfig: Fix option name prefixFelix Singer
With commit 238ff1e9c7 ("payloads/ipxe: Prefix iPXE options with "IPXE" instead "PXE""), the prefix for iPXE related Kconfig identifiers was unified to "IPXE". So rename the identifier for the TRUST_CMD option as well, which was introduced later. Change-Id: I918358b859003503526ba7849494bb23f8c893fd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83361 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-08Makefile.mk: Fix int-shift-leftMaximilian Brune
commit 4a8d73d6a4 ("Makefile.mk: Remove bc dependency") broke the left shift, since the expr tool does not support shifting operations. This patch uses the left shift operator inside arithmetic expansion. Every posix shell should support this. Tested: Build amd/birman mainboard and check that the soft-fuse parameter doesn't change. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If3b29dae727875b0788100a2cb02c86736ffaf8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83377 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-07-08chromeec: support reading long battery stringsPeter Marheine
The Chrome EC currently supports two ways to read battery strings on ACPI platforms: * Read up to 8 bytes from EC shared memory BMFG, BMOD, ... * Send a EC_CMD_BATTERY_GET_STATIC host command and read strings from the response. This is assumed to be exclusively controlled by the OS, because host commands' use of buffers is prone to race conditions. To support readout of longer strings via ACPI mechanisms, this change adds support for EC_ACPI_MEM_STRINGS_FIFO (https://crrev.com/c/5581473) and allows ACPI firmware to read strings of arbitrary length (currently limited to 64 characters in the implementation) from the EC and to determine whether this function is supported by the EC (falling back to shared memory if not). BUG=b:339171261 TEST=on yaviks, the EC console logs FIFO readout messages when used in ACPI and correct strings are shown in the OS. If EC support is removed, correct strings are still shown in the OS. BRANCH=nissa Change-Id: Ia29cacb7d86402490f9ac458f0be50e3f2192b04 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-08Makefile.mk: Remove bc dependencyMaximilian Brune
bc was added as dependency in commit 229e021110 ("Makefile.inc: Add left shift macro") bc is not stated as dependency in our docs (e.g. package installation). If you don't have bc installed you can easily get false positives on coreboot builds. For example you build a mainboard and coreboot tells you the build succeeded, even though you don't have bc installed. This patch is from julius comment on CB:21601. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I6ab4bc2bd7a45e84b923d4fe7ec473e6c7db2146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-08util/ifdtool: dump SPI modes from FLCOMPAlexander Goncharov
These fields are documented in the Alder Lake-S Client Platform SPI Programming Guide, but they are not presented in the Skylake-LP Client Platform SPI Programming Guide Change-Id: I624fe5cb28aa3cb207bc48aa8d31b2a71b70bcf2 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-08cpu/intel/model_206ax: Allow PL1/PL2 configurationAnastasios Koutian
Tested on ThinkPad T420 with the i7-3940XM. Change-Id: I064af25ec4805fae755eea52c4c9c6d4386c0aee Signed-off-by: Anastasios Koutian <akoutian2@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-08mb/google/brox/var/lotso: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control,according to b:348285763#comment6. BUG=b:348285763 TEST=emerge-brox coreboot Change-Id: I67e16a2596884d501273a5787119406dff7a20f9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83304 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-08mb/google/brya: Select Intel PDC to PMC CONFIGURATION for orisaAmanda Huang
Orisa uses PDC<->PMC direct connection for USBC mux configuration. Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. BUG=b:345070027 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I3f740bedc8ff667d15f077fa57d201ab0d42ebf8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83324 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2024-07-08mb/google/trulo/var/orisa: Add fw_config field for PDC controlAmanda Huang
Add a new fw config field to determine which firmware edition shall be flashed to the PDC. BUG=b:334793686 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I817e9415aca1d2f68b484d8e23b581e1a75d6f84 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83353 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-06util/sconfig: Remove unnecessary strdup() callsJakub Czapiga
getopt() optarg value can be used without duplicaing if it is not modified, as it is the case here. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie5a27f64077af1c04b06732cd601145b8becacfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/70525 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-05tgl mainboards: Move PCIe root port settings into their device scopeFelix Singer
Change-Id: I110cc95d536cb0fd3b5db85b84cca7a96e31401c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83253 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-05autoport: Print location of generated sourcesNicholas Chin
Autoport determines the mainboard vendor and board names based on DMI entries, which sometimes doesn't result in the most obvious name. In addition, newcomers may not be familiar with coreboot's directory structure and have no idea where to look. Print out the absolute patch of the generated sources once autoport finishes so that it is easier to locate the files. Change-Id: I4ba00484ac57355d7539fa6e36e0e6df62719f8a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83344 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-05autoport: Factor out GPIO config generationNicholas Chin
Intel chipsets from ICH7 through Lynxpoint use the same GPIO register format and thus mainboards using using these platforms have similar gpio.c files. Factor out the code to generate gpio.c from bd82x6x.go so that it other chipsets added to autoport can use it. This was originally written by Iru Cai in his Haswell autoport patch in CB:30890; I have simply split out the code to a separate commit as it is a separate logical change. TEST=Generated output is identical before and after this patch when run against logs from a Dell Latitude E6430 Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83286 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-05util/liveiso/nixos: Install flashprogFelix Singer
Change-Id: Id0a0de9bbbe2d3b0885bec2abea0a2022a7e1cbb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-05payloads/external: don't prevent parallel build of iPXESergii Dmytruk
When starting a nested instance Make communicates information on the number of jobs and how to synchronize difference instances via MAKEFLAGS variable. Explicitly overwriting it when invoking payloads/external/iPXE/Makefile ends up forcing serial build of iPXE. iPXE builds hundreds of files and its dependency generation is done separately from compilation making the whole process take couple minutes on a single CPU (which becomes several seconds if large enough number of CPUs is available). iPXE seems to have Make-based build system that has no problems with parallel build and not utilizing that effectively turns it into a bottleneck when building a coreboot image in parallel. It's unclear whether MAKEFLAGS= was even added for any particular purpose. It doesn't prevent child instances from using variables of parents, nor it prevents child instance from running in parallel (because it's still passed as an environment variable that's processed prior of variable assignments on command-line), but it does prevent grandchild instance from running in parallel (actual iPXE's Makefile). MFLAGS contains flags from MAKEFLAGS and isn't used implicitly by Make, so no need to clear it either because iPXE doesn't use it. Change-Id: Iac00e2f86d160793d3217e00ddc5012202b3196a Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-07-05mb/google/brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSWentao Qin
SKU1 is UFS, SKU2 is NON-UFS, it needs to select this config to disable the MPHY clock in the SKU2 configuration to ensure that S0ix functions normally. BUG=b:350609955 BRANCH=None TEST=Boot image on SKU1/SKU2 and check S0ix working. Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-04soc/amd/common/acpi/ivrs: use PCI_DEVFN macroFelix Held
Use the PCI_DEVFN macro to make the calculation of the ivhd->device_id value a bit clearer. TEST=Timeless build results in identical binary for Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b7949ad3524790e7d7d527c488a32e785f55bc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83343 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-04util/liveiso/nixos: Update to 24.05Felix Singer
Change-Id: I62dc3a7fd5b8aef467fc547015f23e41d3260122 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-04mb/google/lotso: Add hid report address for gt7986uKun Liu
Add hid report address for gt7986u. BUG=b:342932183 BRANCH=None TEST=Verify touchscreen work normal. Change-Id: I464c2691505083314528519f608108c8a31e6cc0 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83201 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-04drivers/spi/acpi: Update generic property listKun Liu
Update generic property list for build test result fail https://qa.coreboot.org/job/coreboot-gerrit/259702/ BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iecd8573343706184dce5edfc12fe7a143390e0e9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83301 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-07-04mb/google/nissa/var/domika: Create a domika variantWisley Chen
This patch creates a new domika variant which is a Twin Lake platform. This variant uses Yavilla board mounted with the Twin Lake SOC and hence the plan is to reuse the existing yavilla code. BUG=b:350399367 BRANCH=firmware-nissa-15217.B TEST=build, and boot into OS Change-Id: I42c56770f8b8d6018592253d2bb16b8166eb5719 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-04mb/google/brya: disable early EC sync for orisaAmanda Huang
Disable VBOOT_EARLY_EC_SYNC for all trulo boards. BUG=b:345112878 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I10b027d19dedbb190fc960b949017f9e4830d52a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83303 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>