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2022-08-27util/docker/coreboot-sdk: Install GNAT 12Felix Singer
For some reason GNAT 11 is not able to build GNAT 12, since there are some Ada errors during the compilation. However, it works with GNAT 12. So use GNAT 12 for the host toolchain instead. Change-Id: If00a05a0c8564e624809268a12fae28261e380a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-27util/docker/coreboot-sdk: Replace package qemu with qemu-systemFelix Singer
The qemu package doesn't exist anymore or it was renamed. Instead of installing QEMU for all available architectures, install only the packages which ship architectures that are supported by coreboot. * qemu-system-arm * qemu-system-misc (for RISC-V) * qemu-system-ppc * qemu-system-x86 Change-Id: Ifc46a8c9fcb1ab3c38dc8cbbc906882e93a719d7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-27soc/mediatek/mt8188: Enable USE_CBMEM_DRAM_INFOXi Chen
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8188. Therefore, we select this configuration to enable it. TEST=build pass BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I14f3d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66280 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27soc/mediatek: Move emi.c to common folderRex-BC Chen
The emi.c is the same for MT8186 and MT8188, so we could move it to the common folder and reuse it. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I225f1d07c973129172f01bf7f4d7f5d5abe7c02b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66328 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27drivers/mrc_cache: Don't compute checksum if TPM hash is usedReka Norman
When MRC_SAVE_HASH_IN_TPM is selected, mrc_data_valid() uses the TPM hash to verify the MRC cache data, not the checksum. However, we still calculate the checksum when updating the cache. Skip this calculation when MRC_SAVE_HASH_IN_TPM is selected to save boot time. On nissa, this reduces boot time by ~14 ms: Before: 3:after RAM initialization 854,298 (28,226) After: 3:after RAM initialization 849,626 (14,463) Note, the reason the calculation is so slow is that the new MRC data lives in CBMEM, which is not yet marked as cacheable in romstage. BUG=b:242667207 TEST=MRC caching still works as expected on nivviks. After clearing the MRC cache, memory training happens on the next boot, but doesn't on subsequent boots. Change-Id: Ifbb75ecfa17421c0565aec1f3eb48d950244f821 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-27mb/google/corsola: Add new board Magikarpvan_chen
Add a new board 'Magikarp', and enable SDCARD_INIT for it. BUG=b:242822419 BRANCH=None TEST=none Change-Id: Id7432e33b6fd5f1c25536cf068ff76612575e8ee Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
2022-08-27soc/mediatek/mt8188: Add DRAM fast calibration supportXi Chen
Define fields of sdram_params and enable MEDIATEK_BLOB_FAST_INIT to run fast calibration for MT8188 using blob. DRAM fast calibration logs: DRAM-K: Fast calibration passed in 19530 msecs dram size (romstage): 0x200000000 TEST=Fast calibration pass. BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2468d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-27mb/google/geralt: Fully calibrate DRAMXi Chen
Initialize and calibrate DRAM in romstage. DRAM full calibration logs: dram_init: dram init end (result: 0) DRAM-K: Full calibration passed in 50176 msecs TEST=Full calibration pass. BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I31f5693ffe4a1e30defbc8a96dc128de03d6b7e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66278 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27soc/mediatek/mt8188: Add DRAM full calibration supportXi Chen
- Use common SoC drivers for DRAM calibration support. - Remove emi.h because sdram_size() is already declared in common/include/soc/emi.h. - Add dramc_param.h and dramc_soc.h to prepare for implementation of DRAM full calibration. TEST=build pass BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2f88d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-27util/docker/coreboot-sdk: Remove doxygenTom Hiller
Doxygen was removed at the project level. Remove the doxygen Debian package and make target. Change-Id: Ib82ba7890e7f53357eeca318b5f844164747aecd Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67039 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27mb/google/rex: Disable LID_SHUTDOWNSubrata Banik
This patch disables LID based shutdown requests. Google/Rex platform receives a forced shutdown request while booting to depthcharge due to EC wrongly detecting the LID is being closed. For now disable the LID based shutdown behaviour in depthcharge unless the EC issue gets resolved. BUG=b:243920003 TEST=Depthcharge no longer sees the force shutdown request now. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I03e33ea4d04dc48331d1cf98c47786b2a184c258 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-26tests/memrange-test: Correct final end test in test_memrange_steal()Nico Huber
If an inserted region's base wasn't aligned, the resulting range should still cover the original end (original region's base + size) and not the aligned-down base + size. Change-Id: I8f1c9456d6dbab4fa868de5c93fa3656397e54c1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66607 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/meteorlake: Update MTL_USE_COREBOOT_MP_INIT descriptionSridhar Siricilla
The patch update MTL_USE_COREBOOT_MP_INIT Kconfig description. TEST=Build code for MTL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I38609cb03714084dd9092f41dd6e5b418a7f120a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-26ec/google/chromeec: Call PNOT() when Battery Status ChangesTim Van Patten
PNOT() should be called when the battery status changes, to give the SOC an opportunity to handle it. This is in preparation for the low/no battery boot changes. This CL also updates the PNOT() comments to better match the name of the function and why it's called. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Change-Id: I8b74313d242fd4959315a67579eb6c5f49a31a76 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66993 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-26x86: Zero SMBIOS region before writing tablesJonathon Hall
Clear the SMBIOS region before writing SMBIOS tables. On librem_mini and librem_mini_v2, CBMEM allocations are offset by 4K for reboots relative to the cold boot. This means the unused SMBIOS region could contain the first 4K of the ACPI tables from the last boot (including the signature), which prevents Linux from booting. The CBMEM 4K offset appears to be due to FSP allocating memory differently between cold boot and reboot, this appears to be normal and causes the CBMEM base address to change. It is not clear why Linux examines an ACPI signature found in this region, but boot logs over serial confirm that it sees the corrupt table. The table is supposed to be found just below 1M, and kernel source appears to look in this region, but it is definitely finding the corrupt table in CBMEM. Normal cold boot: [ 0.008615] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4) [ 0.008619] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008624] ACPI: FACP 0x0000000099B4A2A0 000114 (v06 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008634] ACPI: DSDT 0x0000000099B48280 00201F (v02 COREv4 COREBOOT 20110725 INTL 20220331) ... Reboot with corrupt table: [ 0.008820] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4) [ 0.008823] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008828] ACPI: ???G 0x0000000099B4A2A0 20002001 (v00 ?G?$ 47020100 ?, 47020100) [ 0.008831] ACPI: �y 0x0000000099B4A3C0 54523882 (v67 ?_HID? A�? 65520D4E al T 20656D69) ... There are no specific errors but it returns to the firmware soon after, presumably due to a fault. This appears to be so early in the boot that panic=0 on the kernel command line has no effect. Test: build/boot Librem Mini, Librem Mini v2 and reboot. Change-Id: Ia20d0b30160e89e8d96add34d7e0e881f070ec61 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66377 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-26mb/google/nissa/var/pujjo: Add FW_CONFIG probe for new audio devicesLeo Chou
Add FW_CONFIG probe for new audio sku: ALC5682I + MAX98357 BUG=b:243474931 TEST=Boot to OS and verify audio devices are set based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I16af6cf4644c473034e184e95ff2038ca31b20de Reviewed-on: https://review.coreboot.org/c/coreboot/+/67016 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/mtl: Activate TME on all CPUsTarun Tuli
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per MTL processor EDS. TEST= Able to build and boot RVP. Confirmed TME supported mode detected via temporary debug prints and MSR 0x9ff indicates activated. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Id368925504d81025239e94698d2cb0e2266a5a96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66949 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26mb/google/nissa/var/craask: Enable Cnvi BT Audio Offload featureTyler Wang
This patch enables Cnvi BT Audio Offload feature and also configures the virtual GPIO for CNVi Bluetooth I2S pads. BUG=b:239670216 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ibc7116e8dc5367fd94d29aba36b91778d0c21e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-26tests/memrange-test: Correct commentary on test_memrange_steal()Nico Huber
Currently, memranges_steal() steals at the lowest possible address. This is actually reflected by the test code that checks if the *base* of the READONLY_TAG range changes. Furthermore, the test ends with the memranges restored, so revise the comment on the final state. Change-Id: Idef71ce464280c6805145f229de9e8913ba850bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66606 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26ec/starlabs/merlin/cml: Correct the offset for Max ChargeSean Rhodes
The offset for Max Charge is located at 0x1a, so correct this in the definitions and EC memory ACPI. Change-Id: I92cc452d1189e62db78aed787f2de65fd5096564 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-26mb/google/brask/variants/moli: Override tdp pl1 valueRaihow Shi
Follow the "619907 Alder Lake-S and Raptor Lake-S Platform" and "685472 Intel® Dynamic Tuning Technology (Intel® DTT)" to override tdp pl1 in 15w cpu MSR to 55w and in 28w cpu MSR to 64w. BUG=b:236294162 TEST=emerge-brask coreboot and check MSR_Package Power Limit-1 in 15w and 28w CPU is correct. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Icb3d7c72b672fbd3e2a9f7ad1f2d1cb2ffc798c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66910 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/amd/picasso: Reserve space for BIOS SIG in BIOS imageRitul Guru
Change-Id: I68667d084001c753e74ba480fa7b6e09b1b88cb8 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66369 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26util/amdfwtool: Add changes to reserve BIOS SIGRitul Guru
changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-26nb/intel/sandybridge: Align TOUUD down to 1 MiB granularityArthur Heymans
This register has a 1MiB granularity. The lowest bit is a lock bit. Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26mb/google/rex: Add mapping for GPIO_PCH_WPTarun Tuli
The define GPIO_PCH_WP needs to be mapped to GPP_H10 based on the Rex schematics 24/6/2022. TEST=Built and booted on Google Rex. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I2489c244bd4cbd9e10ed3db981a6e56a954b5e20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67083 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26mb/google/rex: Add mapping for EC_SYNC_IRQTarun Tuli
The define EC_SYNC_IRQ needs to be mapped to A17 based on the Rex schematics 24/6/2022. BUG=b:243781237 TEST=Successfully build rex and tested to ensure EC is now functional. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ib61ddc9f73dd7b817d3b990bef8f0169f7cafbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67082 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-26soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8dcee90080c6e70dadc011cc1dbef3659fdbc8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66951 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/p2sb: Refactor `p2sb_execute_sideband_access` functionSubrata Banik
This patch refactors p2sb_execute_sideband_access() to be able to handle SBI operations in both SMM and non-SMM scenarios. Prior to FSP-S operation being done, the IOE P2SB device will be visible on the PCI bus hence, performing the SBI operation using IOE P2SB doesn't involve unhide/hide operation. Post FSP-S, the IOE P2SB device is hidden. Additionally, SBI operations can't be performed as is. The only possible way to send SBI is inside SMM mode and to do that, coreboot needs to unhide the P2SB device prior to sending the SBI and hide it post sending SBI. As a result, the p2sb_execute_sideband_access() function has been refactored to manage these cases seamlessly without users of the p2sb_execute_sideband_access() actually being bothered about the calling mode. BUG=b:239806774 TEST=Able to perform p2sb_execute_sideband_access() function call in both SMM and non-SMM mode without any hang/die. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iafebd5190deb50fd95382f17bf0248fcbfb23cb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/amd: rework SPI flash MMIO region handlingFelix Held
Only 16 MByte of the SPI flash can be mapped right below the 4 GB boundary. In case of a larger SPI flash size, still only the 16 MByte region starting at 0xff000000 can be configured as WRPROT and be reserved for the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting at address 0xfe000000 contain for example the LAPIC MMIO region, the ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't be configured as WRPROT. Reserving this region for the MMIO mapped SPI flash would also result in an overlap with the MMIO resources mentioned above. In the case of a smaller SPI flash, reserving the full 16 MByte flash MMIO region makes sure that the resource allocator won't try to put anything else in the lower parts of the 16 MByte SPI mapping region. To avoid the issues described above, always reserve/cache the maximum amount of 16 MBytes of flash that can be mapped below 4 GB. TEST=On boards with 16 MByte SPI flash chips, the resulting image of a timeless build doesn't change with this patch. Verified this on Chausie (Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena (Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the resulting image of a timeless build is different, but neither the coreboot console output nor the Linux dmesg output shows any errors that might be related to this change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25mb/google/brya/variants/crota: fine tune WWAN power sequencingTerry Chen
Because the poweron state of some of the WWAN GPIOs is the asserted state, this patch fixes the poweron sequence so that the WWAN module is always correctly powered on, in both cold and warm reboot scenarios. BUG=b:233564770 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I4ec8312c30392b9ca0a3e0321cb4578e76ec5787 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-25MAINTAINERS: Update AMD maintenance listsMartin Roth
- Add legacy AMD reference boards - Add Google AMD mainboards - Add mailing list for code changes to all AMD sections - Update people in AMD groups Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ibd8001f8e4cd667bf9223dc32bc33a5a1dc9e89f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-25mb/google/rex: Update DQS for RexTarun Tuli
Update the DQS for Rex as per the latest Rex schematics (08/25). BUG=b:243734885 TEST=Built successfully. Confirmed on HW. Change-Id: I2a458a3da725f953cbba8a194ac6f314f5467419 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67041 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up Lp5CccConfig FSP UPDKapil Porwal
Hook up Lp5CccConfig FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up ECT FSP UPDKapil Porwal
Hook up ECT FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idc23717c3ce52e3635e2da41733058f912545e5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67051 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Program MCHBASE prior enabling extended bios rangeSubrata Banik
This patch resolves the SoC programming dependency order where enabling extended bios support requires MCHBASE to be enabled. BUG=b:243693375 TEST=Able to boot from RW-A slot which is mapped to extended BIOS range. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8bd9c3d3fb5e82e34f2d6af8548452c744d4b3c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67046 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25mb/google/rex: Configure GSC INT GPIO early in the bootKapil Porwal
This patch configures GPP_E03 (GSC_SOC_INT_ODL) as GPI/APIC in early GPIO tables. BUG=b:243641061 TEST=Able to build rex image. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I4aa180c7105be3f356a0bbd5b92b4ced628c34fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67017 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-25soc/amd/common/fsp/dmi: Set dimm voltage based on memory typeMatt DeVillier
Voltage set based on standard configuration for each type. TEST=build/boot google/skyrim, verify output in cbmem console log, DMI type 17 table. Change-Id: I9b1e68a9417e43cbb9c55b4c471664f3f9090342 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66981 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25soc/amd/common/fsp/dmi: Print MT/s speeds, not frequency in debug outputMatt DeVillier
Since the frequency field is deprecated, print the max/configured MT/s speeds instead. TEST=build/boot google/skyrim, verify output in cbmem console log Change-Id: Icee5af762ca37c3b2ec8c9a52a7f32fb848390b0 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66980 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25soc/amd/common/fsp/dmi: Translate DRAM speeds for (LP)DDR5Matt DeVillier
Hook up newly-added method to convert from frequency to MT/s so that boards which use (LP)DDR5 report their capability properly. BUG=b:239000826 TEST=build/boot google/skyrim, verify SMBIOS Type 17 table reports DRAM speeds correctly. Change-Id: I694b6c227a8d8fb40c897053808bc79df330ed0c Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66954 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25device/dram: Add function to convert freq to MT/s for (LP)DDR5Matt DeVillier
As the frequency field in the SMBIOS type 17 table is deprecated, we need to provide the maximum and configured speed in MT/s. Add a method to convert from frequency to MT/s using a lookup table. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I0402b33a667f7d72918365a6a79b13c5b1719c0d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25util/apcb/apcb_v3_edit: Add support for LP5X SDRAMRobert Zieba
This commit adds support for LP5X SDRAM. BUG=b:242765117 TEST=Ran with LP5X SPDs and manually patched APCB Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I2d3cb9c9a1523cb4c5149ede1c96a16c3991a5d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66840 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25util/spd_tools: Add support for LP5X SPDsRobert Zieba
This commit adds support for LP5X SPDs. The SPD format is identical to LP5 except that the memory type is set to 0x15 instead of 0x13. Since they are essentially the same, LP5/5X parts share the same parts JSON file and SPD directory. LP5X parts are distinguished by the optional `lp5x` attribute. This commit also updates two existing LP5X memory parts with the correct attribute. BUG=b:242765117 TEST=Generated SPDs, verified that SPDs generated from LP5X parts match their LP5 counterparts except for memory type byte. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-24payloads/edk2: Separate the tasks required to build edk2Sean Rhodes
Separate the tasks that are required to be completed prior to building edk2 into a prep recipe. This allows this to be used for building different targets. This also ensures that the COREBOOT toolchain is used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic4ae8ac4118a5747f38297d0fbf4cb53aa3b6d6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66359 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-24payloads/edk2: Separate the Release String variableSean Rhodes
Separate the Release String from the Build String. This allows the makefile to locate built files more precisely. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id98674f0bbf485b2bfdbf5784d325c5ac89ad076 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66358 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/google/skyrim: Create morthal variantMoises
Create the morthal variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_MORTHAL Signed-off-by: Moises <moisesgarcia@google.com> Change-Id: I25c25f067a040e6930f4fc60fadb8be85dc8eda6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-24mb/google/skyrim: Check if SPD existsIsaac Lee
Update the build script to check if SPD exists, and only if SPD exists the APCB_SBR_D5.gen could be executed. BUG=None TEST=Build Change-Id: Ib7b977a89d403242e8bb1f684269e70082125e88 Signed-off-by: Isaac Lee <isaaclee@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66978 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-24soc/intel/common/block: Drop empty smm.hAngel Pons
This file has nothing useful. Get rid of it. Change-Id: Id2a42005d3b4b5161079c9ff48867cfc6fb0413d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-24mb/google/brya/var/agah: Reenable ASPM L1 substatesTim Wawrzynczak
Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates can be enabled and appear functional. BUG=b:240390998 TEST=lspci reports them as functional, MODS does not hang Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/google/brya/var/agah: Update GPU GPIOsTim Wawrzynczak
Converge as many of the GPU's GPIOs to use PLTRST# as the reset signal explicitly, as the hardware engineers requested this. BUG=none TEST=boot and reboot agah, dGPU still visible on PCIe bus Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I78e58eb17cadc95083571affbecb4e1ce0adf16a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66809 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/google/brya/var/agah: Enable DPTF oem_variablesTony Huang
Support oem_variables and change based on EC notify event. BUG=b:238921409 TEST=emerge-draco coreboot 1. check ACPI object ODVX has oem_variable[0]=0 Name (ODVX, Package (0x06) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } 2. check can get EC oem variable change notify in the kernel log Change-Id: Ibd856563a43d73a3b1be09b3fbebca1b36b5eab1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66575 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24ec/google/chromeec/acpi: Add support for DPTF oem variable event notifyTony Huang
The agah EC code will monitor adapter current to choose corresponding DPTF oem variable table. When it changes, this event will send to the ACPI FW through host event and then pass onto the DPTF kernel driver. This patch adds support for that feature. BUG=b:238921409 TEST=add Printf() calls to the ACPI, and check these Printf() will show up in the kernel log when EC send oem variable table change notify. Change-Id: I1dbbfd9b3d65b56d77050c9ba9957e54530c3a0e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66574 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24libpayload: Add const for dma_coherent argumentYu-Ping Wu
Add the const modifier for the ptr argument of dma_coherent to avoid unnecessary type casting in payloads. BUG=none TEST=emerge-corsola libpayload BRANCH=none Change-Id: Ic4bb1d8318c7e83fd3ab3054aa0333cb27afe588 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Hsin-Te Yuan <yuanhsinte@google.com>
2022-08-24payloads/edk2: Move building to directory called workspaceSean Rhodes
The current edk2 makefile will work in a directory that's name is derived from the repository, such as `mrchromebox` or `starlabsltd`. Move this under a directory, so that it can be ignored by git and so that the makefile can be adjusted to use file targets, rather than phony recipes with wildcards. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If0c80dbc59130f229b78cab9578115e14172301d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66356 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24soc/intel/adl: Consider INTEL_TME config prior TME MSR programmingSubrata Banik
This patch brings INTEL_TME config check prior programming TME Set Activation Core MSR on all cores. TEST=Able to boot Google/Taeko to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8af7e305da1050f443929ab33be556e713e53e9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66976 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/starlabs/lite: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c12161d4868deae5b8900cfa2f42517a9f0b7e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24drivers: Implement EFI_PEI_MP_SERVICES_PPI with FSP_UNSUPPORTED typeSubrata Banik
This patch implements EFI_PEI_MP_SERVICES_PPI structure definitions with APIs that return mp_api_unsupported(). The reason behind this change is to fix an FSP issue where FSP assumes ownership of the APs (Application Processors) upon passing a `NULL` pointer to the CpuMpPpi FSP-S UPD.Hence, this patch implements `MP_SERVICES_PPI_DEFAULT` config to fill EFI_PEI_MP_SERVICES_PPI with `mp_api_unsupported` APIs. Later this data structure can be passed to the CpuMpPpi UPD to avoid APs from getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. TEST=Able to build and boot Google/Taeko with this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I31fcaa2aa633071b6d6bfa05dbe891ef87978d2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24soc/intel/alderlake/hsphy: Add support for HSPHY firmware loadingMichał Żygowski
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init. Implementation based on public Slimbootloader's "Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib". TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded. PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot. [DEBUG] HECI: Sending Get IP firmware command [DEBUG] HECI: Get IP firmware success. Response: [DEBUG] Payload size = 0x6944 [DEBUG] Hash type used for signing payload = 0x3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-08-24soc/intel/meteorlake: Enable GPIO 4 bits pad mode configurationJamie Ryu
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits GPIO pad mode to configure native function 8 to 15. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-24soc/intel/common/gpio: Support 4 bits GPIO pad mode configurationJamie Ryu
Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins that native function 8 to 15 is assigned. This adds native function definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support 4 bits pad mode configuration. Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not assigned, this change would not cause an issue but Kconfig option is added to minimize an impact and support 4 bits pad mode configuration. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-24mb/google/rex: add arbitrage gpio.c headerKevin Chowski
This comment header is necessary for supporting propagation of overrides to variants. Change-Id: Iee92fa4fbc4851c7032401cff99ea49f87717c7f Signed-off-by: Kevin Chowski <chowski@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-24src/arch/x86/smbios.c: remove unneeded bracesFabio Aiuto
fix the following checkpatch errors: WARNING:BRACES: braces {} are not necessary for any arm of this statement 354: FILE: src/arch/x86/smbios.c:354: + if (CONFIG_ROM_SIZE >= 1 * GiB) { [...] + } else { [...] WARNING:BRACES: braces {} are not necessary for single statement blocks 561: FILE: src/arch/x86/smbios.c:561: + if (leaf_b_threads == 0) { + leaf_b_threads = 1; + } Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I14c29e4358cad4cd5ef169ebab7079db2129d8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-24vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPEMatt DeVillier
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h. Add/correct values for DDR5, LPDDR5, LPDDR5X. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-24drivers/spi/tpm: Add Ti50 entry to dev_mapYidi Lin
BUG=none TEST=See "[INFO ] Initialized TPM device TI50 revision 83" Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I3af5f4653b6b8ecd086f85ec573530a4e5c57211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-23mb/**/hda_verb.c: Drop empty filesAngel Pons
These files are no longer required by the build system. Change-Id: I327e7c9211f46d4694591abab11cb38c9180bddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-23{sb,soc}/intel: Do not require hda_verb.cAngel Pons
Just use the conditional inclusion through `device/Makefile.inc`. Change-Id: Id363a97460ae2cfe4b10d491d4ef06394eb530c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-23drivers/siemens/nc_fpga: Fix typo in commentAngel Pons
earyl ---> early Change-Id: I06412fd9487aaa1115fdbd86ff44b34db97d97d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-08-22brya: add new skolas variantNick Vaccaro
Add a new skolas variant, which is a variant of brya's skolas baseboard. BUG=b:242869976 BRANCH=firmware-brya-14505.B TEST=none Change-Id: I7f9f0389d8b1bf75d8652cbcc9d0c15d3a529802 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-22lint-000-license-headers: Add src/sbom/TAGS to exception listFelix Singer
Commit 6dac0c54cd0b makes the linter checking for license headers on all files from the src directory. Since this TAGS file doesn't have one, it's causing a linter error and it makes the QA system complain. However, the TAGS file doesn't need a license header and thus add it to the exception list. Usually the build tests detect such issues, but commit 1d7a9debf241, which introduced that file, was merged independently from the other commit, which modifies the linter. Also, the patch that is introducing this file was based on an older commit at which the patch modifying the linter wasn't merged yet and so this issue was hidden. Change-Id: I78da3fa70c39b709478a384da8769fc058ca18ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66938 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22soc/intel/alderlake: Perform TME core activation on all CPUsSubrata Banik
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per Alder Lake Processor EDS. TEST= Able to build and boot Google/Redrix. Dumping MSR 0x9FF on all logical processors shows zero value being set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I130480d4fba413d47d0d0137932ec1fb041a88d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66753 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22soc/intel/cmn/cpu: API to set TME core activationSubrata Banik
This patch implements API to program TME core activation MSR 0x9FF. Write zero to TME core activate MSR will translate the TME_ACTIVATE[MK_TME_KEYID_BITS] value into PMH mask register. Note: TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35] TEST=Able to build and boot Google/Redrix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48cf8e255b294828ac683ab96eb61ad86578e852 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-22util/crossgcc: Remove binutils related MIPS patchFelix Singer
coreboot doesn't support the MIPS architecture anymore. So remove the MIPS patch. Change-Id: I62a2bca141b42ac33b628c48c84422570f4dda10 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-22Add SBOM (Software Bill of Materials) GenerationMaximilian Brune
Firmware is typically delivered as one large binary image that gets flashed. Since this final image consists of binaries and data from a vast number of different people and companies, it's hard to determine what all the small parts included in it are. The goal of the software bill of materials (SBOM) is to take a firmware image and make it easy to find out what it consists of and where those pieces came from. Basically, this answers the question, who supplied the code that's running on my system right now? For example, buyers of a system can use an SBOM to perform an automated vulnerability check or license analysis, both of which can be used to evaluate risk in a product. Furthermore, one can quickly check to see if the firmware is subject to a new vulnerability included in one of the software parts (with the specified version) of the firmware. Further reference: https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/ - Add Makefile.inc to generate and build coswid tags - Add templates for most payloads, coreboot, intel-microcode, amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM, intel ME and compiler (gcc,clang,other) - Add Kconfig entries to optionally supply a path to CoSWID tags instead of using the default CoSWID tags - Add CBFS entry called SBOM to each build via Makefile.inc - Add goswid utility tool to generate SBOM data Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-21soc/intel: Enable TME based on supported CPU SKU and config optionSubrata Banik
This patch removes the static kconfig being used to fill in TME enable FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check if the CPU has required TME support rather than hardcoding. TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the TME-supported CPU SKUs. As per FSP-M debug log: Without this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x1 With this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21tpm: Correct TI50_FIRMWARE_VERSION_NOT_SUPPORTED help textYu-Ping Wu
Reading firmware_version register is supported on Ti50 version 0.22.4. Therefore correct the help text of the Kconfig option TI50_FIRMWARE_VERSION_NOT_SUPPORTED. Also change the message level to BIOS_WARNING. BUG=b:234533588 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I66a0ef896c9dc4cd0f586555a55dbcd1cfd863f9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66906 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Pronin <apronin@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-08-21mg/google/corsola: Disable TI50_FIRMWARE_VERSION_NOT_SUPPORTEDYu-Ping Wu
Reading Ti50 version is now supported on Ti50 version 0.22.4. Therefore stop selecting TI50_FIRMWARE_VERSION_NOT_SUPPORTED for corsola. BUG=b:234533588 TEST=emerge-corsola coreboot TEST=cbmem -1 | grep 'Firmware version' BRANCH=none Change-Id: Id8d849eaf99542363c64e27411549eb6dddfd059 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66905 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Pronin <apronin@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-08-21mb/google/rex: Reshuffle CHROMEEC_* related configsEran Mitrani
1. Moved CHROMEEC_* to common (required for all boards) 2. added missing EC_GOOGLE_CHROMEEC_SKUID TEST=Verified with simics on RVP Change-Id: I26a01e5d1c78d4cd83b1aa53e68b2c3059da6061 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66762 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21soc/intel/common/block/cpu: API to check if TME is supportedSubrata Banik
As per the Alder Lake FAS coreboot shall detect the existence of TME feature by running the CPUID instruction: CPUID leaf 7/sub-leaf 0 Return Value in ECX [bit 13]=1 If TME is supported then only access to TME MSRs are allowed otherwise accessing those MSRs would result in GP#. TEST=Able to detect the existence of TME feature across different Alder Lake and Meteor Lake CPU SKUs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd4fcf15a66d27748ac7fbb52b18d7264b901cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66749 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to be user-configurable. However, it has been selected from Alder Lake and Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace the `select INTEL_TME` statements with default values in order for this option to be user-configurable on all platforms that support it. Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21Revert "mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants"V Sowmya
This reverts commit 2b19d547c0866fef84bdb7b226ce7a4ac81af64f. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BUG=b:240669428 TEST=verify that EPP is back to the by default 50% setting `iotools rdmsr 0 0x774' Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I76d3914e51c5320af4c202558e1e7c57b7c0de54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Usha P <usha.p@intel.com>
2022-08-21mb/google/brask/variants/moli: Support DPTF oem_variablesRaihow Shi
Enable DPTF oem_variables and override based on CPU match id. BUG=b:236294162 TEST=emerge-brask coreboot and check the value in odvp0 is correct. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21mb/google/nissa/var/pujjo: Add FW_CONFIG probe for Pujjoteen disableLeo Chou
bypass power Add FW_CONFIG probe to separate ext fivr settings for Pujjoteen and others(Pujjo and Pujjoflex) BUG=b:242663554 TEST=Boot to OS and verify that ext_fivr_settings are set based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6bb6d1701c55459cf331dd2f3ffe07f91bca2fa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21mb/google/dedede/var/shotzo: Enable ILITEK touchscreenTony Huang
The current reset delay is not enough to make touchscreen IC ready, ILITEK feedback their requiremt is 400ms in spec T2. After changing the reset_delay_ms and check touchscreen works, ILITE also change the IRO to low level trigger. This CL is to reflect that. BUG=b:235929123 BRANCH=firmware-dedede-13606.B TEST=check touchscreen function work Change-Id: I126b2d74c1d7a1799e2f67a8ab01cba074447c06 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-08-21mb/google/nissa/var/yaviks: Update GPIO settingWisley Chen
Configure GPIOs according to schematics. BUG=b:242277219 TEST=emerge-nissa coreboot Change-Id: Id7412059ba98d58f7014ab7201ea8958ede5905e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21mb/google/nissa/var/yaviks: Update devicetree settingWisley Chen
Update Devicetree according to yaviks's design. BUG=b:242277219 TEST=emerge-nissa coreboot Change-Id: I5d91cccbb44787bcbe7258a817ff97b6dce86c2e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21intel/systemagent: Align debug outputNico Huber
Output should be easier to read as a table. Change-Id: I32e3e0aab5afd25c0b004d18f64de76445d9a0ed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-21mb/starlabs/*: Disable INTEL_LPSS_UART_FOR_CONSOLESean Rhodes
Disable INTEL_LPSS_UART_FOR_CONSOLE to stop debug output on UART 2. This decreases boot time on all boards by around 60%. TGL before: Total Time: 10,110,807 TGL after: Total Time: 3,851,641 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8f8d5cd46e87e7dafe0669b4a29c872b1789eb60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-21mb/starlabs/starbook/kbl: Update verb tableSean Rhodes
The ALC269 does not support the hardware equaliser, so remove the entries related to this, as they have no effect. Revert to the ALC269 defaults which work correctly with Linux. This also corrects the subsystem id from 0x10ec111e to 0x10ec10d0. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I82647f67730ec344591f7dbd759a421c116d4fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-20mb/google/skyrim: Add ELAN touchscreenAmanda Huang
Add ELAN touch support BUG=b:243120074 TEST=emerge coreboot and check ELAN touch screen is workable Change-Id: If30232b3da9af0015d6d87535b53f905c5a30bcb Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66912 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Isaac Lee <isaaclee@google.com>
2022-08-20soc/amd/common/block/psp/psb: add missing amdblocks/smn.h includeFelix Held
smn_read32 is used in this file, so include the header file with the function prototype so that the file compiles successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5bef96cd08f22b3475e8b5ba4e984a6e1ab4da36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-20soc/amd/stoneyridge: move early I2C init to early_fch.cFelix Held
Since the I2C controller is part of the FCH, move the early initialization from bootblock.c to early_fch.c which also matches what the newer AMD SoCs do. TEST=Successfully boots on google/liara and all I2C/cr50/TPM functions appear to work properly Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22d3a8888eaa34ea612da719c408c0083769e806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66866 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-20soc/amd/stoneyridge/early_fch: use common lpc_early_init functionFelix Held
The functionality of sb_enable_lpc is implemented in the common LPC support code as lpc_enable_controller. This gets called by the common lpc_early_init which also calls lpc_disable_decodes and lpc_set_spibase. The lpc_set_spibase call was already done in bootblock_fch_early_init, so the main change in code behavior is that now lpc_disable_decodes gets called during early FCH initialization. The lpc_enable_port80 and sb_lpc_decode calls after the lpc_early_init code will reenable some of the decodes. TEST=Successfully boots on google/liara, cbmem and dmesg logs look clean Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia58a6f609fa149a6c09ed99f08bdc4f05eb56f96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66841 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-20soc/amd/common/dmi: Add missing newline in printkMatt DeVillier
Change-Id: I35dd9a2f0520077913bd3d8f408206dea1b30acb Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66867 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-20soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI configKyösti Mälkki
The PCI config space of the SMBus device has a secondary mapping as an ACPIMMIO bank. Since the PCI device is on bus 0, it's already available early in boot after the enable_pci_mmconf call, so there's no need to use the ACPIMMIO mapping instead of the PCI config space mapping. Verstage on PSP could theoretically access the PCI config space via the 0xcf8/0xcfc register pair, but since verstage on PSP doesn't have the ACPIMMIO mapping anyway, we won't loose any functionality here. Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-19mb/starlabs/lite/glkr: Remove old comment from devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib203451bb3da06efd1d3f6e48496b370d81f4b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66196 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/starlabs/lite: Use chipset.cb aliasesSean Rhodes
GLKs chipset configures the devices, so use these aliases and remove the entries when they are identical. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic29e5305346c3b7fbf66b027754a9ddd16b16269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66195 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/google/nissa/var/pujjo: Add DPTF setting for pujjoLeo Chou
DPTF Policy and temperature sensor values from thermal team. BUG=b:242797681 TEST=build FW and boot to OS. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Id4365f87843a4408ae457e7ef27291fdaa0d5bde Reviewed-on: https://review.coreboot.org/c/coreboot/+/66827 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/intel/adlnrvp: Skip sending the MBP HOB to save boot timeV Sowmya
This change is to skip sending the MBP HOB since coreboot doesn't use it and also helps to reduce the boot time by ~40msec on ADL-N. Boot time data: Before: * 955:returning from FspSiliconInit 956,832 (110,268) After: * 955:returning from FspSiliconInit 944,528 (74,213) BUG=b:241850107 TEST=Verified that boot time is reduced by ~40msec and also S0i3 is working. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I05d226fb5f05463341358cd20655f06376778bac Reviewed-on: https://review.coreboot.org/c/coreboot/+/66676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-19mb/google/nissa: Skip sending the MBP HOB to save boot timeV Sowmya
This change is to skip sending the MBP HOB since coreboot doesn't use it and also helps to reduce the boot time by ~40msec on ADL-N variants. Boot time data: Before: * 955:returning from FspSiliconInit 1,231,364 (117,051) After: * 955:returning from FspSiliconInit 1,198,221 (79,497) BUG=b:241850107 TEST=Verified that boot time is reduced by ~40msec and also S0i3 is working. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iaeaa8bcdf8467fdd467a10a98dd7582e8e0b067c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-19soc/intel/alderlake: Add support to skip the MBP HOBV Sowmya
This patch adds the support to enable/disable skipping MBP HOB from the devicetree based on mainboard requirement. Only ADL-N FSP has the required support to skip the MBP HOB and enabling it is saving the Boot time. BUG=b:241850107 TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iddeb2c652fac9513b14139d6f732d333bbb989d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-19mb/google/nissa: Remove runtime descriptor updates and VBT selectionSam McNally
The infrastructure for selecting an appropriate firmware image to use the right descriptor is now ready so runtime descriptor updates are no longer necessary. Since the different descriptor builds split along HDMI/USB-C lines for nereid, a single VBT file can be used for each, removing the need for runtime VBT selection as well. BUG=b:229022567 TEST=Nereid type-C and HDMI outputs work as expected Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: Idf1fbd6c26203adbda002dec3f11e54a7b9f9b82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>