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2022-08-15pciexp_device: Fix pciexp_find_next_extended_cap()Nico Huber
If we already encountered the last extended capability in the list, we'd call pciexp_get_ext_cap_offset() with `offset == 0`. So it also needs to check if the passed offset is valid. As there were no callers of pciexp_find_next_extended_cap() yet, pciexp_get_ext_cap_offset() was only ever called with `PCIE_EXT_CAP_OFFSET`. Change-Id: I155c4691a34ff16661919913a3446fa915ac535e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-15soc/amd/common/fsp/fsp-acpi: rework HOB pointer validity checkFelix Held
Checking if the return value of the fsp_find_extension_hob_by_guid call is NULL should make the code a bit easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6bdb07eab6da80f46c57f5d7b3c894b41ac23b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-15mb/google/guybrush: Pass in Cr50 IRQ to PSPRaul E Rangel
Different guybrush boards have different TPM IRQs. This change passes in the correct GPIO to the TPM. BUG=b:241824257 TEST=Boot guybrush and verify GPIO 3 was passed and that OEM Crypto test passes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I61954fa4493fd56e528b616ca65166a31917f557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-15soc/amd/common/block/psp: Add psp_set_tpm_irq_gpioRaul E Rangel
The PSP currently uses a hard coded GPIO for the TPM IRQ. Not all board versions use the same GPIO. This method allows the mainboard to pass in the correct GPIO. BUG=b:241824257 TEST=Boot guybrush and verify PSP message prints Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie05d095d7f141d6a526d08fbf25eb2652e96aa49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-15soc/amd/*: move reset_i2c_peripherals call after early GPIO setupFelix Held
Since bootblock_soc_early_init gets called before bootblock_mainboard_early_init which does the early GPIO setup, external I2C level shifters that are controlled by GPIOs might not be enabled yet. Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure that the early GPIO setup is already done when reset_i2c_peripherals is called. Haven't probed any SCL signal on the non-SoC side of the I2C level shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a barla/careena Chromebook doesn't have the longer than expected SCL pulses any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-14payloads/edk2: Move the restoration of the logoSean Rhodes
Logo.bmp is overwritten with a custom one from coreboot. This needs to be restored before the branch is updated otherwise git will report that the repository is dirty. Move this to the update recipe so that will always be done for any recipe that needs to update the branch. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I85bf753a47d9e70d6555dec9a539e8ed7395bead Reviewed-on: https://review.coreboot.org/c/coreboot/+/66355 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14soc/intel/common/block/cse: Tidy up table in commentAngel Pons
Adjust an ASCII art table so that it looks good: consistent padding and aligned table borders. Change-Id: I26196f969406e03f320256b0c3a337282f636914 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66707 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-14mb/google/corsola: Distinguish anx7625 and ps8640 for steelixZanxi Chen
Steelix uses ps8640 for board revision < 2, and uses anx7625 for newer revisions. So we use board_id to distinguish anx7625 and ps8640. BUG=b:242018373 TEST=firmware bootsplash is shown on eDP panel of steelix. Change-Id: Ia6907d2e6e290375946afb13176ab9a26dedd671 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org>
2022-08-14mb/google/herobrine: Update modem status with skuid infoSudheer Kumar Amrabadi
BUG=b:232302324 TEST=Validated on qualcomm sc7280 development board Observing 9th bit of skuid with below values, 1 means Modem device 0 means non-modem device Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com> Change-Id: If62b272a43a4588f96e49c8b2b1d75862d401d31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-14soc/qualcomm/sc7280: Add SocInfo support in corebootTaniya Das
Add support for SocInfo in coreboot. The API socinfo_modem_supported is added to help to differentiate between LTE and WiFi SKUs. BUG=b:232302324 TEST=Validate boards are detected correctly on LTE and Wifi SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: I61047ad49772c3796ba403cafde311ad184a4093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-14drivers/nxp/uwb: Add new driver for NXP UWB SR1xx chipJack Rosenthal
Add a new driver for NXP UWB SR1xx (e.g., SR150) device. The driver was originally written by Tim Wawrzynczak as a WIP in CL:3503703, and was based on drivers/spi/acpi. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=On ghost (with follow-up CL), patch linux with NXP's pending drivers -> UWB device is probed and can respond to a simple hello packet Co-authored-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I5b1b0a5c1b48d0b09e7ab5f2ea6b6bc2fba2a7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66466 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14mb/google/brya/var/ghost: Enable cameraJack Rosenthal
Add OV 5675 MIPI camera to ghost, sensor eeprom, and IPU device to device tree. Enable config for MIPI camera. BUG=b:241343306 BRANCH=firmware-brya-14505.B TEST=with ghost overlay changes, camera in camera app works Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie079e43ae0f34efba396331922ea4a89eda72128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-14Revert "soc/amd/sabrina: Re-init eSPI in bootblock"Karthikeyan Ramasubramanian
This reverts commit 8b1c6c6cb384c89659abbd043c2566df358d8f95. With updated APCB, eSPI configuration carries over to bootblock. Hence eSPI does not need to be re-initialized in bootblock. BUG=b:241426419 TEST=Build and boot to OS in Skyrim with PSP verstage. Cq-Depend: chrome-internal:4929421 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I426b07329d4a0154d915381c99dcc9746b7a3d7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-14broadwell: Decouple LPDDR3 DQ/DQS maps from `pei_data`Angel Pons
Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to chipset code without having to use `pei_data`. The only mainboard using LPDDR3 is Google Samus. Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14soc/intel/broadwell: Consolidate SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. As done on Haswell, add the `mb_get_spd_map` function and the `struct spd_info` type to retrieve SPD information from mainboard code without having to use `pei_data` in said mainboard code. Unlike Haswell MRC, Broadwell MRC uses all positions of the `spd_data` array, not just the first. The placeholder SPD address for memory-down seems to be different as well. Adapt the existing code to handle these variations. Once complete, the abstraction layer for both MRC binaries will have the same API. Change-Id: I92a05003a319c354675368cae8e34980bd2f9e10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-14broadwell boards: Do not set `ddr_refresh_2x` againAngel Pons
The `ddr_refresh_2x` setting is already set in chipset code. Change-Id: I76478689b3aa27c369a0413d9fbde03674d5e528 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55810 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14broadwell: Move some MRC/refcode settings to devicetreeAngel Pons
There's no generic way to tell whether a mainboard has an EC or not. Making Kconfig symbols for these options seems overkill, too. So, just put them on the devicetree. Also, drop unnecessary assignments when the board's current value is zero, as the struct defaults to zero already. Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-14mb/google/auron: Move SPD file handling to chipsetAngel Pons
The SPD file handling code is generic and can be used on any other mainboard. Move it to chipset scope to enable code reuse. Change-Id: I85b1460ccb82f0c1bf409db4a6b4c9355c25e76d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55808 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-14broadwell: Compute channel disable masks at runtimeAngel Pons
Introduce the `SPD_MEMORY_DOWN` macro to indicate that a slot is used with memory-down. This enables computing the channel disable masks as the bits for slots where the SPD address is zero. To preserve current behavior, zero the SPD addresses for memory-down slots afterwards. Change-Id: I75b7be7c72062d1a26cfc7b09b79de62de0a9cea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55807 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13util/release: Update genrelnotes with the latest versionMartin Roth
This is the version of genrelnotes that was used to help with the 4.16 release. - Fix shellcheck issues. - Send messages for the user to STDERR. - Add recent platforms - Handle symbolic links to the git repo. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2204793a5d1cc5792d0720d2bbfb172bb6020dd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-08-13vc/amd/fsp/cezanne,mendocino: add FSP CCX CPPC HOB GUID and structFelix Held
To generate a complete _CPC ACPI object, coreboot needs the minimal and nominal core speed values which are specific to the CPU and not only the CPU family. Since this is done by an undocumented mechanism, FSP has to do this and puts the information we need into a HOB. This adds the HOB GUID and the structure of the HOB data. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/amd/mendocino/chipset_rembrandt: use right chipset folderFelix Held
Since the path after the chip keyword needs to point to the directory that contains the chipset's chip.h file, change this from soc/amd/rembrandt to soc/amd/mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63334fbd59e74df491035b5cf7e296818cc02665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66688 Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-13src/mb: Update unlicensable files with the CC-PDDC SPDX IDMartin Roth
These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13arm/libgcc: Support signed 64-bit divisionRob Barnes
Add support for signed 64-bit division. The implementation mostly relies on __aeabi_uldivmod, which is already implemented. ldivmod.S was adapted from CrOS EC version of ldivmod.S: https://chromium.googlesource.com/chromiumos/platform/ec/+/main/third_party/libaeabi-cortexm0/core/cortex-m0/ldivmod.S The CrOS EC version was adapted from: https://github.com/bobbl/libaeabi-cortexm0/blob/master/ldivmod.S BUG=b:240316722 BRANCH=None TEST=Signed division works in PSP verstage (runs on ARM) Change-Id: I53785c732b0fa35a4809bc054f1482c5461ada7b Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-08-13timer: Switch mono_time to uint64_tRob Barnes
A 32-bit long storing microseconds will rollover every ~1.19 hours. This can cause stopwatch to misbehave, causing unexpected failures. If the current field in stopwatch is near 2^31, the expires field may rollover when initialized. If this occurs, stopwatch_expired() will instantly return true. If current and expires fields are near 2^31, the current field could rollover before being checked. In this case, stopwatch_expired() will not return true for over an hour. Also stopwatch_duration_usecs() will return a large negative duration. This issue has only been observed in SMM since it never takes more than 35 minutes to boot. Switching to uint64_t mitigates this issue since it will not rollover for over 500K+ years. The raw TSC would rollover sooner than this, ~200 years, depending on the tick frequency. BUG=b:237082996 BRANCH=All TEST=Boot Nipperkin Change-Id: I4c24894718f093ac7cd1e434410bc64e6436869a Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65403 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-13payloads/edk2: Move printing the build options to a separate recipeSean Rhodes
Move the code that prints the edk2 build options to it's own recipe so that it can be called for different targets. This change also fixes the print, as it accounts for recent switches such as `--pcd` and `-s`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie797ca26cd28eab0f633bd8dee5ec19634fcea99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-08-13soc/mediatek/mt8188: Initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6d19dc6f4e47ed69ba2ea87c79984020a413aee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66586 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek: Move common definition of DFD to common folderRex-BC Chen
We use the same dump address and size for DFD in all MediaTek SoCs, so we move them to dfd_common.h and rename dfd_common.h to dfd.h. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I162bbb0a82e3b55c8cfbbd20e28a54ad01fd6b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66585 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek/mt8188: Fix the order of register address in addressmap.hRex-BC Chen
TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ie9d7b361dda8c5850bc0682c255bc20f9e26675c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66668 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek/mt8188: Add tracker dumpRex-BC Chen
Tracker is a debugging tool. When bus timeout occurs, the system will reboot and latch some values of tracker registers which could be used for debugging. This function will be triggered only when it encounters the bus hanging issue. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I78f676c08ea44e9bb10bd99bbfed70e3e8ece993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66584 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-13soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITMacpaul Lin
This replaces 'SPDX-License-Identifier' tags in all the files under soc/mediatek/mt8188 for better code re-use in other open source software stack. These files were originally from MediaTek and follow coreboot's main license: "GPL-2.0-only". Now MediaTek replaces these files to "GPL-2.0-only OR MIT" license. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Change-Id: If61e8b252400e8e5ecd185b6806b1ca279065f15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66628 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-13mb/google/brya: Use default EPP of 50% for skolasJeremy Compostella
A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. Similar results are observed on Raptor Lake. BRANCH=firmware-brya-14505.B BUG=b:240669428 TEST=verify that EPP is back to the by default 50% setting `iotools rdmsr 0 0x774' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I735ad9d88c7bf54def7a23b75abc4e89a213fb61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13Revert "mb/google/brya: Set EPP to 45% for all Brya variants"Jeremy Compostella
This reverts commit 938f33e9f7756d730a1da278679087476a476bf2. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BRANCH=firmware-brya-14505.B BUG=b:240669428 TEST=verify that EPP is back to the by default 50% setting `iotools rdmsr 0 0x774' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Icacc555e62533ced30db83e0a036db1c85c0bfa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"Jeremy Compostella
This reverts commit 844dcb3725fc95df53a7229703f5059d2c36f98e. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BRANCH=firmware-brya-14505.B BUG=b:240669428 TEST=verify that ETT is disabled `iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I96a72009aaf96d4237d57f4d5c8b1f41f87174d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66281 Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13mb/google/brya/var/taniks: Disable PCH USB2 phy power gating for taniksJoey Peng
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for taniks board. Please refer Intel doc#723158 for more information. BUG=b:241965786 TEST=Verify on taniks boards. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib95430c7ba9d84f8bafcb1febcff9b4e4038cadc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13mb/google/brask/variants/moli: modify psys_pl2 for 15W and 28W SOCRaihow Shi
Moli has 90W adapter for 15W SOC and 135W adapter for 28W SOC, so modify the Psys_PL2 for both 15W and 28W SOC. -set 90W Psys_PL2 for 15W SOC -set 135W Psys_PL2 for 28W SOC BUG=b:242119726 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: If8f9006d797d74f6d5d802d445edc425a4700420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13tests/lib: Do not pick up unassigned resourcesShuo Liu
Unassigned tag is defined to emulate an unmapped PCI BAR resource. This resource is not mapped into host physical address and hence should not be picked up by memranges_add_resources(). Change-Id: If7a5c437d486b80d798496b985efd80526f13c63 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com>
2022-08-13device: Skip not assigned resources during global resource searchShuo Liu
It's possible that some BARs are not got their resource successfully mapped, e.g. when these BARs are too large to fit into the available MMIO window. Not assigned resources might be with base address as 0x0. During global resource search, these not assigned resources should not be picked up. One example is MTRR calculation. MTRR calculation is based on global memory ranges. An unmapped BAR whose base is left as 0x0 will be mistakenly picked up and recognized as an UC range starting from 0x0. Change-Id: I9c3ea302058914f38a13a7739fc28d7f94527704 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66347 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-08-13tests/lib: Set IORESOURCE_ASSIGNED for bootmem-test and memrange-testShuo Liu
IORESOURCE_ASSIGNED is used to indicate the resource is actually mapped host physical address space. E.g. PCI BAR resources not mapped are not regarded as assigned. In src/include/device/device.h, standard macros, e.g. ram_resource, mmio_resource, io_resource, et al, are all following the usage above. This patch updates the bootmem-test and memrange-test to follow the usage as well. Change-Id: Ifc19302482038267cef01321a46a72d90ca76d35 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66450 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13mb/starlabs/starbook/tgl: Enable TPM Measured BootSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I251840b409dead62586cefe5856b6c544401ba30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-13mb/starlabs/starbook/kbl: Enable CRB_TPMSean Rhodes
Enable CRB_TPM to allow the use of the fTPM (Intel PTT). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b69854ea636947480402ce12450f431028660a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-08-13payloads/tianocore: Rename TianoCore to edk2Sean Rhodes
coreboot uses TianoCore interchangeably with EDK II, and whilst the meaning is generally clear, it's not the payload it uses. EDK II is commonly written as edk2. coreboot builds edk2 directly from the edk2 repository. Whilst it can build some components from edk2-platforms, the target is still edk2. [1] tianocore.org - "Welcome to TianoCore, the community supporting" [2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and UEFI Platform Initialization (PI) specifications." Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-12soc/amd/cezanne,common: factor out CPPC code to common AMD SoC codeFelix Held
The Cezanne CPPC ACPI table generation code also applies to Sabrina, so move it to the common AMD SoC code directory so that it can be used for Sabrina too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ce082a27429948f8af7f55944a1062ba03155da Reviewed-on: https://review.coreboot.org/c/coreboot/+/66400 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-12soc/amd/mendocino: clear Port80 enable bit in ESPI DecodeJon Murphy
This reverts commit Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae. There was a bug that caused the SMU to hang when writing port80. it has since been resolved, so revert this workaround. BUG=b:227201571 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5f10e282ab03756c7dbfb48182940f979eb122e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66470 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-12soc/(amd|rockchip): Update vb2ex_hwcrypto implementations to new API reqJulius Werner
We want to extend the vb2ex_hwcrypto APIs on the vboot side to allow passing 0 for the data_size parameter to vb2ex_hwcrypto_digest_init() (see CL:3825558). This is because not all use cases allow knowing the amount of data to be hashed beforehand (most notable the metadata hash for CBFS verification), and some HW crypto engines do not need this information, so we don't want to preclude them from optimizing these use cases just because others do. The new API requirement is that data_size may be 0, which indicates that the amount of data to be hashed is unknown. If a HW crypto engine cannot support this case, it should return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED to those calls (this patch adds the code to do that to existing HW crypto implementations). If the passed-in data_size value is non-zero, the HW crypto implementation can trust that it is accurate. Also reduce a bit of the console spew for existing HW crypto implementations, since vboot already logs the same information anyway. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ieb7597080254b31ef2bdbc0defc91b119c618380 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-12libpayload: usb: Fix spacing issuesYidi Lin
Found by: find payloads/libpayload/drivers/usb -type f -name "*.[ch]" | xargs \ util/lint/checkpatch.pl --types SPACING -q --fix-inplace -f Change-Id: Id23e2e573e475c6d795812a4b2df9aeffbcaaaf4 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66596 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12mb/google/brya/var/taeko: Disable PCH USB2 phy power gating for taekoJoey Peng
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for taeko board. Please refer Intel doc#723158 for more information. BUG=b:241965786 TEST=Verify on taeko/tarlo boards. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I03042906d5bea9b9010016adb98fbe68e2dc92f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-12libpayload: usbmsc: Prevent usbdisk_remove() from being called twiceYidi Lin
When removing SD card from USB card reader, the USB MSC stack does not detach the device immediately. Instead, the USB MSC stack calls usbdisk_remove() and calls usb_msc_destroy() after several pollings. It results in usbdisk_remove() being called twice. Since the usbmsc_inst_t instance is freed after first usbdisk_remove() call, the second call invokes an invalid usbmsc_inst_t instance and causes exception in CPU. This patch prevents usbdisk_remove() from being called twice by setting usbdisk_created to zero. BUG=b:239492347 TEST=insert an empty SD card into the USB card reader then remove the SD card. AP firmware does not crash. Change-Id: I0675e9fde3e770d63dd0047928356a204245ef18 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66449 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12soc/mediatek/mt8186: Enable USB macro controlAllen-KH Cheng
When powering down SSUSB, the system needs to wait the ACK from SSUSB. We found that the setting of USB PAD top macro is not correct and it will cause timeout waiting for the ACK from SSUSB. To resolve this, we add mt_pll_set_usb_clock() in pll.c to enable usb macro control for powering down SSUSB. TEST=timeout of ssusb powerdown ack does not occur. BUG=b:239634625 Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> Change-Id: I58ba86e0467284e9947bfda1005c151a3e0c8881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66600 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-12mb/google/brya/var/mithrax: Add new memory H9HCNNNCPMMLXR-NEEJohn Su
Add new ram_id:0001 for memory part H9HCNNNCPMMLXR-NEE. BUG=b:241494931 TEST=none Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iee9f881d8ab21396d208a6af9f0cec8414cb50a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-08-12Fix Alder Lake and Raptor Lake Device ID'sMaximilian Brune
- ADP_P_* -> RPP_S_* (got mixed up I guess) - Remove duplicates of ADP_S_ESPI_* - Add infix _ESPI_ to all ADP_S device ID's Document: 619362 Change-Id: Ic18ecbd420fc598f0ef6e3cf38e987ac3ae6067e Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66629 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12Add missing ADL-S device identificationMaximilian Brune
R680E, Q670E, H610E are the ADL-S IoT variants TEST=Boot ADL-S RVP DDR5 and see silicon info is reported as PCH: AlderLake-S R680E Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1804994b4b72f0484eabb15323736679d2668078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-12soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12soc/intel/common: Delete the TBT authenticaton functionJohn Zhao
Delete the Thunderbolt authentication function ioe_tcss_valid_tbt_auth from the common block. Meteor Lake Platform will implement it. BUG=b:213574324 TEST=Built coreboot image successfully. Change-Id: I97a289faa6351fe562f91d8478b72c9403ce88cb Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12soc/intel/alderlake: Fix DDR5 channel mappingAngel Pons
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC memory modules), and the SPD info refers to one channel: the primary bus width is 32 (or 40) bits and the "DIMM size" is halved. On Alder Lake, there are 2 memory controllers with 4 32-bit channels each for DDR5. FSP has 16 positions to store SPD data, some of which are only used with LPDDR4/LPDDR5. To try to make things less confusing, FSP abstracts the DDR5 channels so that the configuration works like on DDR4. This is done by copying each DIMM's SPD data to the other half-channel. Thus, fix the wrapper parameters for DDR5 accordingly. Tested on AlderLake-P DDR5 RVP (board ID 0x12), both DIMM slots now function properly. Without this patch, only the top slot would work. Change-Id: I5f01cd77388b89ba34d91c2dc5fb843fe9db9826 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66608 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-12mb/system76/gaze16: Rename variant dirTim Crawford
Use the actual model name for the variant dir. Change-Id: I199b8efb5c3cddb8943ba4b761546caa11c67a30 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-08-12mb/google/nissa/var/craask: Enable DDR RFIM Policy for CraaskTyler Wang
Enable RFIM Policy, request by RF team. BUG=b:239657092 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Id0f425d75a1ac9486a9284d4e8320ba4c63b182f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-08-12amdfwtool/amdfwtool.h: Allow 16 additional PSP entries to be supportedAltamshali Hirani
Consolidate MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com> Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62911 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12Doc/psp_integration.md: Update infomation with latest documentZheng Bao
Update coreboot.org PSP Firmware Documentation with current internal PSP documentation. Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-12util/spd_tools: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used. Update amdfwtool for consistency with the correct naming convention. BUG=b:239072117 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I404fcf59e89b75cd2488bcb51981aee2eb4ff0df Reviewed-on: https://review.coreboot.org/c/coreboot/+/66468 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12mb/google/rex: Add ACPI support for Type-C portsSubrata Banik
This patch backported from commit ba2e51bd496a (mb/google/brya: brya0: Add ACPI support for Type-C ports) for google/rex. BUG=b:224325352 TEST=Able to build Google/Rex and boot on MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If0a9510784e8f62861ae4bc74805b1513a4865cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/66538 Reviewed-by: Prashant Malani <pmalani@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-12mb/google/rex: Describe USB2/3 ports in devicetreeSubrata Banik
This patch describes the USB2/3 ports in devicetree to generate ACPI code at runtime. The ACPI code includes the port definition, location, type information. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7d787a9986099852d6a0d193bbc28487bf430fe4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66542 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12mb/google/rex: Update mainboard properties for BB retimerSubrata Banik
This patch backport commit 9e23d017f555bad (mb/google/brya: Update mainboard properties for BB retimer upgrade) for Google/Rex. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I508858683cf3cdb0cab5a564fef4a242f8a6679e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66541 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12mb/google/rex: Describe TCSS USB ports in devicetreeSubrata Banik
This patch describes the TCSS USB ports in devicetree to generate ACPI code at runtime. The ACPI code includes the port definition, location, type information. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I08613b31aad47cbf573ed1b5fc68c91cf973e190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66540 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-12mb/google/rex: Add OC pin programming for USB2 Port 8Subrata Banik
This patch adds OC pin programming for USB2 Port 8. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic9dcaef5972d6c0e9fe264445ea10fcd9a82619f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66543 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-12soc/intel/meteorlake: Have non prefetchable MMIO for IGD BAR0Wonkyu Kim
Enable SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO for MTL to fix guc driver failure. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc20935bccdda55db3e57eecd37a4260b3f1a2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66613 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12soc/intel/common: Ignore prefetch PCI attribute for IGD BAR0Wonkyu Kim
From Meteorlake, IGD BAR0(GTTMMADR) is changed to 64bit prefetchable. Due to the prefetchable attribute, resource allocation for IGD BAR0 is assigned WC memory and it causes kernel driver failure. For avoiding kernel driver failure, ignore prefetch PCI attribute for IGD BAR0 to assign UC memory. We're working on publishing below information. - IGD BAR0(GTTMMADR) is changed to 64bit prefetchable BAR - GTTMMADDR BAR should be always mapped as UC memory although marked Pre-fetchable. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I76d816d51f32f99c5ebcca54f13ec6d4ba77bba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66403 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-11util/amdfwtool: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used. Update amdfwtool for consistency with the correct naming convention. BUG=b:239072117 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I673a9b99d207603b605756fc7d277c54c5d0f311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66467 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-11treewide: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-11util/lint: Add .gitignore files to list that don't need a licenseMartin Roth
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I568a357b40e8bb69b2b26752d241f06adfbe029e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11lib: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the lib directory that don't already have them. A note on gcov-iov.h - As machine generated content, this file is believed to be uncopyrightable, and therefore in the public domain, so gets the CC-PDDC license even though there is code in the file. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ifcb584d78a55e56c1b5c02d424a7e950a7f115dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11include: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the include directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0dbf4c839eacf957eb6f272aa8bfa1eeedc0886f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66501 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11southbridge: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the southbridge directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: If74aa82a7c40293198e07e81ceac52bd8ca8ad27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66500 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11drivers: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the drivers directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I97f96de857515214069c3b77f3c781f7f0555c6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66499 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11src/mb: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the mainboard directory that don't already have them. Change-Id: I1adc204624f3ab6fcafd8fbb239e6d69e057973a Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66498 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11src/soc/intel/mtl: Add VPU supportSrinidhi N Kaushik
This change adds support for enabling VPU on MTL SoC. BUG=b:240665069 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie79b45f34a669b9ff777599cb85217abac6cb74e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-08-10mb/google/nissa/var/joxer: Add WiFi SAR tableMark Hsieh
Add WiFi SAR table for joxer. BUG=b:239788985 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ia8dddf454e441840233fa4405704ee1f0a8ed86c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66522 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10docs/utils/ifdtool: Fix waning of malformed tableLance Zhao
Signed-off-by: Lance Zhao <lance.zhao@gmail.com> Change-Id: Idc90c6e8186320979a72563fb5dcdc8fce760e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66562 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10soc/intel/tigerlake: Add USBOTG and CrashLog to irq tableFrans Hendriks
FSP reports missing IRQ for devices. Add USBOTG (D20:F1) and CrashLog & Telemetry (D10:F0) to irq_constrain. Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ic02d33045a07a6888ba97d8f2c6fa71bc7e363e8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-10util/lint & LICENSES: Add PDDC as a "license" for corebootMartin Roth
The Creative Commons Public Domain Dedication and Certification is not a license in the common sense in that it's stating that the associated file is already in the public domain (having no copyright), and is not actually putting it in the public domain like the CC-C0 license does. The use for this in coreboot is for unlicensable files - either blank files or files with no creative content. This allows these files to have the SPDX identifier to identify them as having no known copyright for open source license compliance. If CC-PDM-1.0 is ever included in the list of SPDX licenses, that would probably fit better, but because the public domain mark isn't actually a license, and because "public domain" isn't well defined, CC-PDM was rejected as a SPDX identifier. For further information: https://web.archive.org/web/20201018194411/https://github.com/spdx/license-list-XML/issues/988 Change-Id: Ibb300ecd066cde2a016195c2beca76a460c588e3 Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66496 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10util/lint & LICENSES: Add GCC-exception-3.1 to license exceptionsMartin Roth
The gcov files in the lib directory are licensed GPL 3.0 with the GCC runtime library exception. Add this as a valid license so that the files can get a correct SPDX identifier. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I1cf9c3125592741923c9b4481038055f24fe6ab1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10LICENSES: Add missing licenses and exceptionsMartin Roth
These licenses and exceptions are allowed by coreboot's license checker, but the copies of the licenses were missing from the LICENSES directory. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ic4233e556de08275fe50f1ec83828f9470b4b566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66494 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10mb/google/zork: Set vw_irq_polarity from low to highRaul E Rangel
The EC used on zork uses a level high interrupt. This change configures the polarity correctly. The eSPI config is baked into RO verstage. The zork ToT build doesn't use signed verstage since it's incompatible with the ToT version of vboot. This means we can safely switch the keyboard IRQ polarity. NOTE: Do not cherry pick this into the Zork firmware branch! BUG=b:160595155 TEST=On morphius verify keyboard works as correctly and no spurious interrupts are thrown on S0i3 resume. Also verified keyboard and mouse work correctly in windows. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-10mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarityRaul E Rangel
The default state for the IRQ lines when the eSPI controller comes out of reset is high. This is because the IRQ lines are shared with the other IRQ sources using AND gates. This means that in order to not cause any spurious interrupts or miss any interrupts, the IO-APIC must use a low polarity trigger. On zork/guybrush/skyrim the eSPI IRQs are currently working as follows: * On power on/resume the eSPI controller drives IRQ 1 high. * eSPI controller gets configured to not invert IRQ 1. * OS configures IO-APIC IRQ 1 as Edge/High. * EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1 high. * eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ 1 as high. This results in missing the first interrupt. * When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the eSPI controller to set IRQ1 to low. We are now primed to catch the next edge high interrupt. This is generally not a problem since the linux driver will probe the 8042 with interrupts off. On S3/S0i3 resume since the eSPI controller comes out of reset driving the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is configured to trigger on edge high. This results in the 8042 controller getting incorrectly marked as a wake trigger. By configuring the IO-APIC to use low polarity interrupts, we no longer lose the first interrupt. This also means we can use a level interrupt to match what the EC actually asserts. We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI because the linux kernel will ignore the level/polarity parameters for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't have this problem. The PIC is not currently configured anywhere and it defaults to an edge/high trigger. We could add some code to configure the PICs trigger register, but I don't think we need the functionality right now. For zork and guybrush, this change is a no-op. eSPI is configured in verstage which is located in RO, and we have already locked RO for these devices. We will need to figure out how to properly set the `vw_irq_polarity` for these devices. BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104 TEST=On zork, guybrush and skyrim $ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count' Verify keyboard works as expected and no interrupt storms are observed. On morphius I verified keyboard and mouse work on windows as well. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-09MAINTAINERS: Add lists for soc/intel/meteorlake and mb/google/rexKapil Porwal
Change-Id: Ia5def4cf86b47ac96ba5fc6ec86a139d5ad2765e Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-09mb/google/nissa/var/pujjo: Enable USB3.0 port 3 for WWANStanley Wu
Pujjo support WWAN device, enable USB3.0 port 3 for WWAN device BUG=b:241322361 TEST=Build and boot on pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Iafe2ea18663794138e0a27879fc108d23eb81456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-09utils: Add initial version of "remove_unused_code" scriptMartin Roth
This script creates a patch to remove all of the coreboot code that a platform doesn't use. This is useful for auditing the codebase for an individual platform or releasing a platform's code. Unlike the script that Sage used that did something similar, this keeps the entire Kconfig tree (Though in a single file), all makefiles that are required to build, and the standard build tools can still be used. This will allow for much easier re-integration back into the coreboot codebase if code is released after running this. This is just the initial version and more features needed to be added to make it fully functional. - It should be able to build multiple configurations to retain the code for all of those configurations. - Flag to remove submodules files as well - Additional variable flags to replace hardcoded values. - The list of makefiles that need to be kept is pretty long, and could be updated so that they aren't needed by the top level makefiles. - Add flag to show changed files - Show number of files before and after script is run Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-09mb/google/brya/var/ghost: update arbitrage gpio.c headerKevin Chowski
This update follows suggestions from Martin Roth about the contents of the comment. Change-Id: Ic296bcd6a0fb250426f5d75aac69a3fa0f2aaf32 Signed-off-by: Kevin Chowski <chowski@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-09util/amdfwtool: Fix ISH_B directory offsetKarthikeyan Ramasubramanian
On boards which use both PSP recovery A/B layout as well as VBOOT A/B layout, ISH_B directory entry is pointing directly to PSP Level2 directory. This is not correct and either ISH_B should be marked as not present or it should point to the ISH_A directory itself which in turn point to PSP L2 directory. Fix it by choosing the latter option. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-08mb/google/brya: Select SOC_INTEL_COMMON_UFS_SUPPORT for NissaMeera Ravindranath
BUG=b:238262674 TEST=Build and check ufs.c file gets compiled for Nissa boards Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Idc5ad922b97bd1e65e5023f9126c43e42cfc38a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66064 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-08soc/amd/sabrina: Rename PSP SPL defaultMarshall Dawson
Change the SPL file from the 'cezanne' placeholder to a mendocino filename. Also, move the default location to blobs/mainboard since it's not board-agnostic. BUG=b:241543152 BUILD=Enable feature and build amd/chausie Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I47647c5d926484e25e3f893e72c671554e277a56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-08soc/amd/sabrina: Rename PSP whitelist defaultMarshall Dawson
Change the name of the whitelist file from the 'cezanne' placeholder to a mendocino path/to/file. Also, as whitelist files won't be pushed into a public repo, modify the path to point to site-local. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I49bbf1335606567735e36ed9bda1314bfc6247d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07soc/amd/sabrina: Use new mendocino amd_blobsMarshall Dawson
Modify sabrina's fw.cfg to point to the proper directory and use the standard names, as released by AMD. The name 'sabrina' was an alias used for the Mendocino product. The public-facing builds have been using Cezanne blobs, renamed as Sabrina or SBR, but can now take advantage of the appropriate blobs. BUG=b:239072117 TEST=Build amd/chausie Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id646844e41980802be1e39dce96e5adaace4311d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-073rdparty/amd_blobs: Advance submodule pointerMarshall Dawson
This picks up the following changes 83c44ad mendocino: Add additional SPI configs 5141d91 mendocino: Add all blobs from PI 1.0.0.1 3b29a7d cezanne: Upgrade microcode patch to 00A50F00h BUG=239072117 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I1060dc7bec8f436dccf270bc3abde75cb09bb591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07mb/google/skyrim: Resolve boot behaviorJon Murphy
Move GPIO init for SSD_AUX_RESET_L to ensure that eMMC devices will be initialized in time for the nominal boot flow. BUG=b:237701972 TEST=Boots to OS BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I610966fd9d31581f15d8bcd51f8a116c27fd6311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66461 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07mb/google/brya/var/ghost: Pull EN_PP3300_TCHSCR highJack Rosenthal
This gets the display working. BUG=b:240884260 BRANCH=firmware-brya-14505.B TEST=display works in both depthcharge and linux Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I03edac865d68ef48e86d47a04f27ed84894f2f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66395 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-07superio/ite/common/early_serial.c: ite_kill_watchdog: set timeout to 0Michał Kopeć
Set the watchdog timeout to 0 in ite_kill_watchdog, as in some ITE models it is set to non-zero by default, activating the watchdog despite us setting the control register to 0. Based on: - "ITE IT8786E-I Preliminary Specification V0.4.1 (For D Version)" - Linux it87_wdt driver Change-Id: I1e78e2acc96e9dd0f283c5c674d3277d26cdee26 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07mb/amd/chausie: Add Kconfig prompts to EC stringsMarshall Dawson
Make the default Microchip EC firmware path/to/file values overridable by adding prompts to the strings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I300f78a11960dbe193165fcb379b7190e3de4545 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07pciexp_device: Handle unsupported requests in pciexp_get_ext_cap_offset()Bill XIE
Looking into pciexp_get_ext_cap_offset() it seems a little hackish and prone to endless loops. Either it should limit the loop or bail out when pci_read_config32() returns 0xffffffff, meaning "Unsupported Requests". This commit fixes an endless loop when the queried PCIe device is downstream of a legacy PCI bus which doesn't support extended config space, thus pci_read_config32() will return 0xffffffff, for example, the combination below with CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS enabled. TEST=Build and boot to OS in ASUS P8C WS with the following peripherals and CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS enabled: 00:1c.4 PCI bridge [0604]: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 5 [8086:1e18] (rev c4) 00:1c.4/00.0 SATA controller [0106]: Marvell Technology Group Ltd. 88SE9170 PCIe 2.0 x1 2-port SATA 6 Gb/s Controller [1b4b:9170] (rev 13) 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev a4) 00:1e.0/00.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8111 PCI Express-to-PCI Bridge [10b5:8111] (rev 21) 00:1e.0/03.0 FireWire (IEEE 1394) [0c00]: VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller [1106:3044] (rev c0) 00:1e.0/00.0/00.0 Network controller [0280]: Qualcomm Atheros AR93xx Wireless Network Adapter [168c:0030] (rev 01) with 00:1c.4/00.0 being successfully tuned with pciexp_tune_dev(), and 00: 1e.0/00.0/00.0 not tuned as expected. Change-Id: Ibb92548c47288b40e851fcc0a8a37937e8bdbf3c Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66439 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-07payloads/tianocore: Remove the option for CorebootPayloadPkgSean Rhodes
Recent changes to both coreboot and edk2 means that UefiPayloadPkg seems to work on all hardware. It has been tested on: * Intel Core 2nd, 3rd, 4th, 5th, 6th, 8th, 8th, 9th, 10th, 11th and 12th generation processors * Intel Small Core BYT, BSW, APL, GLK and GLK-R processors * AMD Stoney Ridge and Picasso This includes the problematic Lenovo X230s. The most likely fixes are: * Configuring the PCI Base and Length in edk2 * Fixes to the HostBridgeLib in edk2 * Adjustment to the SD/eMMC initialisation timeout This means we can now remove the already deprecated option for CorebootPayloadPkg and the legacy 8254 timer build option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ice7b7576eb3d32ea46e5138266b7df3fbcdcf7ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>