summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2024-09-13configs: Disable graphics on intel/archercity CRBShuo Liu
Change-Id: Ic78190a6bff233388bf52fdbb94fa3d7812010f2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-09-13soc/intel/xeon_sp/gnr: Move CPU ID definition to common headerJincheng Li
Change-Id: I816c6f68840c122fbc37085e31a1b0368a819f4a Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84313 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Enlarge MAX_CPUS to 512Jincheng Li
GNR-AP supports up-to 128 cores/256 threads per socket. Enlarge MAX_CPUS to 512 = 128*2*2 with 2 socket configuration considered. Change-Id: I8dc46dcdd3ca1c3ddfa47fbb28912a2c6e4c46fa Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84312 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13vc/intel/fsp/fsp2_0/graniterapids: Update FSP headersJincheng Li
FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to pass compilation with full platform codes. Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-13soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZEGang Chen
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR, this default size is enough. Use the default size so that more CAR spaces could be saved for other purpose. Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/ptl: Do initial Panther Lake SoC commit till ramstageSaurabh Mishra
List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I61930726ad0c765bfa1d72c5df893262be884834 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-13soc/intel/cmn/block/cpu: Simplify calculation of non-eviction waysSubrata Banik
The calculation of non-eviction ways (used for cache-as-ram configuration) has been simplified by removing conditional move instructions and directly adding the remainder to the quotient. This achieves the same ceiling operation but with potentially improved efficiency (less instructions). No functional changes are expected. TEST=Able to build and boot google/rex. Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-09-12mb/google/brox: Set PCIE WLAN bluetooth companion deviceKarthikeyan Ramasubramanian
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:362672785 TEST=Build Brox firmware and boot to OS. Ensure that the BRDS table is populated under the right ACPI device scope. Scope (\_SB.PCI0.XHCI.RHUB.HS10) { Name (BRDS, Package (0x02) { 0x00000001, Package (0x0A) { 0x00000012, 0x00000001, 0x00000001, 0x7C, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70 } }) } Change-Id: I9a74a995bca8d412b85c243c7f2f98c9917b5e76 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84296 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com>
2024-09-12mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPUKarthikeyan Ramasubramanian
Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:363854853 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I386f8e88a5af661b1f4c04d2e2a34cd181608bd8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: <srinivas.kulkarni@intel.com>
2024-09-12amdfwtool: Set the fields when the header is createdZheng Bao
The fields spi_block_size and base_addr of regular PSP header, lookup and reserved of combo header, are constants. So we move the setting statements to the creation functions. Only update the count, size and fletcher in later function file_dir_header. TEST=Binary identical test on all AMD SOC platforms Change-Id: I55c400e45536a57841b01d7c90d3fef9afa53e78 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-12soc/mediatek: Remove redundant struct pad_func and PAD_* definitionsYidi Lin
Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch also refactors the PAD_* macros by, - Repurposing PAD_FUNC and dropping PAD_FUNC_SEL. - Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit initialization. BUG=none TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84222 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-12payloads/edk2/Makefile: detect invalid commit hash on checkoutSergii Dmytruk
There is already a check for invalid reference, however `git rev-parse reference` doesn't fail on unknown commit hash unless `^{object}` peeling operator is used (`^{commit}` can be used as well). Change-Id: I7ef39aeee2e902ac2fad6ac41b546c47418e1dec Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-12payloads/edk2: Update default branch for MrChromebox repo to 2024-08Matt DeVillier
Update the default branch used for MrChromebox's edk2 fork from 2023-09 to 2024-08. This updated branch has been rebased on the latest upstream stable tag (edk2-stable202408), and updates the EFI filesystem drivers which had been causing some issues with bootable USBs created using Rufus as it tried to unload the filesystem drivers and load its own. TEST=build/boot google boards link, panther, lulu, reef, ampton, akemi, banshee, zork, dewatt, frostflow with edk2 payload selected. Change-Id: I459b668345ed2a34e198e6a3d3a2da94b2940e69 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84293 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-12amdfwtool: Add a unified function to add combo entriesZheng Bao
TEST=Binary identical test on all AMD SOC platform with use_combo Change-Id: I41c5c6fb5acf92604dd06becf1eda680a1fab545 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84131 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-12amdfwtool: Add combo new layout for new familyZheng Bao
The new layout definition has a new way to support combo. It packs multiple ISH entries into PSP L1 directory. TEST=Identical test on all AMD platform Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-12mb/google/brox/variants/brox: remove PL4 value modificationSumeet Pawnikar
Remove PL4 value modification based on PsysPL3 value. BUG=None BRANCH=None TEST=Built and boot on brox system Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Ic7fbc6386769aa9f76a8665a742c97dfd790fd1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83662 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-11soc/intel/raptorlake: Fall back to Intel microcode repoFelix Singer
With the release 20240910 of the Intel microcode repository, it also includes the updated microcode file with version 0x129, which makes the one from the coreboot blobs repo superfluous. Thus, use the one from the Intel repository again. Change-Id: I7fb58874719a8373072419e34b3f8923f7db927d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84295 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-113rdparty/intel-microcode: Update submodule to upstream mainFelix Singer
Updating from commit id 2f56505: 2024-08-14 19:59:27 -0600 - (microcode-20240813 Release) to commit id fbfe741: 2024-09-10 12:02:03 -0600 - (microcode-20240910 Release) This brings in 1 new commits: fbfe741 microcode-20240910 Release Change-Id: If66975c71ade0f08b81fb90d0a91e61ca3405804 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84294 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11mb/google/brox/var/lotso: Update verb tableJian Tong
Correct the number of NID entries. BUG=b:349996984 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I5f5553a5d8014f957d6b89ac4c1039594817bf32 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84184 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-11mb/google/brox/var/jubilant: Enable ASPM for PCIe4 SSD of CPURen Kuo
Enable ASPM of CPU PCIe4 for SSD to improve power consumption. BUG=b:364441213 BRANCH=None TEST="sh -c 'lspci -vvnn || lspci -nn'" 01:00.0 Non-Volatile memory controller LnkCtl: ASPM L1 Enabled Change-Id: I4380bb8748f2847b1824e20edb19578c7aedfe4f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-11soc/intel/cml, pci_ids: Remove IDs of non-existent graphics devicesMaxim Polyakov
These identifiers are not included in the GPU list from Intel [1]. At the same time, 0x9B44 is not PCI DID of graphics device at all: 8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2]. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html [2] https://web.archive.org/web/20231004011832/https://devicehunt.com/ view/type/pci/vendor/8086/device/9B44 Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11soc/intel/cml, pci_ids: Fix IDs for Intel Comet Lake-S/H GT1Maxim Polyakov
According to the Intel GPU list [1], these devices have the following IDs: 8086:9BA8 - Comet Lake-S GT1 [UHD Graphics 610] [2] 8086:9BA5 - Comet Lake-S GT1 [UHD Graphics 610] 8086:9BA4 - Comet Lake-H GT1 [UHD Graphics 610] [3] 8086:9BA2 - Comet Lake-H GT1 [UHD Graphics 610] Allows coreboot to correctly initialize IGD (8086:9ba8) in Intel Celeron G5905 CPU (ID a0653, Cometlake-H/S G1 (6+2), ucode: 000000f9). This can also be verified using devicehunt.com [2,3]. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html [2] https://web.archive.org/web/20240731150632/https://devicehunt.com/ view/type/pci/vendor/8086/device/9BA8 [3] https://web.archive.org/web/20230928015210/https://devicehunt.com/ view/type/pci/vendor/8086/device/9BA4 Change-Id: I776f434f3627d6fbd046a92eb736b1ffcac8274a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11soc/intel/cml, pci_ids: Fix ID for Comet Lake-H GT2Maxim Polyakov
According to the Intel GPU list[1], 0x3E9B is DID of "Intel UHD Graphics 630" for the Coffee Lake processor family and has already been added to the pci_ids.h as PCI_IDE_INTEL_CFL_H_GT2. At the same time, the real PCI DID for Comet Lake-H GT2 is 0x9BC2 [1], which is missing in the file. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11util/lint/lint-final-newlines: Supply dirs in rowMaximilian Brune
This just orders the EXCLUDED_DIRS directories in a row based manner, since there are quite a few them now and it is arguably easier to read and to add new directories if they are written in a row based fashion. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I802aece355bba4900e71824d802c4b2438726e84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11tree: Use boolean for dmi_power_optimize_disableElyes Haouas
Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11tree: use boolean for hybrid_storage_modeElyes Haouas
Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-10tree: Use boolean for lpss_s0ix_enableElyes Haouas
lpss_s0ix_enable is already defined as boolean: `git grep lpss_s0ix_enable $(find -type f -name "*.h") src/soc/intel/apollolake/chip.h: bool lpss_s0ix_enable;` Change-Id: I34bd568defe202daaad6136b9c184bc292a226b3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-09-10intel/alderlake: Order Kconfig selectors for FSP pathsNico Huber
Should make the sorting order of the paths more obvious. Change-Id: Ie73e717f37f80a11a903e99cc094ea4d76e1ca1f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83827 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10intel/alderlake: Drop redundant Client/AlderLake* FSP pathsNico Huber
The Alder Lake "Client" FSP paths have been replaced by symlinks to Raptor Lake in the FSP repo. Hence we get the same files anyway and can spare us to maintain the individual paths. Change-Id: Ia9b256ce1940894e2cf31acaa4a83ea39f6723b6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-10mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPUWentao Qin
Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:364484621, b:361828368 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage w/o this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ ``` w/ this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+ ``` Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84241 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/starlabs/starbook/adl: Add USB ACPI to devicetreeSean Rhodes
Change-Id: I7050a4d12efd65c7026abf3e45961e2061b7170a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10mb/starlabs/starbook/adl: Remove PMC GPIO routingSean Rhodes
These aren't used so remove them Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10mb/starlabs/starbook/adl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10ec/starlabs/merlin: Don't report the battery serial number to ACPISean Rhodes
Reporting the battery serial number to ACPI causes Windows to say there isn't a battery present. As the serial number is as useful as waterproof towel, don't do it. Change-Id: I97a28b1d8d7bb45ea4790c8125cd3c1bc52ee5f9 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10ec/starlabs/merlin: Move the chip id checkSean Rhodes
As the merlin EC supports both the IT8987 and IT5570, move the check into the code so the same variant directory can be used for both chips. Change-Id: I8c43a367e42f7e56ddd26b1c8fe7bf4b275d4ac3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83632 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/dell/snb_ivb_latitude: Move early_init.c out of variantsNicholas Chin
Now that the USB configs are in the devicetree, only the bootblock_mainboard_early_init function remains in early_init.c. It is identical between every variant except the E6230, which enabled fewer decode ranges in the LPC_EN register. Enabling the additional decode ranges probably shouldn't cause issues, so go with the majority. TEST=Timeless builds do not change with the exception of the E6230. Change-Id: Ic43915888f5893652991b7402ebab3bd3a2cf278 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-10util/ifdtool: Exit with failure on unrecognized flagsHsuan Ting Chen
ifdtool will exit with success while encountering an unrecognized flag. For example, -g is a newly introduced flag, when we want to call it with an older version of ifdtool, we will get the return value 0 and cause confusion. This patch change the exit status for unrecognized flags and doesn't change the exit status for -h and -?. BUG=b:362983041 BRANCH=none TEST=futility update --servo --image /var/tmp/image.bin --quirks unlock_csme on the servo host with old ifdtool Signed-off-by: Hsuan Ting Chen <roccochen@google.com> Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-10mb/google/nissa/var/teliks: Update eMMC DLL tuning valueszengqinghong
Update eMMC DLL tuning values for improved initialization reliability. BUG=b:361013271 TEST=Cold reboot stress test over 2500 cycles Change-Id: Icd1f9c7bdec2bc99152a13ac4ce0724a26718a52 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84248 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/google/nissa/var/joxer: Use `DB_USB` to probe conn1 deviceSubrata Banik
Joxer experienced error messages during developer mode entry due to failed USB-C1 probing. This patch adds the `DB_USB DB_1C` probe directive to the `conn1` device in the overridetree, ensuring USB-C1 is only probed when `FW_CONFIG` supports the applicable hardware SKU. This should resolve the error flood seen during dev mode entry on Joxer. BUG=b:364240631 TEST=Able to build and boot google/joxer to OS without any error. w/o this patch: send_packet: CrosEC result code 9 send_packet: CrosEC result code 3 Failed to get PD_MUX_INFO port1 ret:-3 update_all_tcss_ports_states: port C1: get_usb_pd_mux_info failed send_packet: CrosEC result code 9 send_packet: CrosEC result code 3 Failed to get PD_MUX_INFO port1 ret:-3 w/ this patch: No error reported during dev mode entry Change-Id: I8cdefa01409d5a8a75032f30dacde40057e064dd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-10include/console/system76_ec.h: Remove unused <stddef.h>Elyes Haouas
Change-Id: I3ac96786b4bbf7c8b3a8b57f58df396b1b754bd3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83953 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10nb/amd/agesa/agesa_helper.h: Remove unused <stddef.h>Elyes Haouas
Change-Id: I991ce1e264c3ca01bc34904b5efe758a3eb58806 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83952 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10cpu/x86/smm/smm_module_handler: Remove <commonlib/bsd/compiler.h>Elyes Haouas
<commonlib/bsd/compiler.h> is automatically included. Change-Id: I653f6c6099512c6e5ab64207f99e7813e4403f05 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-09Docs: Revert false MyST Parser toctree conversionsNicholas Chin
Commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser) converted recommonmark style toctrees in bulk using a script. This was done by searching for lists of references, which is how recommonmark denoted toctree entries. However, this also converted lists of external URLs, which would not normally be included in the toctree. Revert these cases back to lists of URLs as they were before the migration. Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-09-09Doc/rmodules.md: Move to libNicholas Chin
The content of this page fits lib the best, which also reflects the location of the rmodule runtime code in the src tree. This also fixes a "document isn't included in any toctree" warning from Sphinx since it is now added to the lib/index.md toctree. Change-Id: I86545f4c1a7e1b3ccefa4f6085e764536f33f29c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-09Doc/rmodules.md: Change header levelsNicholas Chin
Increase the header levels of headers following the initial "Relocatable Modules (rmodules)" so that there is only one title for the page with the other headings as subheadings. Also fix header capitalization while we're here. Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84239 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09intel/alderlake: Sort FSP paths, most specific selectors firstNico Huber
The `!FSP_USE_REPO` is most specific, if we're not using the FSP repo, we can ignore all the FSP-repo paths. Hence put these first. Having `FSP_TYPE_IOT` selected is also more specific, we can ignore all the "Client" paths then. This makes sure that we don't catch a "Client" by accident (otherwise we'd have to add a `!FSP_TYPE_IOT` for those). Change-Id: Ibe9931d8f964a337c46fde31a3bc22c69d40eded Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-09util/cbfstool: Print max empty entry size in error messageYu-Ping Wu
Currently, cbfstool prints the following error message when the added file doesn't fit in the region: E: Could not add [file, 1024 bytes (1 KB)@0x0]; too big? It requires manual inspection to know the space left in the region. To make that easier, also print the maximum empty CBFS entry size in the error message: E: Could not add file [header 76 + content 1024 bytes (1 KB)] @0x0; Largest empty slot: 512 bytes Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-09-09soc/mediatek/common: Move common GPIO definitions to gpio_defs.hYidi Lin
BUG=none TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84221 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09soc/amd/cezanne: Add an option to enable A/B recovery schemeZheng Bao
Extracted from NDA spec #56995: "The A/B recovery scheme formally separates the SPI flash space into different partitions; a primary, “A” and secondary, “B”, which hold the same set of system firmware. Under this scheme, the partitions A and B can hold identical contents initially, but each partition can be updated individually. Normally the system boots from partition A, but if the A partition is found to be corrupted, the system will switch to partition B and boot. The OEM BIOS can then choose to continue the boot from partition B, or repair partition A using contents from partition B." The Cezanne platform supports both A/B recovery and no recovery method. It needs this flag passed to amdfwtool to enable the A/B recovery layout. Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-09mb/google/zork: Add Kconfig to set IGD UMA allocation via APCBMatt DeVillier
Add a Kconfig choice to select the IGD UMA allocation, which selects a precompiled ACPB binary with the corresponding UMA value set. Default to the previous value (128MB) for non-ChromeOS builds, and 64MB for ChromeOS as that is the value used there. TEST=build/boot google/morphius, verify UMA size changes with selection via dxdiag tool under Windows. Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84237 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntaxNicholas Chin
MyST Parser uses {eval-rst} to denote embedded reStructuredText blocks, not eval_rst as was previously used by recommonmark. Change-Id: I3476d205605675690eb0d434f4ae9b7b2f091748 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84238 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09soc/intel/xeon_sp: Reserve MMIO high rangeShuo Liu
Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will assign domain MMIO high windows from this range. However, there will be unassigned parts among these high windows for non-domain device usage (e.g. misc devices belonging to an IIO stack but not belonged to any PCIe domains under that stack). This will cause segmentation in MTRR UC coverage. For example, in SPR-XCC where only CPM0/HQM0 are supported and instantiated to PCIe domains, MMIO ranges are still reserved for CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c. Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR calculation, this reservation will connect the discontinued domain MMIO high windows together to form one continuous range, and save MTRR register usage from inadequacy. This change is initially raised for SPR but could be effective for GNR as well. TESTED = Build and boot in intel/archercity CRB, MTRR register usage decreases from 7 to 3 in 2S system. TESTED = Only setting MTRR for below 4GB ranges test fails with LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb) tsc: Detected 2000.000 MHz processor last_pfn = 0x2080000 max_arch_pfn = 0x10000000000 x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM. ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9 ... Call Trace: ? 0xffffffff8f600000 ? setup_arch+0x4bb/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0 ---[ end trace 0e56686fd458f0c5 ]--- update e820 for mtrr modified physical RAM map: modified: [mem 0x0000000000000000-0x0000000000000fff] reserved ... modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved last_pfn = 0x6354e max_arch_pfn = 0x10000000000 Memory KASLR using RDRAND RDTSC... x2apic: enabled by BIOS, switching to x2apic ops Using GB pages for direct mapping ... Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff] DMA zone: 28769 pages in unavailable ranges DMA32 zone: 19122 pages in unavailable ranges BUG: unable to handle page fault for address: ff24b56eba60cff8 BAD Oops: 0000 [#1] SMP NOPTI CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2 ... Call Trace: ? set_pte_vaddr_p4d+0x24/0x35 ? __native_set_fixmap+0x21/0x28 ? map_vsyscall+0x35/0x56 ? setup_arch+0xa00/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb CR2: ff24b56eba60cff8 ---[ end trace 0e56686fd458f0c6 ]--- RIP: 0010:fill_pud+0xa/0x62 ... Kernel panic - not syncing: Attempted to kill the idle task! ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83538 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-08mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macroNicholas Chin
Use the AZALIA_PIN_DESC macro from include/device/azalia_device.h instead of magic numbers, as well as the enums for each of the register field values. The macros were generated by running util/hda-decoder against the original azalia logs used for the original board ports. TEST=Timeless builds for all variants did not change between main and this patch Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84099 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-09-08mb/google/kahlee: Add Kconfig to set IGD UMA allocationMatt DeVillier
Add a Kconfig choice to select the IGD UMA allocation. Default to the previous value (32MB). TEST=build/boot google/liara, verify UMA size changes with selection. Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84235 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-07soc/intel/ptl: Add GPIOs for Panther Lake SOCCliff Huang
Add definitions for the GPIO pins on Panther Lake SoC, as well as GPIO IRQ routing information and defines for ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_V, GPP_C Comm. 1: GPP_F, GPP_E Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 Comm. 4: GPP_S Comm. 5: GPP_B, GPP_D, VGPIO ref doc: - PT EDS vol2 - Panther Lake H GPIO Implementation Summary (#817954) BUG=b:348678529 TEST=Verify on Intel Silicon platform for PTL using google/fatcat mainboard. Note that these GPIO changes cannot be verified along as they are merely data structure and defines for the SOC. With the GPIO ASL, we should see the following GPIO instances under /sys/bus/acpi/devices when booting to OS: INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/ Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-07soc/intel/{common,alderlake}: Add missing ADL-N SKUsMichał Żygowski
Based on DOC #767454 (public) version 1.2. Allows to boot the HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID was not recognized and the SA driver did not pick up the stolen ranges, causing the PCI MMIO allocation to be placed in the stolen areas. TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04. Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-07nb/intel/sandybridge: Add Kconfig to set default IGD allocationMatt DeVillier
Add a Kconfig choice to select the default IGD memory allocation, for users/boards which do not use an option table to set it. TEST=build/boot google/link, verify IGD size changes with selection. Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-07mb/google/dedede/var/awasuki: Update touchscreen power sequenceTongtong Pan
Reduce resume time. BUG=b:361728839 TEST=emerge-dedede coreboot chromeos-bootimage & test touchscreen function on awasuki DUT Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84196 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-07amdfwtool: Set L2 table size as 0x400Zheng Bao
The Max size of L2 table is 0x400. If we set it to other value, the the A/B recovery image can not boot on Cezanne/Majolica platform. The affected boards are Birman, Chausie, Skyrim, Mayan. Other boards are binary identical. Tested on Skyrim and image can boot. Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84194 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-07drivers/intel/fsp2_0: Consolidate `BUILDING_WITH_DEBUG_FSP` optionSubrata Banik
Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly improves the option's prompt and help text. TEST=Built and booted google/rex successfully. Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-07drivers/intel/fsp2_0: Add Kconfig option to control MBP HOB creationSubrata Banik
This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. Disabling this option can improve boot time on platforms that do not utilize the MBP HOB, such as ChromeOS devices. The option is disabled by default on ChromeOS and enabled by default on other platforms. On ADL-P based platforms, this option is forced to be enabled as ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config from MTL and TGL config file. TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when it is disabled. Also verified that the system boots successfully in both cases. Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-063rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWERMichał Żygowski
Signing is performed with test keys by default, set CONFIG_SIGNING_KEYS_DIR to a non-empty value to use other keys. Depending on the version of the Talos II firmware this alone might not allow booting because coreboot replaces only part of the stock firmware and its newer versions enable secure boot by default (not to be confused with SecureBoot in EFI). The signing performed in this commit is still a prerequisite and might as well be done on its own. Fixing operation with newer stock firmware will be done in a follow-up change. Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-09-06mb/starlabs/byte_adl: Add Alder Lake N Byte Mk IISean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/byte-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-06soc/intel/common/gpio: vm index changes as PTL vm entries are not continuousCliff Huang
Add specific virtual wire mapping structure for: - First pad group does not starts with bit position 0. - vw_index and position are not continuous in between groups within a community. BUG= TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-06mb/google/brask/var/bujia: Add PSYS settingShon
According to the Intel OPS spec, the DC power from display is 12~19V@8A max. It can't set PsysPmax by unknown voltage, so get voltage by ec command "ectool adcread 4" then calculate PsysPmax value. The OPS display can supply 90W power, configure psys_pl2 to limit the system power to 90W. BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk intel-rplfsp intel-adlfsp coreboot chromeos-bootimage Check adcread value by ectool adcread 4. If get 19540, PsysPmax should be 19540 * 8000 ~= 156 W. Check FSP debug log have the following message. PsysPmax = 156W Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-09-06vc/google/chromeos: Skip boot info logging if cse sync at payloadDinesh Gehlot
This patch skips event logging for current boot information at ramstage if CSE sync is scheduled at payload. Given that CSE sync could initiate a system reset, resulting in redundant boot information logs, the payload should handle the logging of boot information following CSE sync. BUG=b:360082747 TEST=Verified elog boot info is not logged at ramstage Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84120 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-06soc/mediatek/mt8196: Add EINT supportYidi Lin
Add support to configure GPIOs to pull for external interrupts (EINT). BUG=b:334723688 TEST=Talk with Ti50 TPM using IRQ flow. Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84026 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-06mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCMWisley Chen
Add control for the 1.2V enable pin in VCM to comply the mipi camera power sequence. 2.8V enable --> 1.2V enable --> reset BUG=b:362386165 TEST=Run ITS test Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84211 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-06Makefile.mk: compile ECC tools and inject ECC to final imageMichał Żygowski
$ build/cbfstool build/coreboot.rom print FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs_master_header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 18495 LZ4 (30096 decompressed) fallback/ramstage 0x4940 stage 24288 LZMA (61240 decompressed) config 0xa880 raw 1324 LZMA (3308 decompressed) revision 0xae00 raw 726 none build_info 0xb100 raw 122 none (empty) 0xb1c0 null 347108 none header_pointer 0x5fdc0 cbfs header 4 none Change-Id: I8541aa6f1429ed6143830ed11c47c150183ddf0d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67064 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-09-06mb/google/brox/var/lotso: remove unused cam enable_gpioJian Tong
Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84198 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-06mb/google/brox/var/lotso: disable RTS5227 PCIE L0s supportJian Tong
Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1. lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled. BUG=b:359409425 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84177 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-06mb/google/brox/variants/brox: Update PL1 MinSumeet Pawnikar
Update PL1 Min value from 6W to 15W based on the brox thermal cooling capacity and hardware design. BUG=None BRANCH=None TEST=Build and boot on brox board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-06drivers/i2c/generic: Remove erroneous acpigen_pop_lenSean Rhodes
There are one too many acpigen_pop_len calls in the code to generate the ROTM; remove one to fix an EMERG warning: [EMERG] ASSERTION_ERROR: file `src/acpi/acpigen.c`, line 38 The extra acpigen_pop_len() call was added commit 45d2c3d5436e ("i2c/drivers/generic: Return ROTM in a package"). Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-05soc/intel/pantherlake: Hardcode IOM_BASE_ADDR_MAX valueJeremy Compostella
iasl refuses to perform an arithmetic computation in a QWordMemory parameter and fails with the following error. dsdt.asl 2149: 0x4010800000, ((0x4010800000 + 0x10000) - 1), 0x0, Error 6051 - ^ Address Min is greater than Address Max This commit replaces the arithmetic with the result to define IOM_BASE_ADDR_MAX. BUG=b:348678529 TEST=Build for google/fatcat mainboard. Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f16 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84216 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-05mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic supportDavid Wu
When world-facing camera is absent, coreboot need to enable GPP_R6(DMIC_WCAM_CLK) and GPP_R7(DMIC_WCAM_DATA) for 3rd dmic support BUG=b:333973512 TEST=Boot google/riven to OS and verify 3rd dmic working properly. Change-Id: I6c8780ce37b5d3987f5cdf6e6e6d0b4896b33230 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84141 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-05soc/intel/common/systemagent: Fix grammer in commentsYuchi Chen
Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84199 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-05mb/google/brox/var/jubilant: Remove STORAGE_UNKNOWN fw_config optionKarthikeyan Ramasubramanian
With `probe unprovisioned` fw_config rule, there is no need to define an explicit STORAGE_UNKNOWN option. Hence remove it. BUG=None TEST=Build Jubilant FW image. Change-Id: I4f6ace4b39a1ee0b63486d3872b20c8da719ae4a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84095 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-05soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT tableCliff Huang
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-04src/include: Introduce a new BIT_FLAG_32(x) macroSaurabh Mishra
Introduces the BIT_FLAG_32(x) macro to create a 32-bit mask with the designated bit set. This ensures compatibility with the 32-bit 'GEN_PMCON_A' register on 64-bit systems, where 1ul is 64 bits wide and could potentially cause an overflow when shifted beyond 31 bits. Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04soc/intel: Refactor ITSS macrosSubrata Banik
This patch refactors ITSS related SoC specific macros by consolidating them into a common itss.h file. This improves code maintainability and reduces redundancy as each SoC previously defined the same macros. Specific changes include: - Move SoC specific ITSS macros into intelblocks/itss.h. - SoC code now includes intelblocks/itss.h instead of the SoC-local soc/itss.h. - Drop soc/itss.h from static ASL files. - Delete soc/itss.h from all SoC locals except Apollo Lake and Sky Lake. TEST=Able to build and boot google/hatch, google/xol and google/karis. Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-09-04mb/google/brox/jubilant: Tune I2C timingRen Kuo
Tune I2C2 timing: Set falling time to 250ns from 400ns to meet spec: "THIGH>0.6us" BUG=b:362685374 TEST= Build jubilant firmware Measure the i2c signal on jubilant to meet spec: I2C2 THIGH from 0.494 us to 0.76 us Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84143 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-04soc/intel/common/block: Include register offsets for POWER_CTLSaurabh Mishra
Details: - Add (POWER_CTL) – Offset 0x1fc required bits. Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04include/cpu/x86: Add Misc Enable and Thermal Interrupt Register MacroSaurabh Mishra
Details: - Add (TM1_TM2_EMTTM_ENABLE_BIT) - Offset 0x1a0 required bits - Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 0x1b2 required bits Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84174 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04soc/intel: Remove unused `GPIO_IRQ_xxx` definitionsSubrata Banik
This patch removes the GPIO_IRQ_START and GPIO_IRQ_END definitions from itss.h for Alder Lake, Cannon Lake, Elkhart Lake, Jasper Lake, Meteor Lake and Tiger Lake. These definitions are no longer needed. TEST=Able to build and boot google/xol and google/karis. Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84182 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-04soc/intel/meteorlake: Remove unused pch_handle_sideband() functionSubrata Banik
This change removes the unused pch_handle_sideband() function from the Meteor Lake platform code. TEST=Able to build and boot google/rex. Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04tree: Use boolean for emmc_enable_hs400_modeElyes Haouas
Change-Id: I41a877ed7f5f3d02904dc939b32996a7f6d45373 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for disable_package_c_state_demotionElyes Haouas
Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for disable_c1_state_auto_demotionElyes Haouas
Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for skip_ext_gfx_scanElyes Haouas
Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-09-04tree: Drop unnecessary "true/false" commentsElyes Haouas
Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-03util/inteltool: Fix format for PCI vendor/device IDsAlexander Couzens
PCI vendor/device IDs are 16 bit. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: I87804a63f04b7461d348a245531542776575eb7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84186 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-03mb/google/brox/jubilant: Generate RAM IDsRen Kuo
Generate RAM IDs of lp5 memory: 1)Hyinx 4GB*4 H58G56BK8BX068 2)SAMSUNG 4GB*4 K3KL8L80CM-MGCT BUG=None TEST=Run part_id_gen tool and check the generated files. Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-09-03mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13Ren Kuo
Modify the FP IRQ pin to GPP_D13 from GPP_F15 from HW change on EVT. The design change to follow the brox's GPE0 routing, and the FP wake source can be routed. BUG=b:363166664 TEST= Build jubilant firmware Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84124 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/lattepanda: Add support for LattePanda MuKunYi Chen
Add initial support for the LattePanda Mu board, which features: - Intel Alder Lake-N N100 processor - Samsung K3LK7K70BM-BGCP, 8GB LPDDR5 memory - Samsung KLMCG2UCTA-B041, 64GB eMMC storage - SO-DIMM 260-pin connector for function expansion This commit includes: - Basic board configuration - Memory initialization - Essential I/O setup - Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file from original BIOS - BIOS download link: https://github.com/LattePandaTeam/LattePanda-Mu located at "./Softwares/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip" Test Environment: - Carrier Board: Lite - Payload: mrchromebox/edk2 - EDK2 Version: uefipayload_202309 Test result Passed: - Windows 11 boot from eMMC - Install Ubuntu 24.04 on NVMe SSD - Ubuntu 24.04 boot from NVMe SSD - USB 3.0/2.0 functionality - Realtek RTL8111H-CG-RH Ethernet - HDMI Display - Audio over HDMI work in Ubuntu 24.04 Known Issues: - S3 sleep mode non-functional - Power-on after shutdown requires power removal - SuperIO UART not detected in Windows 11 - Audio over HDMI not work in Windows 11 - Windows 11 BSOD occurs with NVMe SSD installed: - Stop code: Machine Check Exception - NVMe SSD not working on Windows 11, except when: - KDNet Debugging enabled on NIC during boot - SSD becomes functional in this scenario Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-02drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_infoArthur Heymans
GCC LTO found this. Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84056 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/cherry: Complete PCIe reset in romstageYidi Lin
De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118 Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-02soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe resetYidi Lin
Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84117 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
2024-09-02drivers/usb/acpi: Add DSM for Intel BluetoothSean Rhodes
Add support for creating a DSM Method for Intel Bluetooth that is outlined in Intel's connectivity integrated guide (which has no document number). It supports two GUIDs: Set Tile Activaction (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9) BIT(0) Indicates whether the device supports other functions BIT(1) Set Tile Activation Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9) BIT(0) Indicates whether the device supports other functions BIT(1) Set Bluetooth reset timing Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84133 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/zork: Ensure eSPI GPIOs programmed w/o vbootMatt DeVillier
On the non-vboot boot path, eSPI is configured as part of fch_pre_init(), and we need to ensure that the mainboard sets the eSPI GPIOs properly before the common SoC code performs eSPI init. Use the mb_set_up_early_espi() function to set the eSPI GPIOs at the correct time. TEST=build/boot google/zork (morphius), verify keyboard functional. Change-Id: I03efe6def37a018c3de410523be21bf008174e94 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84148 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/zork: Ensure early GPIOs programmed w/o vbootMatt DeVillier
Now that zork can boot without vboot, ensure that the GPIOs set in verstage are programmed in bootblock on the non-vboot path. The eSPI GPIOs will be set in a subsequent patch using mb_set_up_early_espi() since setting them in bootblock_mainboard_early_init() would be too late given when the SoC eSPI init takes place. TEST=build/boot google/zork (morphius) w/o vboot Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 12:03:22 +0000