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2021-10-26soc/intel/alderlake: set lock offset for gpio pad communitiesNick Vaccaro
Initialize the pad_cfg_lock_offset field for the various gpio pad_community structures in the adl_communities. BUG=b:201430600 TEST='emerge-brya coreboot' and verify it compiles successfully. Change-Id: I2cd3e43a84b0140bb2aeae5de1e299db714d419b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-26soc/intel: Update api name for getting spi destination idWonkyu Kim
Update api name and comments to be more generic as spi destination id is not DMI specific. Update api name as soc_get_spi_psf_destination_id and comments. And move PSF definition from pcr_ids.h as it's not pcr id. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie338d05649d23bddae5355dc6ce8440dfb183073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2021-10-26soc/example/min86/Kconfig: don't unselect CPU_X86_LAPICFelix Held
Since all multi-core x86 CPUs need to have LAPICs, this option should be selected for soc/example/min86. TEST=The example/min86 mainboard still builds. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5aa6e850f0b4dca27309385ba889b04335fe4f0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held
With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/intel/socket_LGA775: Drop commented-out entriesFelix Held
The code for these CPU models isn't present in coreboot. These lines have been commented-out since they where added, so drop them. Change-Id: I8fc53fea4225217bc5bb70d839c280ebb64fd3a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/intel/*/Kconfig: move selection of CPU_X86_CACHE_HELPERFelix Held
Move the selection of CPU_X86_CACHE_HELPER to the Kconfig file of the CPU models which call the x86_enable_cache function that gets added to the build by selecting this option. Change-Id: Ie75682f5d20a79fc2f3aab9b8a2c3ccf79d1ad5c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26Documentation/releases/4.15: Add note about libpayload improvementsJakub Czapiga
Change-Id: I3043e70523db1b7f1df90789a69eadd155848bb0 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-10-26mb/prodrive/hermes: Remove overridetreeAngel Pons
There's no need to have an overridetree with a single board variant. TEST=Compare static.c and observe only device order has changed. Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-26mb/prodrive/hermes: Reorganize per-port PCIe settingsAngel Pons
Move per-port PCIe settings inside the corresponding PCIe root port device. Also, remove several unnecessary and/or redundant comments. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I3f64d56b3b2c592194b18ae7b7c63ef41a1e060f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-26cpu/x86: Introduce `CPU_X86_CACHE_HELPER`Felix Held
There's no need for relative paths with Kconfig options. Change-Id: Ib9b9b29a158c34a30480aaabf6d0b23819d28427 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/amd,intel/*/Makefile: don't add cpu/x86/cacheFelix Held
Some CPUs don't use the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ia44c7b150cd12d76e463903966f67d86750cbdd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26soc/*/Makefile: don't add cpu/x86/cacheFelix Held
No SoC uses the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26soc/intel/common: Add HECI Reset flow in the CSE driverSridhar Siricilla
This change is required as part of HECI Interface initialization in order to put the host and CSE into a known good state for communication. Please refer ME BIOS specification for more details. The change adds HECI interface reset flow in the CSE driver. It enables coreboot to send HECI commands before DRAM Init. BUG=b:175516533 TEST=Run 50 cold reset cycles on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba Reviewed-on: https://review.coreboot.org/c/coreboot/+/55363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-26soc/intel/adl: Skip sending MBP HOB to save boot timeMAULIK V VAGHELA
MBP Hob is being generated by FSP after getting data from ME. coreboot does not consume this HOB and FSP provides an option for bootloader to skip generation of MBP HOB. This will help in saving ~14 ms of boot time. Here is the data from Brya P1 Board: Before: 955 returning from FspSiliconInit 879,432 (99,156) After: 955 returning from FspSiliconInit 1,177,513 (84,506) BUG=b:188577893 BRANCH=None TEST=No functional impact on Brya system and boot time is reduced with this patch. Change-Id: Ibb64e4d0f4ae7212defb6704b05a78e754f75cd7 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58289 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-25mb/google/guybrush/var/nipperkin: override dxio to turn off WLAN ASPM L1.2/L1.2Kevin Chiu
turn off WLAN ASPM L1.1/L1.2 as a short-term w/a for WLAN AP probe failure. BUG=b:198258604 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage AP is able to be probed by wlan module Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ic7be523626b0ff6e4b1c66ba6af13b15061ef4cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-25sc7280: Add AOP FW download supportRavi Kumar Bokka
AOP firmware support from sc7280. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ib7027cdf78a9cdcccc8cfff7eef3cc540fb4093e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-25soc/qualcomm: Commonize AOP firmware supportRavi Kumar Bokka
Move AOP firmware support from qualcomm/sc7180 into qualcomm/common BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-25soc/qualcomm/sc7280: define the aop symbolsRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I62044f6fcb301c0ca35c42598f998913f9b94b95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-25soc/amd/common/block/lpc/Makefile: simplify handling spi_dma.cFelix Held
Use the verstage_x86 class for the spi_dma.c target instead of using the verstage class and guarding it with !VBOOT_STARTS_BEFORE_BOOTBLOCK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b8cafd1ef17df8c485f6594bc0928cea88e436b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-25cpu,soc/amd/*/Makefile: don't add cpu/x86/pae a second timeFelix Held
Since cpu/x86/Makefile.inc already adds the pae sub-directory, there is no need to include it in the Makefile of a CPU or SoC, so remove it from those Makefiles. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78368f7eb880fb64f511a2fa8c8acde222d0dca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held
All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25soc/intel/common: Skip CSE post hook when CSE is disabledSubrata Banik
This patch fixes regression introduced by commit bee4bb5f0 (soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM) FAFT test case fail when doing `firmware_DevMode` test. If CSE is already hidden then accessing CSE registers would be wrong and will receive junk, hence, return as CSE is already disabled. BUG=b:203061531 TEST=Brya system can boot to OS with recovery mode. Change-Id: I2046eb19716c397a066c2c41e1b027a256bd6cf9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25drivers/pc80/tpm: Use '%u' as printf formatter for unsigned variablesWerner Zeh
Use %u instead of %d for printing unsigned variables. Change-Id: I0f4bf7b80dfbde0802af8ad96fd553cb75d60e6e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25drivers/pc80/tpm: Use stopwatch for timeout-loopsWerner Zeh
There are manual timeout-loops which use a fixed value and udelay(). In all cases there is a debug printk() inside this loop which, when enabled, takes way longer than the counted microsecond delay. This leads to the result that e.g. a 1 second delay takes nearly an eternity if the debug messages are enabled due to the longer function execution time. This patch uses the stopwatch scheme for the timeout-loops which still makes sure that the timeout period is maintained while it takes longer function calls like printk() into account. In order to keep the minimum delay between two register accesses on the TPM keep the udelay(1)-call. TEST=Enable TPM debug messages on a board where the TPM hits a timeout by failure and make sure that the debug messages occur in the log just in the timeout period. It still works as expected if the debug messages are disabled. Change-Id: I8fd261c9d60a9a60509c847dbc4983bc05f41d48 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25mb/google/brya/variants/gimble: Enable Bluetooth offload supportMac Chiang
Enable CnviBtAudioOffload UPD BUG=b:199180746 TEST=emerge-byra coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: Ic507b1d0f7c2f38de8d24247cd677b897a7463f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25elogtool: add pytest for elogtoolRicardo Quesada
This CL adds a python test for elogtool. It tests the basic functionality of elogtool: list, clear and add. A future CL will include more complex tests. BUG=b:172210863 TEST=pytest elogtool_test.py Change-Id: If1241ad070d1c690c84f5ca61c0487ba27c2a287 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-10-24util/inteltool: Add PCH IDs for 200 series chipsetsTimofey Komarov
Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: Iadad5e79aef9da3fac627adc135525a5001a72b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-23arch/x86: fix a wrong variable in ioapic_set_max_vectors()Iru Cai
The commit 04a40379b has a wrongly written variable, which sets an IOAPIC register to a wrong value and makes the Linux kernel unable to boot. Tested on HP EliteBook 2760p, the kernel boots after this patch. Change-Id: Ifda7bb61a431dbf9c2df2f738aa806dd6d8097b8 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-22soc/amd/cezanne,picasso/chipset.cb: drop LAPIC deviceFelix Held
After adding code to handle the case of missing the link/bus on the CPU cluster device in mp_cpu_bus_init, there's no need to have the LAPIC device in the devicetree any more. TEST=Mandolin still boots successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icfc4fb61b373129f3bf4f4de09c38076a8f66733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22soc/intel/denverton_ns: use mp_cpu_bus_initFelix Held
After adding the functionality to add a bus/link on the CPU cluster device in mp_cpu_bus_init if it is missing due to no LAPIC device being present in the devicetree below the CPU cluster device, we can use mp_cpu_bus_init as init function in cpu_bus_ops and implement mp_init_cpus. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I76aebeca1b3227cfd310b6c45f506c042b35ae04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22include/device: ensure valid link/bus is passed to mp_cpu_bus_initFelix Held
When a chipset or mainboard devicetree doesn't have any LAPIC devices in its CPU cluster, not only the LAPIC device, but also the link/bus between the CPU cluster device and the LAPIC devices will be missing and the CPU cluster's dev->link_list will be NULL. This patch handles this case in the common code like commit 3c0ecd57c174b7391c66d22406effe18ce570cac (soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus) and commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9 (soc/intel/denverton_ns: Ensure CPU device has a valid link) already did in the common Intel SoC and the Denverton code. With this change all CPUs and SoC that use the common mp_cpu_bus_init as init function in the CPU cluster's device operations struct won't require having at least one LAPIC device in the chipset or mainboard device tree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0d85de5cafb6390b8fbd512186899d6a815e972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22soc/intel/elkhartlake: Add PSE PCI devices into header fileLean Sheng Tan
Since PSE devices could be initialized as either host owned (PCI devices) or PSE owned (will be hidden from coreboot and only visible to PSE interface), add all PSE devices in PCI list header file for future usage. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Iaa40cdcb021d05e50504dd85f94e9c021e284d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58466 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-22AGESA binaryPI: Use common acpi_fill_madt()Kyösti Mälkki
Change-Id: I01ee0ba99eca6ad4c01848ab133166f8c922684d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22mb/emulation/qemu-i440fx: Select IOAPICKyösti Mälkki
For SMP operation IOAPIC needs to be configured. For a build with MAX_CPUS=1 emulation might still decode the IOAPIC MMIO window, it does not really matter to have it always reserved. Change-Id: Ia340fc418cd9ceda56a2a10972e130d9f289c589 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()Kyösti Mälkki
This adds delivery of PIC/i8259 interrupts via ExtNMI on the affected platfoms. Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC max entries before APIC IDKyösti Mälkki
This allows to replace set_ioapic_id() call with setup_ioapic() that also clears redirection table entries. Change-Id: I854f19c997a96bcdccb11a0906431e3291788cb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22arch/x86/ioapic: Allow IOAPIC with only one vectorKyösti Mälkki
Remove the test for count=0 that leaked from drivers/generic/ioapic implementation. See commit ea2fb8d80 and commit 8cc25d229. Change-Id: I26944b930851fbea160c844ea46e2faa61c9af8e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-22sb,soc/intel: Set IOAPIC redirection entry countKyösti Mälkki
The number of redirection table entries (aka interrupt vectors) inside an I/O APIC may depend of the SKU, with the related register being of type read/write-once. Provide support utilities to either lock or set this registers value. Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22soc/intel/braswell: use mp_cpu_bus_initFelix Held
Implement mp_init_cpus and use mp_cpu_bus_init as init function in cpu_bus_ops. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2adcb1e1d79ced804925c81095cc5c0c2e6f9948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22soc/intel/baytrail: use mp_cpu_bus_initFelix Held
Implement mp_init_cpus and use mp_cpu_bus_init as init function in cpu_bus_ops. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I057ae8d95bdc510e9e7afb144b692531107fa45d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21soc/amd/common/block/cpu/smm/finalize: simplify finalize_coresFelix Held
The local variable int r isn't needed, so remove it. This is a preparation to change the return type of mp_run_on_all_cpus from int to enum cb_err which will be done in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c454cbfcc581be41ea3463ea6f852a72886128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21soc/intel/skylake/cpu: rework failure handling in post_mp_initFelix Held
Use a boolean type to store the information if any mp_run_on_all_cpus call failed. This is a preparation to change the return type of mp_run_on_all_cpus from int to enum cb_err which will be done in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic04ad3e4a781a00ee6edcd7dbd24bc7601be1384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21include/memory_info.h: Increase DIMM_INFO_TOTAL number from 8 to 16Tim Chu
Increase the number of total dimm to 16 to support system with more than 8 dimms. Also, remove unneeded comment. TESTED=On S9S, dmidecode -t 17 shows expected results. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Iead53e96f37c55ba1b7a13fb62db1a1c10fa2e1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58440 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21arch/x86/smbios: Add support for wake-up type in smbios type 1Tim Chu
Add system wake-up type in smbios type 1 - system information. TESTED=On S9S, can override original value and show expected result using "dmidecode -t 1". Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: If79ba65426f1f18ebb55a0f3ef022bee83c1a93b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-10-21mb/google/brya/var/kano: Correct GPIO GPP_R6 and GPP_R7 settingDavid Wu
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1). BUG=b:202913826 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ibf8ff0e48c4bab435d082dee27bcd53bc85b088d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21mb/google/brya/var/brask: Correct SSD power sequenceDavid Wu
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:197385770 TEST=emerge-brask coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia7e5c7b1a2194d53d98865d33cf1bc6111572876 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21mb/google/guybrush/var/nipperkin: Enable GPP2 for NVMe bridge eMMC storageKevin Chiu
BUG=b:195269555 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage eMMC sku is bootable Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: If9e0fdc1667cbaac05fdf4c6689d47a561016c9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC tableMichael Niewöhner
Some elements in the ACPI CPPC table allow static DWORDs. Instead of using a fake register resource, use a tagged union with the two types "register" and "DWORD" and respective macros for CPPC table entries. Test: dumped SSDT before and after do not differ. Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-21mb/google/guybrush/var/nipperkin: Override GPIO configurationKarthikeyan Ramasubramanian
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected in nipperkin. Override those GPIO configurations. BUG=None TEST=Build and boot to OS in Nipperkin. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-21mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO DescriptorKarthikeyan Ramasubramanian
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be de-asserted before PCIe link training during S0i3 resume. Otherwise the concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume. This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so that SMU de-asserts this reset on S0i3 resume. BUG=b:199780346 TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for 500 iterations. Ensure that the PCIe devices enumerate fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-21mb/google/guybrush: Make DXIO Port Descriptor configurableKarthikeyan Ramasubramanian
Instead of a const port descriptor, make it configurable. This will help to avoid adding duplicate tables for every minor configuration updates. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and cold reboot cycles for 10 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21cpu/x86/mp_init: use cb_err as run_ap_work return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_run_on_aps which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of run_ap_work gets translated to the int values in mp_run_on_aps. This could also be done by a cast of the run_ap_work return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id346c8edf06229a929b4783498d8c6774f54a8b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init & bsp_do_flight_plan return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_init_with_smm which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of mp_init gets translated to the int values in mp_init_with_smm. This could also be done by a cast of the mp_init return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4129c1db06a877c47cca87782af965b62dcbbdc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as wait_for_aps return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of wait_for_aps to not need a local timeout variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I86b8c8b0849ae130c78125b83d159147ce11914c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as apic_wait_timeout return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of apic_wait_timeout to not need a local timeout variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fe32c761492d252b154d2f50f2a330cf4f412d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as install_permanent_handler return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb64b5908b938bb162153433e5f744ab0b95c525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as install_relocation_handler return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95f36ba628c7f3ce960a8f3bda730d1c720253cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86: Remove cpu parameter to ap_initRaul E Rangel
We now pre-populate cpu_info before jumping to the C handler. We no longer need this parameter. I moved the stack alignment closer to the actual invocation of the C handler so it's easier to reason about. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify all CPUs still function Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8997683b6613b7031784cabf7039a400f0efdea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MPRaul E Rangel
This will reduce the number of AP init paths we need to support. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and see all CPUs initialized correctly Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21arch/x86,cpu/x86: Fix 64-bit CPU_INFO_V2 build errorsRaul E Rangel
There are two possible code sections where the cpu_info macros can be included: .code32 and .code64 Doing a `push %eax` while in a .code64 section will result in a compiler error. This macro manually pushes the 32-bit register onto the stack so we can share the code between 32 and 64 bit builds. We also can't implicitly dereference per_cpu_segment_selector because it's a 32-bit address. Trying to do this results in the following: E: Invalid reloc type: 11 E: Illegal use of 32bit sign extended addressing at offset 0x1b2 If we load the address first, then dereference it, we can work around the limitation. With these fixes, 64-bit builds can now use CPU_INFO_V2. BUG=b:179699789 TEST=Boot qemu 64 bit build with CPU_INFO_V2 and 4 CPUs. See AP init work as expected. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21mb/google/brya/var/kano: Enable BT offload supportDavid Wu
Enable the CnviBtAudioOffload UPD and program the corresponding BT VPGIOs. BUG=b:202913826 TEST=emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id81cba82742f552c098ec3719a0b453b752dc5c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21util/release/build-release: Create cross-toolchain version fileFelix Singer
Add cross-toolchain version file to the release tarball, which can be used for pre-setting the variables used in buildgcc. Change-Id: Iad1e0adaa95b71f161caf978276bfb0a63eac8f4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21util/crossgcc/buildgcc: Use pre-set CROSSGCC_VERSION if possibleFelix Singer
For reproducibility, a version string is appended to the version of the tools used in the cross-toolchain. Currently, git is used to determine that version string at runtime of this script. There are cases, where it's not possible to determine that version string, e.g. when a release tarball is used, and if so, the version string is just `v_`. Thus, allow pre-setting the variable `CROSSGCC_VERSION`. Change-Id: I888ccd877c93436b5e033528c43bd8667b8d2f10 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21mb/google/trogdor: determine which panel to use by panel_id for quackingstickSheng-Liang Pan
panel_id 6 for AUO B101UAN08.3. BUG=b:201263032 BRANCH=none TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I076ded9300c2ec1704a566722870bd0d1a20e9d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58363 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21mb/google/dedede/var/bugzzy: Add LTE power off sequenceSeunghwan Kim
This change adds LTE power off sequence for bugzzy. BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21mb/google/dedede/var/bugzzy: Enable/disable LTE function based on FW_CONFIGSeunghwan Kim
Enable/disable LTE function based on DB_PORTS field of FW_CONFIG. - GPIO control - USB port setting BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20cpu/x86/mp_init: rework start_aps to fix X86_AMD_INIT_SIPI caseFelix Held
When CONFIG_X86_AMD_INIT_SIPI was set, the second/final SIPI that afterwards checks if all APs have checked in was skipped and if it got so far, start_aps returned CB_SUCCESS despite not having checked if all APs had checked in after the SIPI. This patch makes start_aps skip the first SIPI in the CONFIG_X86_AMD_INIT_SIPI case so we use the proper timeouts and error handling for the final and this case only SIPI and signal the caller an error when not all APs have checked in after the SIPI. A timeless build for lenovo/x230 which is a mainboard that doesn't select X86_AMD_INIT_SIPI results in identical binary, so this doesn't change the behavior of the !X86_AMD_INIT_SIPI case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I39438229497c5d9c44dc7e247c7b2c81252b4bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-20google/trogdor: Support Parade ps8640Philip Chen
Support Parade ps8640 as the second source edp bridge for some trogdor board variants/revisions. BUG=b:194741013 BRANCH=trogdor TEST=verified firmware screen works on lazor rev9 Change-Id: Iae5ccd8d9d33d60e4c37011ecffdd7a05af59ab2 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-20mb/google/brya/var/redrix: Enable bt_offload supportMac Chiang
Enable CnviBtAudioOffload UPD and program the corresponding VGPIO pins BUG=b:191931762 TEST=emerge-coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I81bae537d52592e878db56343970de6fc488950f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20util/crossgcc/buildgcc: Allow printing only the versionFelix Singer
In preperation to CB:58396, add the parameter `-W|--print-version`, which allows printing the content of `CROSSGCC_VERSION`. In combination with CB:58396, this can be used to pre-set the variable in case of the git history is not accessible. Change-Id: I9a205ca0ecb0ece47eb5d8fa73706478354512ff Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-20util/crossgcc/buildgcc: Remove CROSSGCC_COMMITFelix Singer
For reproducibility, the buildgcc script is copied to the destination folder of the toolchain. `CROSSGCC_COMMIT` is used as a file name extension for the script and was introduced when `CROSSGCC_VERSION` didn't contain the commit yet. Since this is not the case anymore, remove it. Change-Id: Id0a0b657eb828b2728ff787228eaa38be83d9517 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58450 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20mb/intel/adlrvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: If68c118f22579cc0a3db570119798f0f535f9804 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: use cb_err as start_aps return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb96f28b4d59b3d00638a43c927df80f5d1643f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58455 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: add final new line to debug messagesFelix Held
Since during AP startup it's not guaranteed that no AP console output will be printed between consecutive printk calls in send_sipi_to_aps, add a new line character to all printks to make sure to have the outputs from the APs on separate lines. For consistency also add a final new line character to the printk call in start_aps. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3983b8a0e6b272ba5fb2a90a108d17a0c480c8b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58454 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: factor out send_sipi_to_aps functionFelix Held
Apart from the SIPI number in the debug message the two instances of the SIPI sending code in start_aps are identical, so factor it out into a new send_sipi_to_aps function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a921b81fce77fbf58c7ae3b50efd8c3e6e5aef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58453 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: use types.h includeFelix Held
Using types.h as include instead of stddef.h and stdint.h will also provide commonlib/bsd/cb_err.h which will be used in follow-up patches. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I08a68dc827d60c6c9a27b3ec8b74b9c8a2c96d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58452 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20util/cbfstool/rmodule: Omit undefined extern symbols from reloc tableRaul E Rangel
When using `DECLARE_OPTIONAL_REGION`, it is assumed that REGION_SIZE(name) == 0 if the region was not defined in the memlayout. When using non-rmodule stages (i.e., bootblock, romstage, etc), this assumption holds true, but breaks down in rmodule (i.e., ramstage) stages. The rmodule tool is not currently omitting undefined externals from the relocation table. e.g., extern u8 _##name##_size[]; This means that when the rmodule loader runs, it will rewrite the symbol from 0 (which is the default the linker assumed) to 0 + offset. This is wrong since the symbol doesn't actually exist. Instead we need to omit the relocation so it continues to keep the default value of 0. BUG=b:179699789 TEST=Print out REGION_SIZE(cbfs_cache) in ramstage and verify it is set to 0. I also see the following printed by the rmodtool now: DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone_size DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone DEBUG: Omitting relocation for absolute symbol: _stack_size DEBUG: Omitting relocation for absolute symbol: _program_size DEBUG: Omitting relocation for absolute symbol: _cbmem_init_hooks_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache DEBUG: Omitting relocation for undefined extern: _cbfs_cache DEBUG: Omitting relocation for undefined extern: _cbfs_cache_size As you can see the _watchdog_tombstone will also be fixed by this CL. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib57e263fa9014da4f6854637000c1c8ad8eb351a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20lib/cbfs: Call rdev_unmap on hash mismatchRaul E Rangel
We don't want to leak any mappings. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibcd28ce12cbd5e221e8f4fa910fd8472bedb802f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20kconfig_lint: use just one variable for keeping track of choicesMichael Niewöhner
Instead of using two variables, one for the boolean value and one for the path, use just one with the path. Since an empty string evalutes to false, this simplification does not change behaviour. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2f1171789af6815094446f107f3c634332a3427e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20kconfig_lint: put $inside_choice together right in the first placeMichael Niewöhner
Instead of substituting the delimiter later, put $inside_choice together right in the first place. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia713510a683101c48c86a1c3722ebb1607a29288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20soc/amd/common/block/cpu: Remove magic number in memlayoutRaul E Rangel
The SPI DMA controller can only perform transactions on a cache line boundary. This change removes the magic number and uses the #define to make it clear. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20soc/intel/alderlake: Fix wrong FIVR configs assignmentBora Guvendik
For PchFivrExtVnnRailSxEnabledStates, vnn_enable_bitmap config is used by mistake, instead of the expected vnn_sx_enable_bitmap Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Idf100be3ac4d6d97335c627e790c1870558d1210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/intel/adlrvp_m: Enable touchpadBernardo Perez Priego
These changes include ELAN touchpad to ACPI tables and configure GPIO's. BUG=None Test=Boot board, touchpad should be functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-20mb/intel/adlrvp: Remove EC regionBernardo Perez Priego
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ic76c29069beb510dd7620f340e0aab212668c3f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-20psp_verstage: remove psp_ef_table structKangheui Won
psp_efs.h now has embedded_firmware struct which is copied from amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to remove duplicates. TEST=boot on zork and guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-20mb/google/brya/anahera: Add two thermal sensor settingWisley Chen
Anahera has 4 thermal sensors, so add the missing sensors settings. BUG=b:203187535 TEST=build and verified by thermal team. Change-Id: I0e5c0d9c09c88cc95fdfd77b96800a0f4929d7d2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/brya/anahera: Update HID to MX98360AWisley Chen
Because of a change in the chromium OS kernel machine driver for the MAX98357A, a _HID that matches MAX98360A has to be used. (https://chromium- review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268/) BUG=b:200778066 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: Ic68373920d9135e614ff792149079de451ec6e60 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/taeko: enable DPTF functionality for taekoKevin Chang
Enable DPTF functionality for taeko BRANCH=None BUG=b:203035930 TEST=Built and tested on taeko board Change-Id: Ic9f3cbf5cd52ebc48b274b43fcdb57a51dcf94ec Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-10-20mb/google/brya/var/anahera: change from CLKREQ#2 to CLKREQ#6 for eMMCWisley Chen
Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6 BUG=b:197850509 TEST=build and boot into eMMC Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/dedede/var/bugzzy: Generate SPD ID for Samsung K4U6E3S4AB-MGCLSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20mb/google/dedede/var/sasuke: Generate SPD ID for Samsung K4U6E3S4AB-MGCLSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I91183f33b92569dd49967ef866d58043d79c287b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20soc/intel/{skl,apl}: don't run or even include SGX code if disabledMichael Niewöhner
Do not run or include any code in case the user did not explicitly enable SGX through `SOC_INTEL_COMMON_BLOCK_SGX_ENABLE`. Also move the ifdef inside the ASL file. Change-Id: Iec4d3d3eb2811ec14d29aff9601ba325724bc28c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-20mb/google/brya/var/taeko: Add fw_config probe for ALC5682-VSJoey Peng
ALC5682-VD/ALC5682-VS load different kernel driver by different _HID. Update the _HID depending on the AUDIO field of fw_config.Define fw config bit 5-7 in coreboot for codec. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: I635b173e0fe4c46d28f2c29fecee1998b29499b1 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/intel/jasperlake_rvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_JASPERLAKE_RVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: Ic7552195ed5a3ae6ab8e456d7d38d5539a052009 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-19soc/intel/skl: Constify `soc_get_cstate_map()`Patrick Georgi
This is a follow-up to commit e9f10ff38b which changed the base signature and all other occurrences. To make gcc11 happy (which is pickier about these things), let skylake follow. Change-Id: I42a629d865baa53640213a03e54e85623a386e35 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58458 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-19mb/intel/kblrvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_KBLRVP_COMMON`, which is used as base for each variant. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 13:41:56 +0000