mb/google/guybrush: Make DXIO Port Descriptor configurable

Instead of a const port descriptor, make it configurable. This will help
to avoid adding duplicate tables for every minor configuration updates.

BUG=None
TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and
cold reboot cycles for 10 iterations each.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 14 insertions, 89 deletions

diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index 09bded05ce..177b538e64 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -1,96 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <device/device.h>
 #include <device/pci_def.h>
 #include <soc/platform_descriptors.h>
 #include <soc/gpio.h>
 #include <types.h>
 
-/* All PCIe Resets are handled in coreboot */
-static const fsp_dxio_descriptor guybrush_czn_pci_wwan_descriptors[] = {
-	{ /* WLAN */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 0,
-		.end_logical_lane = 0,
-		.device_number = PCI_SLOT(WLAN_DEVFN),
-		.function_number = PCI_FUNC(WLAN_DEVFN),
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-	{ /* SD */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 1,
-		.end_logical_lane = 1,
-		.device_number = PCI_SLOT(SD_DEVFN),
-		.function_number = PCI_FUNC(SD_DEVFN),
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ1,
-		.gpio_group_id = GPIO_69,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-	{ /* WWAN */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 2,
-		.end_logical_lane = 2,
-		.device_number = PCI_SLOT(WWAN_DEVFN),
-		.function_number = PCI_FUNC(WWAN_DEVFN),
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ2,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-	{ /* NVME */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 4,
-		.end_logical_lane = 7,
-		.device_number = PCI_SLOT(NVME_DEVFN),
-		.function_number = PCI_FUNC(NVME_DEVFN),
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ3,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-	{ /* TODO: remove this temporary workaround */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 8,
-		.end_logical_lane = 11,
-		.device_number = PCIE_GPP_BRIDGE_2_DEV,
-		.function_number = PCIE_GPP_2_4_FUNC,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ5,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-	{ /* TODO: remove this temporary workaround */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 16,
-		.end_logical_lane = 23,
-		.device_number = PCIE_GPP_BRIDGE_1_DEV,
-		.function_number = PCIE_GPP_1_0_FUNC,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ6,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	}
+enum dxio_port_id {
+	WLAN,
+	SD,
+	WWAN_NVME,
+	NVME
 };
 
 /* All PCIe Resets are handled in coreboot */
-static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
+static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 	{ /* WLAN */
 		.engine_type = PCIE_ENGINE,
 		.port_present = true,
@@ -205,13 +130,13 @@ void mainboard_get_dxio_ddi_descriptors(
 		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
 		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
 {
-	if (variant_has_pcie_wwan()) {
-		*dxio_descs = guybrush_czn_pci_wwan_descriptors;
-		*dxio_num = ARRAY_SIZE(guybrush_czn_pci_wwan_descriptors);
-	} else {
-		*dxio_descs = guybrush_czn_dxio_descriptors;
-		*dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors);
-	}
+	/* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it
+	   is enabled. */
+	if (is_dev_enabled(DEV_PTR(gpp_bridge_2)))
+		guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE;
+
+	*dxio_descs = guybrush_czn_dxio_descriptors;
+	*dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors);
 
 	*ddi_descs = guybrush_czn_ddi_descriptors;
 	*ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors);