coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-01-24	soc/amd/cezanne: add basic romstage	Felix Held
2021-01-24	soc,vendorcode/amd/cezanne: add basic FSP integration	Felix Held
2021-01-24	soc/amd/picasso: Remove some empty strings	Zheng Bao
2021-01-24	soc/amd/cezanne: Add PSP integration for cezanne	Zheng Bao
2021-01-24	soc/intel/xeon_sp/cpx: Account for 'rc' heap manager	Arthur Heymans
2021-01-24	arch/x86/car.ld: Account for FSP-T reserved area	Arthur Heymans
2021-01-24	soc/intel/lpc_lib: drop dead code	Michael Niewöhner
2021-01-24	soc/intel/icl: drop wrong, unused code	Michael Niewöhner
2021-01-24	soc/intel/cnl: use Kconfig to determine PCH type	Michael Niewöhner
2021-01-24	soc/intel/broadwell: Align raminit with Haswell	Angel Pons
2021-01-24	soc/intel/broadwell: Drop `struct romstage_params`	Angel Pons
2021-01-24	broadwell: Flatten `mainboard_pre_raminit`	Angel Pons
2021-01-24	broadwell: Clean up `mainboard_post_raminit`	Angel Pons
2021-01-24	soc/intel/broadwell/chip.h: Drop unused fields	Angel Pons
2021-01-24	soc/intel/broadwell: Select CPU_INTEL_HASWELL	Angel Pons
2021-01-24	soc/intel/broadwell: Move romstage.c to Haswell	Angel Pons
2021-01-24	soc/intel/broadwell: Drop now-unused CPU code	Angel Pons
2021-01-24	soc/intel/broadwell: Use Haswell CPU headers	Angel Pons
2021-01-24	mb/google/auron: Use Haswell CPU code	Angel Pons
2021-01-24	mb/google/jecht: Use Haswell CPU code	Angel Pons
2021-01-24	mb/intel/wtm2: Use Haswell CPU code	Angel Pons
2021-01-24	mb/purism/librem_bdw: Use Haswell CPU code	Angel Pons
2021-01-24	soc/intel/broadwell: Allow to use Haswell CPU code instead	Angel Pons
2021-01-24	soc/intel/broadwell: Select INTEL_LYNXPOINT_LP	Angel Pons
2021-01-24	cpu/intel/haswell: Add Broadwell CPUIDs and microcode	Angel Pons
2021-01-24	cpu/intel/haswell: Set C9/C10 vccmin	Angel Pons
2021-01-24	cpu/intel/haswell: Add fast ramp voltage for Broadwell	Angel Pons
2021-01-24	lib/edid_fill_fb: Relax bits_per_pixel constraint	Raul E Rangel
2021-01-23	soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()	Kyösti Mälkki
2021-01-23	ACPI: Add helpers for CBMEM_ID_POWER_STATE	Kyösti Mälkki
2021-01-23	soc/amd: Rename chipset_state to chipset_power_state	Kyösti Mälkki
2021-01-23	ACPI S3: Replace stashed acpi_slp_typ value	Kyösti Mälkki
2021-01-23	intel/baytrail,braswell,broadwell: Add const qualifier for power_state	Kyösti Mälkki
2021-01-23	ELOG: Add const qualifier for chipset_power_state	Kyösti Mälkki
2021-01-23	soc/amd/picasso/pcie_gpp: Remove duplication in pirq_data declaration	Raul E Rangel
2021-01-23	soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 array	Raul E Rangel
2021-01-23	soc/amd/picasso/pcie_gpp: Add clarifying comment	Raul E Rangel
2021-01-23	mb/google/guybrush: Set FWM position to an upper address	Zheng Bao
2021-01-23	soc/amd/picasso/acpi: Remove dummy AOAC parent device	Raul E Rangel
2021-01-23	soc/intel/cometlake: Add ucode for CML-H	Tim Crawford
2021-01-23	3rdparty/intel-microcode: Update submodule to 20201118 release	Tim Crawford
2021-01-23	mb/google/auron: Drop `variant_romstage_entry`	Angel Pons
2021-01-23	mb/google/auron: Factor out SPD indexing	Angel Pons
2021-01-23	mb/google/auron: Factor out `mainboard_print_spd_info`	Angel Pons
2021-01-23	mb/google/auron: Merge two print statements	Angel Pons
2021-01-23	mb/google/auron: Drop `spd.h` from variants	Angel Pons
2021-01-23	mb/intel/coffeelake_rvp: do UART pad configuration at board-level	Michael Niewöhner
2021-01-23	soc/intel/apl: drop LPC pad configuration code	Michael Niewöhner
2021-01-23	drivers/intel/fsp2_0: Add meaningful ERROR message	Subrata Banik
2021-01-22	vendorcode/google/chromeos: Build CSE Board Reset in Romstage	Karthikeyan Ramasubramanian
2021-01-22	util/docker: Replace all variables in Dockerfile	Martin Roth
2021-01-22	soc/amd/cezanne: add pci_devs.h	Felix Held
2021-01-22	mb/amd/majolica: Add PSP support for board majolica	Zheng Bao
2021-01-22	mb/google/guybrush: Set the ROMSIZE as 16M	Zheng Bao
2021-01-22	ec/google/chromeec: Provide EC access for Retimer firmware update	John Zhao
2021-01-22	ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update	John Zhao
2021-01-22	drivers/intel/usb4: Enable retimer FW upgrade mux interaction	Brandon Breitenstein
2021-01-22	sconfig: Handle smbios_slot_desc in overridetree	Frans Hendriks
2021-01-22	mb/prodrive/hermes: Fix 30 second boot delay	Patrick Rudolph
2021-01-22	mb/google/octopus: Garfour override VBT selection	Tony Huang
2021-01-22	mb/google/nightfury: Update RAM IDs usage	Seunghwan Kim
2021-01-22	types.h: Add a helper macro BITS_PER_BYTE	Furquan Shaikh
2021-01-22	soc/intel/alderlake: Adding Kconfig for ADL_M PCH	Varshit Pandya
2021-01-22	soc/intel/commmon: Include Alder Lake device IDs	Varshit Pandya
2021-01-22	mb/google/volteer/var/elemi: Update dptf parameters	Wisley Chen
2021-01-22	soc/mediatek/mt8192: pmic: Set efuses manually	Hsin-Hsiung Wang
2021-01-22	mb/google/volteer/variants/eldrid: Configure USB2 port for Type-C	Nick Chen
2021-01-22	soc/mediatek/mt8183: Fix pq module size config	Yu-Ping Wu
2021-01-22	mb/emulation/qemu-q35: Account for TSEG	Arthur Heymans
2021-01-22	cpu/intel/haswell: Enable timed MWAIT if supported	Angel Pons
2021-01-22	soc/amd/common/block/smbus: always return SMBus MMIO in get_sm_mmio	Felix Held
2021-01-22	mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax	Elyes HAOUAS
2021-01-22	soc/intel/baytrail,broadwell: Refactor acpi_wake_source()	Kyösti Mälkki
2021-01-22	mb/google/kukui: Enable MT8183_DRAM_EMCP for katsu	Sunway
2021-01-22	Makefile.inc: Avoid --emit-relocs on RISC-V	Julius Werner
2021-01-21	soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16	Felix Held
2021-01-21	mb/siemens/chili: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/up/squared: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/intel/kblrvp: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/intel/minnow3: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/intel/leafhill: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/intel/glkrvp: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/intel/apollolake_rvp: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/intel/tglrvp: do UART pad config at board-level	Michael Niewöhner
2021-01-21	mb/intel/jasperlake_rvp: do UART pad config at board-level	Michael Niewöhner
2021-01-21	mb/intel/icelake_rvp: do UART pad config at board-level	Michael Niewöhner
2021-01-21	mb/google/reef: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/intel/minnow3: drop unneeded call to lpc_configure_pads	Michael Niewöhner
2021-01-21	mb/intel/leafhill: do LPC/eSPI pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/intel/glkrvp: do LPC/eSPI pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/up/squared: do LPC/eSPI pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/google/reef: do LPC/eSPI pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/google/hatch: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/google/glados: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/google/octopus: do UART pad configuration at board-level	Michael Niewöhner
2021-01-21	mb/google/dedede: do UART pad config at board-level	Michael Niewöhner
2021-01-21	mb/google/drallion: do early pad configuration in early bootstage	Michael Niewöhner
2021-01-21	mb/google/octopus: do LPC/eSPI pad configuration at board-level	Michael Niewöhner
2021-01-21	cpu/intel/haswell: Clean up CPUID definitions	Angel Pons
2021-01-21	cpu/intel/haswell: Add s0ix support	Angel Pons