diff options
| author | John Zhao <john.zhao@intel.com> | 2021-01-01 12:25:56 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-22 14:28:14 +0000 |
| commit | 408e5ab6c9d09fc34c7febc57438c6500e6efa9c (patch) | |
| tree | 2770edac86dd8e55b8ac1c44438e9d9e9e0c29d0 | |
| parent | 297d27b8bb628e40f93c283068cc68d033b9d162 (diff) | |
ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update
The RFWU byte is defined as Bits[3:0] for port number and Bits[7:4] for
operations. The supported operations are:
RETIMER_FW_UPDATE_PORT_INFO 0
RETIMER_FW_UPDATE_PD_SUSPEND 1
RETIMER_FW_UPDATE_PD_RESUME 2
RETIMER_FW_UPDATE_GET_MUX 3
RETIMER_FW_UPDATE_SET_USB 4
RETIMER_FW_UPDATE_SET_SAFE 5
RETIMER_FW_UPDATE_SET_TBT 6
RETIMER_FW_UPDATE_DISCONNECT 7
BUG=b:162528867
TEST=Booted to kernel and verified RFWU entry from ACPI DSDT ERAM field.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1ba04c6357b6fd0cc33ffce33e7e430539bace79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49051
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/ec/google/chromeec/acpi/ec.asl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 218d08b091..7b1a66391c 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -81,6 +81,7 @@ Device (EC0) Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power + RFWU, 8, // Retimer Firmware Update } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) |