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2023-02-24soc/intel/cmn: Include ME specification configuration at commonDinesh Gehlot
This patch includes ME specification configuration for various versions, which will allow SoCs to get ME support by selecting the correct version. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I817d14e52b0d353bbb4316d6362fcb80cbec3cda Reviewed-on: https://review.coreboot.org/c/coreboot/+/73128 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-23soc/amd/commmon/gfx: Generalize check for selective GOP initMatt DeVillier
Rather than explicitly checking for Recovery or Developer mode via vboot, use display_init_required() so that vboot is not required, and other instances where the display is needed pre-OS (such as when applying a critical system update) are covered as well. With this change, SoCs implementing selective GOP init will need to select VBOOT_MUST_REQUEST_DISPLAY in order for display_init_required() to not assert on compilation. BUG=b:255812886 TEST=build/boot skyrim Change-Id: Iac7e06863764a9f21c8a50fc19050cb5a6627df2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-23soc/amd/mendocino: Generalize check for selective GOP initMatt DeVillier
Rather than explicitly checking for Recovery or Developer mode via vboot, use display_init_required() so that vboot is not required, and other instances where the display is needed pre-OS (such as when applying a critical system update) are covered as well. Select VBOOT_MUST_REQUEST_DISPLAY in order for display_init_required() to function properly (and not assert on compilation). BUG=b:255812886 TEST=build/boot skyrim Change-Id: If2fee71bcc11468fd2db0abaafe4ea35e2953993 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-23vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4031.01Bora Guvendik
The headers added are generated as per FSP v4031.01 BUG=b:270416522 BRANCH=firmware-brya-14505.B TEST=Boot to OS Cq-Depend: chrome-internal:5513169, chrome-internal:5511170 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ia21807ee71c98489fd96f870c2d61f54e094c3d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-23mb/google/rex: Set audio GPIOs based on fw_configKapil Porwal
Define some actions based on probe results for audio: - Disable the SoundWire GPIOs when I2S option is selected. - Disable the I2S GPIOs when SoundWire option is selected. - Disable all the GPIOs when no audio is enabled. BUG=b:269497731 TEST=Test that GPIOs are configured based on the current value of the fw_config field in cbi. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0ed452a0d08e6779add318d9bbd1e97b50b6aea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-23mb/google/rex: Use gpio padbased table overrideKapil Porwal
In order to improve gpio merge mechanism. Change iteration override to padbased table override. And the following patch will change fw config override with ramstage gpio table override. Port of commit 7aef2b1294f2 ("mb/google/nissa: Apply gpio padbased table override") BUG=none TEST=Verify devbeep at depthcharge console Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2ee86bbec7d25a35d726f29ad79891f1054bf52c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73182 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-23soc/intel/elkhartlake/gpio.c: Fix GPD reset mapMichał Żygowski
The reset bit mapping was incorrectly assigned to GPIO groups. The reset mapping for Community 0 actually reflects the GPD reset mapping. Change the Community 0 reset mapping to the correct default map and fix the GPD reset mapping. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I2b9d093ca7ea0f5087f49671ca457c0b45927918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-23soc/intel/xeon_sp/uncore.c: mark TSEG/SMM region as reservedJonathan Zhang
Change-Id: I5f534a898de4ba58ac7d65c5bd6ee10eafa648e4 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-23intel/alderlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for RPL & ADL-N based ChromeOS platforms. It is not disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Taniks. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-23soc/mediatek: Add "DRAM" to Kconfig MEDIATEK_BLOB_FAST_INIT nameYu-Ping Wu
In the current Kconfig option MEDIATEK_BLOB_FAST_INIT, the meaning of "BLOB" is unclear. Add "DRAM" to the name. BUG=b:204226005 TEST=./util/abuild/abuild -t GOOGLE_STEELIX -x Change-Id: Ida7bda770f1d1a40cae205b08c8cb22f2329e49f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73155 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23mb/intel/mtlrvp: Move MX98357A codec out of soundwire nodeYong Zhi
MX98357A is not a soundwire codec, so move it out of drivers/intel/soundwire node. BUG=none TEST=Build and boot MTL-P RVP to Chrome OS. Verify I2S audio card enumeration and no max98357a entry under /sys/bus/soundwire/devices. Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: I24fc7084ea18445c341eed012cfacde8de126fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com>
2023-02-23mb/google/skyrim/var/crystaldrift: Update devicetree settingYunlong Jia
Setup FW_Config for our project. Configure USBHub\PIXA Touchpad\Audio(rt5682s & alc1019). BRANCH=None BUG=b:262798445, b:268621319 TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I2c590ae36d4d089f70e1799189cd414f825e5b8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-23Revert "soc/intel/adl: Select CSE defined ME spec version for alderlake"Lean Sheng Tan
This reverts commit 272c9c07bd9c7dcd684614c67487504ce06f7a36. Reason for revert: Sorry was going to give +2 but pressed the submit button and accidentally merged this out of train. Change-Id: I8a2c6407832bdcf3d475209356501f8fc3672f6b Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73213 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-23soc/intel/adl: Select CSE defined ME spec version for alderlakeDinesh Gehlot
Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I94cb8a9cbb6167d1a11a012efbd6a135a8692969 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73135 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23soc/intel: Use common codeflow for MP initArthur Heymans
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*: Remove lapic from devicetree). Alderlake cpu code was linked in romstage but unused so drop it. Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-22nb/amd/pi/00730F01/acpi_tables: use existing IO_APIC2_ADDR definitionFelix Held
Use the existing IO_APIC2_ADDR definition instead of a magic value. TEST=Timeless build results in identical image for pcengines/apu2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7ee039e23309fdae0d614bb1fb0610d82564bf3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-22soc/amd/picasso,stoneyridge/acpi: drop x_firmware_ctl_[l,h] assignmentFelix Held
The coreboot-common acpi_create_fadt writes a pointer to the FACS table into both firmware_ctrl and x_firmware_ctl_l FADT fields and sets x_firmware_ctl_h to zero. When x_firmware_ctl_[l,h] is non-zero, the pointer in firmware_ctrl will be ignored, but that's what is already done on Cezanne and newer. TEST=Linux doesn't complain about any new ACPI problem on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9eab4dcf828f28a60c6312ec96872aac4cfb266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-22sb/amd/pi/hudson/fadt: drop unneeded ARM_boot_arch assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the ARM_boot_arch FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id2d24a9b8d5b04271eb4da6a622b5bba66dbc501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73188 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-22soc/amd/picasso,stoneyridge/acpi: drop unneeded ARM_boot_arch assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the ARM_boot_arch FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ica968db1228a2d63e83f2b6c4ea57c5f02bf1504 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73187 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-22mb/google/*: Resume from suspend on critical batteryIvan Chen
This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate when the state of charge drops to low_battery_shutdown_percent. BUG=b:255465618 TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898) Verify system resumes from s0ix and then enter S5 on nivviks with steps: 1. disconnect AC 2. powerd_dbus_suspend --disable_dark_resume=false 3. fakebatt 5 4. fakebatt 4 Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9 Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-02-22soc/intel/xeon_sp/spr: Add common device treeTim Chu
Add common device tree used for EGS platform. Also add register setting shared for all EGS platform. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I812f621ee9d1643fd4fa35df92443d64f7aaabc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-22Revert "mb/google/poppy: Nami - invoke power cycle of FPMCU on startup"Subrata Banik
This reverts commit 2e6fa8206e0a3bdd2e53542b6377fe2b37e3f26e. Reason for revert: causing `redefinition` issue. src/mainboard/google/poppy/variants/nami/gpio.c:527:26: error: redefinition of 'variant_romstage_gpio_table' const struct pad_config *variant_romstage_gpio_table(size_t *num) ^ src/mainboard/google/poppy/variants/nami/gpio.c:426:26: note: previous definition is here const struct pad_config *variant_romstage_gpio_table(size_t *num) ^ Change-Id: I107cce8bf3a5bf38edb39b9d46512ee0d467d354 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73210 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-02-22soc/mediatek/mt8188: Fix audio sampling rateJohnson Wang
The current clock register definition is wrong, which results in wrong audio sampling rate. Fix it by adjusting the POSTDIV registers of APLL1-APLL5. TEST=build pass BUG=b:250459803, b:250464574 Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0 Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-22soc/mediatek/mt8188: Fix USB2 detection issueShaocheng Wang
MT8188 supports port0/port1 download. The hardware needs a trapping pin to select the port to use. When port1 is selected, the phy of port1 will be switched to port0. That is, port1 connector will be the physical line of port0. Since port0 phy isn't initialized in coreboot, switch back to port1 phy. BUG=b:269059211 TEST=can detect USB2 devices in depthcharge. Change-Id: Ic97d0bd9d0233883196b2e73ac2a22cd8ea9466b Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-22mb/google/dedede/var/dibbi: Enable USB2 port 6Sam McNally
USB2 port 6 may be used for a PL2303 USB to UART bridge, so enable the port. BUG=b:269690930 TEST=kernel can detect a PL2303 USB device BRANCH=dedede Change-Id: I0ba421c3a502e69d101de40bbd31122211d3fb05 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-02-22mb/google/poppy: Nami - invoke power cycle of FPMCU on startupTarun Tuli
Add functionality such that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami. Confirmed power is off for 150ms seconds on boot. Confirmed RCC_CSR of FPMCU indicates power cycle occurred. Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) Change-Id: I21eb85dc11e0ea0eb5de8a6092b01663d3c3df91 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68820 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-21soc/amd/phoenix: add VBIOS ID remapping for phoenixRitul Guru
Phoenix2 VBIOS PCI DID is 15c8 though the VBIOS image uses a different PCI ID i.e. 0x1205, so we need to implement map_oprom_vendev for the SoC. Change-Id: I7eef5eb41b781f02abb9dd4098e92a8652a431f5 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-21vga: Fix the support of extended ASCIIHsuan Ting Chen
VGA defineds the extended ASCII set based on CP437, but there is a bug on printing them: in vga_write_at_offset(), we perform a bitwise or between 'unsigned short' and 'signed char': ``` p[i] = 0x0F00 | string[i]; ``` If we want to show an extended ASCII character, string[i] will be negative and this bitwise operation will fail due to their implicit casting rule: convert signed char to unsigned short by adding 65536. To fix this, we need to cast the string to unsigned char manually somewhere. Since we still want to leverage the built-in string utilities which only accepts const char*, we still preserve the original prototypes before, and cast it until we write into the frame buffer. BRANCH=brya BUG=b:264666392 TEST=emerge-brya coreboot chromeos-bootimage and verify drawing characters with code > 127. Change-Id: I9cd65fe9794e5b0d338147924f28efd27fc8a1e8 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-21arch/x86/smbios: use cpu_cpuid_extended_level instead of open coding itFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice15f0ce591104a2ace186f9049748219c2bc097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-21mb/google/skyrim/var/markarth: Update Elan touchscreen power sequenceJohn Su
Based on product spec v1.4, update T3 timing from 180 ms to 150 ms. BRANCH=none BUG=b:262734395 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0d8f1e008276fccdfbb8c76cfebaccbe71160b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73130 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-21vboot: Fix reboot loop in recovery with VBOOT_CBFS_INTEGRATIONJakub Czapiga
After first recovery request coreboot would get stuck in bootloop with VB2_RECOVERY_PREAMBLE as recovery reason due to not checking whether coreboot is alread in recovery mode, and calling failing code. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Idc947a1d150ff6487cf973b36bf4f0af41daa220 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-20mb/google/brya/var/skolas: remove disable_package_c_state_demotionNick Vaccaro
Package C state demotion is now disabled for all RPL SoCs from within soc/intel/alderlake/fsp_params, so no need to duplicate that in the skolas devicetree.cb. BUG=268296760 BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Change-Id: I1c630e2efbdddd18a5423c79b73269e9b1be79c7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-20soc/amd/common/include/psp_efs: rename new PSP directory EFS entryFelix Held
The EFS entry at offset 0x14 can point to either the first level PSP directory table or to the PSP combo directory structure that was used before the introduction of the AMD A/B recovery scheme. This scheme is not to be confused with the VBOOT scheme. The PSP verstage code checks if the header this entry points to begins with the PSP_COOKIE, which indicates the entry is a first level PSP directory table. Due to that, the EFS entry at offset 0x14 is always expected to point to a PSP directory table, so rename combo_psp_directory to new_psp_directory to match the actual usage. This EFS entry that points to the PSP directory table is called new_psp_directory, since the entry at EFS offset 0x10 was used on some early AMD chips to point to the older PSP directory table and that one is already called psp_directory. amdfwtool uses the same naming scheme for those two PSP directory table pointers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10f19ee63f8d422433dba64402d84fd6bb9e0f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73083 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-20Makefile: Fix project_filelist.txt generationMaximilian Brune
The ctags tool (called by ctags-project target) currently complains about not finding certain files. The project_filelist.txt generation includes the compiler generated "*.d" files, except for files found in build/util. Most file paths in these "*.d" files are file paths relative to the root directory of coreboot. Some projects though are compiled separately from coreboot (e.g. payload, vboot, util). Some of these (e.g. util, vboot) are also put into the build directory of coreboot and relative file paths are relative to these projects instead of coreboot. This has the uncanning side effect that the ctags Makefile target can't find these files, since they are not relative to the coreboot root directory. This patch also excludes the build/external directory from those files, since they contain 'separately' compiled projects like 3rdparty/vboot. That fixes the ctags-project Makefile target. Change-Id: I16294171c29a0d5fd25a31018846f1013e130ee0 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71517 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-20soc/intel/rtd3: Hook up supported states to KconfigSean Rhodes
Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it is not, it will break S3 exit. When D3COLD_SUPPORT is not enabled, return `3` (D3Hot). This fixed S3 exit on both TGL and ADL. Tested on StarBook Mk V and Mk VI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72765 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-19soc/intel/xeon_sp/finalize.c: Set BIOS_DONE MSR as applicableTim Chu
If BIOS_DONE MSR is supported, set it after ReadyToBoot, because FSP programs certain registers via Notify phase ReadyToBoot and it cannot be modified by FSP after coreboot has set BIOS_DONE MSR, therefore we try to set BIOS_DONE MSR as late as possible to avoid this. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I4f19a7c54818231ebbccd2b6f8b23f47b117eb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71964 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-19soc/intel/common/block/fast_spi: Add SPI Vendor Component LockJonathan Zhang
Add fast_spi_set_vcl() to be called by the SOC lockdown function if SPI Vendor Specific Component Capabilities are desired. Change-Id: I6d9b58e90fa16c539b90c6b961862e97e1bf29a2 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72478 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-19crossgcc: Replace binutils no-bfd-doc patch with configure optionElias Souza
It is not more necessary to patch binutils, we can pass an argument during build time to not build docs. Regenerate binutils-2.37_no-makeinfo.patch. Change-Id: If600f0bb46db5f84956940683a7adc83eaca01e5 Signed-off-by: Elias Souza <eliascontato@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73115 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-19treewide: Remove useless "_STA: Status" commentElyes Haouas
Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-18util/spd_tools/src/spd_gen/lp5.go: Support LP5X 8533MbpsKyle Lin
Add support for LP5X 8533Mbps in SPD tool. BUG=b:263189532 TEST=None Change-Id: I72b02514f68647dda996822f910db8bc93f61ca4 Signed-off-by: Kyle Lin <kylelinck@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marx Wang <marx.wang@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-18mb/google/geralt: Report SKU ID and panel ID for unprovisioned devicesYidi Lin
To make MIPI/eDP panel functional on unprovisioned devices, it requires passing SKU ID and panel ID info to the payload(depthcharge) to load the corresponded device tree for kernel. BUG=b:247415660 TEST=cbmem -1 |grep "SKU Code". Change-Id: Id2254729b7bd621d1e9bc520e8f40916d0f81030 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73076 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-18soc/intel/meteorlake: Add PM Energy Report feature optionYong Zhi
This patch adds enable/disable FSP DisableEnergyReport feature option to be used in devicetree for power instrument purpose. BUG=None Branch=None Test=Build and boot MTL RVP. Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: I58d4aea28ee2561d2ed73260c40cb22ce3fdd135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-17cpu/amd/pi/00730F01/model_16_init: use CPUID_FROM_FMS macroFelix Held
Replace the magic number with the CPUID_FROM_FMS macro to make it easier to read. TEST=Resulting image of timeless build for pcengines/apu2 is identical Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I15480dc883b65b5ffaf0cd38cf4e1f7b2222022e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73069 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17cpu/amd/pi/00730F01/model_16_init: use CPUID_ALL_STEPPINGS_MASKFelix Held
Instead of having two entries for two different steppings of the same family and model combination using the CPUID_EXACT_MATCH_MASK, just have one entry that uses CPUID_ALL_STEPPINGS_MASK to cover all steppings. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0118bb9b4b0be4d954a657d50789addca08a784e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73068 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17mb/protectli/vault_cml: Disable PTT and SPI TPMMichał Żygowski
The platform supports a discrete LPC TPM module. However, ME firmware enables PTT by default and descriptor is configured for SPI TPM on the platform's original firmware. So disabling PTT in ME is not enough, because it falls back to SPI TPM. Ensure PTT is disabled in ME and SPI TPM is disabled in descriptor soft straps. TEST=Boot VP4650 and see LPC TPM is recognized by coreboot. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3764e085f2eb5ae957b9087d150320def7af4fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-02-17mb/protectli/vault_cml: Add Comet Lake 6 port board supportMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-02-17mb/google/skyrim/var/frostflow: Update Elan touchscreen power sequenceFrank Wu
Based on product spec v1.4, update T3 timing to 150 ms from 300 ms BRANCH=none BUG=b:269041202 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-02-173rdparty/intel-microcode: Update from 262f0c97f2fb to 2be47edc99eeFelix Singer
Updating from: 262f0c97f2fb microcode-20221108 Release Updating to: 2be47edc99ee microcode-20230214 Release This brings in 1 new commit: * 2be47edc99ee microcode-20230214 Release Change-Id: I3db14d7788ef93b320602e744ba322eb7f754a3c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-17soc/intel/common/block/graphics: Hook up all ADL-S IGD PCI IDsMichał Żygowski
Some users of MSI Z690-A board reported non-working IGD display during post using various CPUs. As not all PCI IDs were hooked, coreboot didn't detect GOP-provided framebuffer nor passed the framebuffer information to the payload, causing a black screen. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I07584e07182ee56b61b6f751100431589d1cbe83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elias Souza <eliascontato@protonmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17libpayload: Use __func__ instead of old __FUNCTION__Elyes Haouas
Change-Id: Ic3c22ac101a2ff44f97b2ac3fe3c0a89391718de Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17soc/intel/common/block/smbus/Kconfig: Drop unused ACPI driver Kconfig symbolElyes Haouas
Change-Id: Ic46e1663609068439069f666beca17ed76c679f0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69331 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17tree: Use __func__ instead of hard-coded namesElyes Haouas
Change-Id: I87e383ce2f28340dbc3c843dbf2ed0e47c00a723 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17nb/intel/pineview/raminit.c: Get rid of duplicated branchesElyes Haouas
Duplicated branches found using 'Wduplicated-branches' GCC flag. Change-Id: I252ea6aefb6d6c85135e640ba8deaa118be38f5e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_ART : Active Cooling Relationship Table"Elyes Haouas
Change-Id: Ief8dd9c7f7b82e1cd62de5bc1a361432b0eac4ca Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17mb/roda/rv11: Remove unuseful "_ALR: Ambient Light Response"Elyes Haouas
Change-Id: I3a846d8e4b70ccb3e6fde448c00376cd0088716c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17mb/rodarv11: Remove unuseful "_ALI: Ambient Light Illuminance"Elyes Haouas
Change-Id: I0cbdcd5a787d99e2579a312a51c63d7fc4120462 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_AEI: ACPI Event Interrupts"Elyes Haouas
Change-Id: I58a4e4fbd1a43462147daa58a5fda767cfd59c06 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_ADR: Address" commentElyes Haouas
Change-Id: Ib968fe7f9f95e8f690b46b868fd7d6f9332b4c9a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72664 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_CID: Compatible ID" commentElyes Haouas
Change-Id: I7db69e2faf412b9c6732f6dfc362d5774094ef27 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17Documentation/acpi: Add links to ACPI specificationElyes Haouas
Change-Id: I31250a914753136bc5d303e7ebccb3525cce0d86 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73034 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17util/crossgcc: Update GCC from 11.2 to 11.3Felix Singer
While the work on updating GCC to version 12 is still WIP, update it to the latest minor release 11.3. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I8810bbb238b01985774ff8da1e246ab1b192e663 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70221 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-17mb/hp/z220_series: Reorder Kconfig selects alphabeticallyFelix Singer
Change-Id: I4035fabd46b1ba7fa5463abb7f780aeccd6a96e0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-17lint/checkpatch.pl: Remove check for keyword 'boolean' in KconfigElyes Haouas
We can not use 'boolean' since commit 53ea1d44 "util/kconfig: Uprev to Linux 5.13's kconfig". This also reduce difference with upstream. Change-Id: Iff9fbde46784547c07726816d2fdd71967e0595e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORTSean Rhodes
Add NO_S0IX_SUPPORT for boards that do not support, or do not want to support S0IX. As all the boards in the tree that do this, don't support D3Cold, add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is selected to disable D3Cold support. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I03378cc7bb76fd65fcec81018e47f6288d437cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-17soc/intel/cmn/block/acpi: enable BERT table without crashlogJonathan Zhang
Besides crashlog, there's also other errors such as MCA error, which should be recorded in BERT table. With current code, BERT table is not generated if crashlog is not enabled. Add if statement for SOC_INTEL_CRASHLOG so that MCA error can be recorded in BERT table when crashlog is not supported. For some server mainboard, crashlog is supported through BMC instead of host firmware. Also check if BERT region is generated when crashlog is not enabled. Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-17mb/google/dedede/var/dibbi: Update devicetree for enabling audioSam McNally
Enable HDA device and update jack codec HID from ALC5682I-VD to ALC5682I-VS. BUG=b:268309238 TEST=kernel detects audio DSP and rt5682s BRANCH=dedede Change-Id: Icd17d5009ab8ef4711bb6c5fa414a8188fc0912f Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-17soc/intel/xeon_sp: move PCH specific code into lbg directoryJonathan Zhang
pmc_lock_smi() and pmc_lockdown_config() have PCH specific implementations. Move them from common lockdown.c and pmc.c into lbg/soc_pmutil.c. Move sata_lockdown_config() and spi_lockdown_config() to lbg/lockdown.c. While here, fix some coding style issues. Change-Id: I9b357ce877123530dd5c310a730808b6e651712e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-17mb/google/nissa/yaviks: Tuning eMMC DLL value for eMMC initialization errorchia-ling.hou
BUG=b:265611305 TEST=Reboot test 2500 times pass Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: I2b114cac58a7fadeaee6d48996cb8b51f192e78f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-02-17soc/intel/meteorlake: Improve `incomplete` debug messageSubrata Banik
This patch improves `incomplete` debug messages for missing ACPI name PCI devices. Additionally, using the proper PCI device B:D:F to locate the device with the missing ACPI name. Finally, modify the msg time from Debug to Warning to make it more purposeful. TEST=Able to build and boot google/rex. Without this patch: ``` [DEBUG]  dev->path.devfn=10 [DEBUG]  dev->path.devfn=a2 [DEBUG]  dev->path.devfn=b0 ``` With this patch: ``` [WARN]  Missing ACPI Name for PCI: 00:02.0 [WARN]  Missing ACPI Name for PCI: 00:14.2 [WARN]  Missing ACPI Name for PCI: 00:16.0 ``` Change-Id: I605e59de8cbec18c9a56eaa6e90a34f36ea4cdd9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73072 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-17soc/intel/cmn/acpi/pep: Add PCI device number for warning msgSubrata Banik
This patch fixes the wrong warning msg around `Unknown min d_state` with having proper PCI Bus/Device/Function number to help to parse the log better. With this patch: [WARN ]  Unknown min d_state for 20 [WARN ]  Unknown min d_state for 50 [WARN ]  Unknown min d_state for 98 [WARN ]  Unknown min d_state for 9a [WARN ]  Unknown min d_state for f9 With this patch: [WARN ]  Unknown min d_state for PCI: 00:04.0 [WARN ]  Unknown min d_state for PCI: 00:0a.0 [WARN ]  Unknown min d_state for PCI: 00:13.0 [WARN ]  Unknown min d_state for PCI: 00:13.2 [WARN ]  Unknown min d_state for PCI: 00:1f.1 Change-Id: Iccaf26882ce5998469b2be6cf5bc7082f193cb29 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-17vc/intel/fsp/mtl: Update header files from 2473_86 to 2523_80Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 2523_80, previous version being 2473_86. FSPM: 1. Rename DMI UPDs 2. Address offset changes FSPS: 1. Address offset changes BUG=b:266499304 Change-Id: Ib4b8478bc3558ef863b6b52e685f981a5891e4a9 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72591 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-17payloads/Yabits: Remove deprecated Yabits PayloadElias Souza
Yabits is no longer maintained and git repo is archived. Yabits has not been maintained for a long time, the project is apparently closed. Change-Id: Ida0bb79342448510d2c309339fabbe8066eca73c Signed-off-by: Elias Souza <eliascontato@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-16mb/scaleway/tagada: Drop supportFelix Singer
According to the author of the mainboard scaleway/tagada, the mainboard is not used anymore. Since the mainboard is not publicly available for purchase and not used anywhere else, the usual deprecation process of 6 months is not needed. Thus, to reduce the maintenance overhead for the community, support for the following components will be removed from the master branch and will be maintained on the release 4.19 branch. Also, add a note to the 4.20 release notes. * Mainboard Scaleway Tagada Change-Id: Ifb83b8f2b1dc40cbef657e52c629948dc466ec6e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72915 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/intel/elkhartlake/fsp_params.c: wire up remaining ddc paramsMichał Kopeć
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I434c22cd784e24c76bc47aee8728d28255b762db Reviewed-on: https://review.coreboot.org/c/coreboot/+/72405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-16commonlib/bsd, libpayload: Do not include helpers.h in stddef.hThomas Heijligen
`stddef.h` should only provide the definitions defined by ISO or Posix. The included `commonlib/bsd/helpers.h` provide a lot of non standard definitions that may interfere with definitions from the application. Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70116 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16libpayload/string: add strndup() functionThomas Heijligen
Change-Id: Ie509e49f21fb537692704ac6527efa09649164e3 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70115 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/amd/mendocino/Kconfig: add VGA BIOS ID and file defaultsFelix Held
Add the correct defaults for VGA_BIOS_ID and VGA_BIOS_FILE in Mendocino's Kconfig instead of relying on the board's .config files providing the correct settings. Those settings are per-SoC and not per-board, so this is valid for all boards using the Mendocino APU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I09c537d3801123e7ffc01608171918b0396b7a5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16soc/amd/cezanne/Kconfig: add VGA BIOS ID and file defaultsFelix Held
Add the correct defaults for VGA_BIOS_ID and VGA_BIOS_FILE in Cezanne's Kconfig instead of relying on the board's .config files providing the correct settings. Those settings are per-SoC and not per-board, so this is valid for all boards using the Cezanne APU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67101d518c6b873ad89932ae39c2deb2ed6a4c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16soc/amd/picasso/Kconfig: update VGA_BIOS_ID's help textFelix Held
map_oprom_vendev_rev is implemented in graphics.c in the SoC directory. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0123cb8ff662445fd0a613711d9e1981272b1235 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16mb/google/brya: Add new baseboard hades with variants hadesEric Lai
Add a new baseboard for hades, an Intel RPL based reference design. Also, add variants for the reference boards hades. This commit is a stub which only adds the minimum code needed for a successful build. Need update gpio and memory DQ pins after final shchematic comes out. BUG=b:269371363 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-16soc/amd/mendocino: Remove non-functional APCB checkFred Reitberger
The way the PSP_APCB_FILES list is created will always insert at least a space into it. When tested by the if, this space will prevent the else clause from ever running and never generate a build error. Remove the non-functional check. Instead, mainboards should select warn_no_apcb or die_no_apcb to generate a warning message or build error if the APCB is missing. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic96846d74df2dc279e13b22f2a83b6f893954fe8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73009 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/amd/glinda: Remove non-functional APCB checkFred Reitberger
The way the PSP_APCB_FILES list is created will always insert at least a space into it. When tested by the if, this space will prevent the else clause from ever running and never generate a build error. Remove the non-functional check. Instead, mainboards should select warn_no_apcb or die_no_apcb to generate a warning message or build error if the APCB is missing. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I26b96966495dc35a8b4a0cb7d5a841f3812f2a70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73007 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/amd/phoenix: Remove non-functional APCB checkFred Reitberger
The way the PSP_APCB_FILES list is created will always insert at least a space into it. When tested by the if, this space will prevent the else clause from ever running and never generate a build error. Remove the non-functional check. Instead, mainboards should select warn_no_apcb or die_no_apcb to generate a warning message or build error if the APCB is missing. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib9fe0f05739fb19da2494629dc1d5aaa0ca6431f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73006 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/amd/common: Add die_no_apcbFred Reitberger
Add target to die when no APCB is found. This is not always a fatal case, so mainboards can select between this and warn_no_apcb. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I5bbc8dd3200c4781677411e67a4b5f1fe8b20286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-16mb/google/geralt: Pass XHCI_INIT_DONE to the payloadYidi Lin
BUG=b:269059211 BRANCH=none TEST=emerge-gralt coreboot Change-Id: Ia2ec6db332939f1ac629cda9a0784a12c92d91da Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73056 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2023-02-16vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION configYidi Lin
Add Kconfig option for VBOOT_ARMV8_CE_SHA256_ACCELERATION, which will use ARMv8 Crypto Extension for SHA256[1] instead of software implementation. This will speed up firmware verification in verstage. [1] https://crrev.com/c/4170144 BUG=b:263514393 BRANCH=corsola TEST='calculating body hash (SHA2)' get 13 msecs improvement on Tentacruel. Before: 509:finished calculating body hash (SHA2) 161,548 (14,490) After: 509:finished calculating body hash (SHA2) 155,101 (1,187) Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72711 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16libpayload: Add VBOOT_SHA_ARMV8_CE configYidi Lin
Add Kconfig option for VBOOT_SHA_ARMV8_CE, which will use ARMv8 Crypto Extension for SHA256[1] instead of software implementation. [1] https://crrev.com/c/4170144 BUG=b:263514393 BRANCH=corsola TEST='vboot kernel verification' gets 111 msecs improvement on Tentacruel. Before: 1100:finished vboot kernel verification 905,150 (123,518) After: 1100:finished vboot kernel verification 787,277 (12,254) Cq-Depend: chromium:4170144, chromium:4242678 Change-Id: If92830830a0658dfad2a066e9efa624783865cf2 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-16Update vboot submodule to upstream mainYidi Lin
Updating from commit id ffb34f48: PRESUBMIT: disable automatic git cl presubmit to commit id 5b8596ce: 2sha256_arm: Fix data abort issue This brings in 15 new commits. Change-Id: I27a2dbd83114d7f5c075e0823f0c7948b82da694 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-16mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1Cliff Huang
Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec. BUG=none BRANCH=firmware-brya-14505.B TEST=Insert a SD card or NIC AIC on PCIe slot1 and run 'suspend_stress_test -c 1'. The RP8 should not cause suspend issue. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72422 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/intel/common/block/pcie/rtd3: Fix root port _ON logicCliff Huang
_ON() calls _STA() at the beginning. If _STA() indicates the device is ON, it exits immediately. The solution is to move this _STA() check into the ONSK logic. In general cases, ONSK remains '0'. NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following by a device reset such as WWAN device. When such device calls its _RST(), it increments OFSK. When the following _OFF() is called, it was scheduled to skip, it will also increments ONSK. Similarly, when the following _ON() is called, it checks if the previous _OFF was skipped or not. If skipped, it needs to do the same. In normal suspend/resume cases, these two variables remains '0'. No _OFF() and _ON() calls are skipped. entire generated code: Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { Return (One) } Acquire (\_SB.PCI0.R3MX, 0xFFFF) EMPG = Zero Local7 = 0x06 While ((Local7 > Zero)) { If ((AMPG == Zero)) { Break } Sleep (0x10) Local7-- } Release (\_SB.PCI0.R3MX) \_SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020, 0x00000020, 0x00000020) \_SB.PCI0.STXS (0x015E) If ((NCB7 == One)) { L23R = One Local7 = 0x14 While ((Local7 > Zero)) { If ((L23R == Zero)) { Break } Sleep (0x10) Local7-- } NCB7 = Zero Local7 = 0x08 While ((Local7 > Zero)) { If ((LASX == One)) { Break } Sleep (0x10) Local7-- } } } Else { ONSK-- } } BUG=b:249931687 BUG=b:241850118 TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72826 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directoryTim Chu
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset. These changes are in accordance with the documentation: * Intel(R) Emmitsburg Platform Controller Hub External Design Specification. Document Number: 606161 * Emmitsburg PCH BIOS Specification. Document Number: 631063. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-16mb/amd/birman&mayan: Use relative address as EC FW locationZheng Bao
When the flash size is over 16M, the absolute address could be lager than 16M, which can not be taken by CBFS. For the relative address, it is more flexible. This is one of series of patches to support 32/64M flash. BUG=b:255374782 TEST=binary identical test on birman and mayan when CONFIG_BIRMAN_HAVE_MCHP_FW and CONFIG_MAYAN_HAVE_MCHP_FW are set as y. Change-Id: I65be3039cd3449bfb481ad87281b72e88a58bd45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16mb/ocp/deltalake: Set SMM console log level via VPDJohnny Lin
Select DEBUG_SMI and RUNTIME_CONFIGURABLE_SMM_LOGLEVEL. Tested=On OCP Delta Lake, SMM log level can be changed via VPD variable. Change-Id: I73afc944fbd6c21e884397f3049bd363e2c1ce2c Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47006 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-16drivers/ocp/vpd: Override mainboard_set_smm_log_levelJohnny Lin
VPD variable 'smm_log_level' can be read and passed to SMM for overriding SMM log level. By default it's zero therefore it disables most of the SMM log. When we need to see SMM log we can set this VPD to a larger value to enable it. Implement mainboard_set_smm_log_level() that reads VPD variables for SMM log level. Change-Id: I90d471d1d070d9a0f1a82ca9da8a2c034c9fd574 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71992 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-16soc/intel/cmn/gfx: Skip warning msg in ChromeOS normal modeSubrata Banik
This patch ensures avoiding displaying wrong warning msg as `Graphics hand-off block not found` during ChromeOS normal mode booting as FSP is not executing GFX PEIM hence, GFX hand-off HOB is expected to be missing.  TEST=Able to build and boot google/rex in normal mode w/o having warning msg.  Change-Id: Ia9192129852195f6183c0c43369cd33b253f9140 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-16mb/google/rex: Mark unused USB ports as emptySubrata Banik
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Mainboard variants to override the USB ports as per the target board design. TEST=Able to build and boot google/rex with all USB ports are working as expected. Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-16mb/google/brask/var/aurash: Initiate coreboot settingZoey Wu
Initial Aurash configuration base on moli design. 1. Set up gpio. 2. Add memory config. 3. There is no SD card setting on aurash, remove it from overridetree. 4. Follow moli psys schematic design. 5. Enable BT offload. BUG=b:269063331 TEST=emerge-brask coreboot. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: Ia9088cc2937bab72c8c22af592392384a10616a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ricky Chang <rickytlchang@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 06:55:04 +0000