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2023-11-02Revert "soc/intel/{tigerlake,meteorlake}: Check ITBT FW version"Ravi Sarawadi
This reverts commit 2e10a6d6f3ec46bcaf75bd066319d51f001be764. Reason for revert: The FW version check is not supported except for ADL platform. Reverted change broke S0ix functionality; the original CL was added as HW W/A for ADL ONLY. BUG=b:306214725 TEST=S0ix cycles on Rex with TBT Device attached. Change-Id: Ib8eb11d36eac4e1c94a3349386442fa3eeeaef37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02util/docker: Add libnss3-dev package to coreboot-sdk for vbootMartin Roth
The latest updates to Vboot use libnss, so add the library to the coreboot sdk. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iee0c44296b189b5327ef8f950b1bba9eb668f298 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78867 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-02util/crossgcc/buildgcc: Fix detection of GNAT on recent versionsFelix Singer
gnatgcc is deprecated and in recent GCC releases its purpose is fulfilled by the gcc binary. In case of a deprecated gnatgcc version is installed, it doesn't provide the expected output and hostcc_has_gnat1() fails. In this case, just set the value of CC to gcc. It's still required to install GNAT in addition to GCC. Change-Id: I730bdfda81268d10bd2a41ef5cb4e3810b76a42c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-02Documentation: order distributions alphabeticallyMarkus Meissner
Change-Id: I95d4347791988087d90992b45120ff34ba2da1c5 Signed-off-by: Markus Meissner <coder@safemailbox.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78864 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02soc/amd/*: Ensure PSP soft fuse bitmask set properlyMatt DeVillier
Commit e728766f4596 ("soc/amd/mendocino: Do not load MP2 Firmware when in RO") added logic to ensure that the MP2 disable soft fuse bit was set for the RO section, but failed to check if the bit was already set otherwise (as it is for non-ChromeOS builds). This caused the bit to appear twice in the PSP_RO_SOFTFUSE_BITS string, and when the string was converted to a series of numeric values and added together, bit (n+1) ended up being set instead of bit n. To mitigate this, use the makefile sort() function to ensure the PSP_[RO_]SOFTFUSE_BITS string does not contain any duplicates before the bitmask is calculated. Apply this to all AMD SoC makefiles where the softfuse bits are added. TEST=build/boot google/skyrim (frostflow). Use a verbose build (V=1) to verify that the correct soft fuse value is passed to amdfwtool for RO and RW_A/B for both ChromeOS and non-ChromeOS builds. Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78823 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-11-02mb/google/brya/var/omnigul: Add fingerprint SPIJamie Chen
Add fingerprint SPI, and power off FPMCU during romstage. BUG=b:305860604, b:306320063 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, measure evtest can detect and check device probed in kernel log Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-02mb/google/guybrush: Set PS2K_IRQ to level/lowMark Hasemeyer
On guybrush, keyboard presses are signaled by the EC via eSPI virtual wire. The interrupt is shared with others and should be active low. From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"): > The default state for the IRQ lines when the eSPI controller comes > out of reset is high. This is because the IRQ lines are shared with > the other IRQ sources using AND gates. This means that in order to > not cause any spurious interrupts or miss any interrupts, the > IO-APIC must use a low polarity trigger. Setting `vw_irq_polarity` in the device tree provides an option to invert interrupts from the eSPI controller, but the register is initialized from verstage which is baked into RO. As a workaround, the necessary interrupts on the EC have been reconfigured to be active low, and we can modify the IO-APIC accordingly. EC related CL here: https://crrev.com/c/4891663 BUG=b:218874489 TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage` -Flash new RW fw and verify keyboard is functional -`suspend_stress_test -c 1` and verify i8042 irq is removed as a wake source -`echo mem > /sys/power/state`. Press key and verify system wake from i8042. Cq-Depend: chromium:4891663 Change-Id: I7d093d94a666263684645ef724e945069c68c806 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-11-02drivers/intel/gma/opregion: Use CBFS cache to load VBTJeremy Compostella
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-02commonlib/fsp_relocate: Fix potential NULL pointer dereferenceJeremy Compostella
Commit 1df1cf994aa9 ("commonlib/fsp_relocate: add PE32 section support") introduced a potential NULL pointer dereference if there is PE32 binary to relocate outside of the first firmware volume. The `fih_offset' pointer was used as an output variable but now it is also used as an input variable to pass the FSP information header to the `pe_relocate()' function. This commit resolves this potential NULL-pointer dereference by passing the pointer systematically and without affecting the logic as it is only set if it has not been set before. Change-Id: I9fad90a60854d5f050aa044a5c0b3af91c99df4a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78501 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02soc/amd/mendocino: Update FSP-S UPD to pass boot logoKarthikeyan Ramasubramanian
A new FSP-S UPD is added to allow passing a buffer containing boot logo in BMP format. Update the FSP-S UPD and add a SoC specific callback to populate the UPD. BUG=b:294055390 TEST=Build and boot to OS in Skyrim. Pass the BMP logo buffer through the UPD to FSP-S. Ensure that the concerned driver in FSP-S handles the buffer. Change-Id: Ie522956b6dfe2400ef91d43c80f2adc6d52c8415 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78817 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02soc/amd/common/psp: Remove unnecessary prompts from KconfigMartin Roth
I think this was probably a cut & paste error. We don't want prompts for the "default" Kconfig options. Those should be set by the platform, not the end user. These prompts didn't make sense where they were in the Kconfig menus either. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Idcd2ba84591d31a9a25bcc6cae3ec163939d7836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-02soc/intel/*: Correct ACPI device name for eMMCMatt DeVillier
The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-01soc/intel/cmn/gfx: Fix GFX modeset issue with dual-displaySubrata Banik
This patch fixes the redundent GFX modeset issue when a dual display is attached (e.g. an eDP display and an HDMI display). The issue was caused by the MBUS joining logic not considering the display type. This patch introduces three types of display: internal, external, and dual-display. The MBUS joining logic is then updated to consider the display type and ensure that the correct pipes are joined to the MBUS: For internal-only displays, only PIPE-A is joined to the MBUS. For external displays, no pipes are joined to the MBUS. For dual-displays, all available pipes are joined to the MBUS. BUG=b:284799726 TEST=Able to fix the redundent modeset issue when eDP and HDMI attached to the google/rex. Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78691 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01arch/x86/memcpy.c: Optimize code for 64bitArthur Heymans
In 64bit movsq is available which moves memory in chunks of 8 bytes rather than 4 bytes. Linux uses the same code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I65f178d2ed3aae54b0c1ce739c2b4af8738b9fcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/78646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-01mb/google/hatch: Change WiFi device type from PCI to genericMatt DeVillier
Change the WiFi device type to generic, so that the LPI constraint generator does not create a reference for a device which does not exist in ACPI (SB.PCI0.RP14.MCHC). The invalid reference causes a Windows BSOD. TEST=build/boot Win11 on google/hatch (akemi) Change-Id: Ieab0722a81f0952bb5b6df8e60c4d684ff455418 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78543 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01soc/intel/meteorlake: Adjust Power State Current 2 thresholdJeremy Compostella
VccSA Power State 2 (PS2) current threshold has be adjusted to 10A to improve PS2 residency which reduces Voltage Regular (VR) power loss. BUG=b:308002192 TEST=power and performance analysis shows a positive Load Line result Change-Id: I2da2b05de8a04f91dacaa55062165c4351422865 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-01drivers/generic/adau7002: Set ACPI status to hiddenMatt DeVillier
No driver available or needed under Windows, so hide from OS. TEST=build/boot Win11 on google/kahlee (liara), verify ADAU7002 device no longer listed as unknown under Device Manager. Boot Linux and verify audio still functional. Change-Id: If6d250a123825a69441b5c4d3cde35d5a68f568d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78510 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01mb/{google,intel}: Update FMD to support CBFS verificationAnil Kumar
This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed for boards that currently use them. BUG=b:284382452 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-01mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBIYu-Ping Wu
Enable FW_CONFIG for geralt so that the information can be passed to payloads via coreboot tables. BUG=b:157692450 TEST=emerge-geralt coreboot BRANCH=none Change-Id: I8898143f44d2ffda3cb1708c2d7efadc289303a1 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-01util/lint: Fix some mistakes in spelling.txtJulius Werner
Somehow two words slipped in here where the "bad" and "good" spellings are the same, which doesn't make sense. Remove them. Change-Id: I9b53ce8538616c164efb4eb25ff859975ddadfd2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78822 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-01mb/google/brya/var/quandiso: Add VBT data fileRobert Chen
Add data.vbt file for quandiso recovery image. Select INTEL_GMA_HAVE_VBT for quandiso as it has a VBT file now. The VBT file is copied from chromeos internal source and based on yaviks VBT. BUG=b:296506936 TEST=emerge-nissa coreboot Change-Id: Ia9f84b4f56171737a9e7a513b63549b3013775c4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77588 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2023-11-01mb/google/nissa: Add AUDIO_CONFIG in fw_configRen Kuo
The codec alc5650 has different setting from other amp codec in depthcharge. Since nissa has a single shared depthcharge target, add the fw_config field to allow different audio_configs. (refer to chromium:4983866) BUG=b:307410704 TEST=With depthcharge change, set fw_config and gbb flags on craaskana and check beep sound on firmware screen is workable. Change-Id: I7446fce57557204d91151f1a31755381c1813c6f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78791 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01Documentation: add Nitrokey to distributionsMarkus Meissner
Nitrokey offers various products, which have coreboot pre-installed. Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a Signed-off-by: Markus Meissner <coder@safemailbox.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78299 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01mb/google/rex/var/rex0: Toggle NVMe PWR pin to reset SSDWonkyu Kim
During warm reboot, NVMe is not detected with non-serial image sometimes while there is no issue with serial image. This change toggles NVMe PWR pin as soon as in early stage to make NVMe ready sooner. BUG=b:260547988 BRANCH=None TEST= Build rex0 and try warm reboot from OS console. Check if the platform with Micron SSD boots to OS again without an issue. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I2f34e3f49e7fc388198ff85c8e119cb3f242a60e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-01mb/google/rex: Avoid hang for pre-prod SoC by setting SAGV_POINTS_0_1_2Subrata Banik
Intel has identified an idle hang issue on pre-prod silicon that will not be fixed or root-caused. To avoid the issue, this commit sets SaGvWpMask to SAGV_POINTS_0_1_2 in the devicetree. Note: This change will affect system power. BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang on google/screebo. Change-Id: Id0b8db0076d983d336c3bec6d6c33614c69964d1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78794 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKUCurtis Chen
This commit adds power limit settings for 4+8 28W SOC sku and renames MTL_P_682_CORE to MTL_P_682_482_CORE since they are sharing same 28W settings. BUG=b:306677879 TEST=boot on rex with 4+8 SOC and power limit settings are correct Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78796 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01Revert "vboot: Add catchall recovery reason for unspecified phase 4 errors"Martin L Roth
This reverts commit 7499d9610016c4a89b722498885f196ed6d217aa. Reason for revert: coreboot build fails Change-Id: I8ef853d81ee9b1f18d36dfd82cdf687381ece2c6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78845 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-01Revert "Update vboot submodule to upstream main"Martin L Roth
This reverts commit 6e03007bfa948d679f5d4d6998c12c581b390d1a. Reason for revert: Build fails - Jenkins test escappe. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78844 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-10-31vboot: Add catchall recovery reason for unspecified phase 4 errorsJulius Werner
The code for "phase 4" of firmware verification currently only sets a recovery reason when there's an actual hash mismatch detected in vb2api_check_hash_get_digest(). This is the most likely way how this section of code can fail but not the only one. If any other unexpected issue occurs, we should still set a recovery reason rather than just reboot and risk an infinite boot loop. This patch adds a catchall recovery reason for any error code that falls out of this block of code. If a more specific recovery reason had already been set beforehand, we'll continue to use that -- if not, we'll set VB2_RECOVERY_FW_GET_FW_BODY. Change-Id: If00f8f8a5d17aa113e0325aad58d367f244aca49 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78821 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31Update vboot submodule to upstream mainJulius Werner
Updating from commit id 24cb127a: 2023-08-21 Nicholas Bishop sign_uefi_unittest.py: Fix long-line lint to commit id f2b01bf0: 2023-10-27 Julius Werner firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY This brings in 47 new commits: f2b01bf0 firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY ef6d02df futility/vb2_helper: Add missing newline for error messages 886d13d7 PRESUBMIT: switch to cros format ac2e1a75 host/lib: Decouple openssl headers from HOSTLIB 86ec05f7 futility: updater: Add help info for --quirks 2850244e futility: updater: Abort if the unlock_csme_* is used on a locked device f1b5c88d devkeys: delete old unused firmware_bmpfv.bin 4444c5fe crossystem: Fix tpm_fwver for fwid < 12935 98ef339f 2lib: Prevent overwriting the value of fw_vboot2 c7517eb4 make_dev_ssd: support ChromeOS Kdump 8e3462cc tlcl: Increase the TPM_BUFFER_SIZE 740a2966 vboot_reference: Drop 'host' usage for 'internal' in flashrom.h 57877a44 vboot: Remove comments about physical dev switch 3401d16c 2lib: Fix typos, comments and formats fdf52d45 scripts/: Drop deprecated {g,s}et_gbb_flags.sh scripts bf76e9ee 2lib: Output the correct kernel_version 1ac4663e make_dev_firmware.sh: update pattern for matching wp status c57ab9f7 2lib: Add recovery reason VB2_RECOVERY_WIDEVINE_PREPARE e094ba31 tlcl: Reduce the variants of TPM2B b047600d sign_official_build: support key config for pkcs11 f8712b73 vboot: support signing with pkcs11 private key 17fe786f strip_boot_from_image.sh: sfill fast 6c856cd3 futility/updater: Fix EC software write protection logic 1dc5a421 futility: update: Deprecate --unlock_me by --quirk unlock_csme_nissa f0d88587 futility: update: Refactor the 'unlock ME' quirk(s) 81429ee9 futility: update: Do not update RO when the AP RO is locked a3beb737 futility: update: Revise the ordering or quirks 2c1844fa futility: update: Remove unused quirk 'unlock_wilco_me_for_update' 75530d32 tests/futility: Test with new signer_config.csv based firmware updater cba649fa 2lib: Expose 2hmac ab015448 2lib: Refactor hmac to vb2_hmac_calculate 3545f8b4 Revert "sign_uefi: Remove exception catching" 55f625a9 dump_fmap: Add offset and size to flash_ec format output a27ee336 keygeneration: add shellcheck source statements to help linting 055f9aa2 keygeneration: replace_recovery_key.sh: make minios key optional 6cb8ab60 scripts: delete unused values kernel command line 1f76c38b vboot: Drop phone recovery support ccf6b037 scripts: Legacy fix for set_gbb_flags.sh 8f03069e futility: Add basic README.md 88963df8 utility: Query platform wp status with futility 6c3817d2 utility: Drop cros_alias technical debt in dev_debug_vboot df85f512 scripts: Drop cros_alias technical debt in make_dev_firmware.sh 7395cd68 futility/updater_utils.c: Match on EC path to prepare for split 52518415 crossystem: Recover corrupted RW_NVRAM on flash writes 81f9ddaf futility/cmd_gbb_utility.md: Add basic GBB subcmd doc c4995268 futility/: Fix define confusion 69dab5a6 crossystem: Avoid writing duplicate entries to RW_NVRAM 6c37b520 Revert "crossystem: stop supporting legacy chromeos_acpi driver" Change-Id: Ic7ecd1755d26df349b8abf1c5a77c806facfe1d8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78820 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-31util/kconfig: fix 0009-util-kconfig... patchRichard Marko
This was reverted via commit 9ab3a1fe4a1d and causes unapply to fail so we adjust the patch to preserve the original return value. Change-Id: I5ad2180854e0263d2d097b059cb16ec478b859c5 Signed-off-by: Richard Marko <srk@48.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78442 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31util/kconfig: Fix README.md formattingRichard Marko
Change-Id: I0c47a603cc6e6174cd4895ff9f44b5bc242c653e Signed-off-by: Richard Marko <srk@48.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78441 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31util/kconfig: add savedefconfig patch to quiltRichard Marko
Adds commit 48ad5c23680c util/kconfig: chmod +w before savedefconfig to quilt patch series. Change-Id: I381dce2fee995227efc60169fd90ab505c99b74b Signed-off-by: Richard Marko <srk@48.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78440 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31util/kconfig: chmod +w before savedefconfigRichard Marko
This prevents a headscratcher when .config in root doesn't have a write permission bit set which causes a build failure of savedefconfig not able to write to copied file, for example *** Error while saving defconfig to: build/mainboard/emulation/qemu-i440fx/cbfs-file.eU5E0t.out.tmp2 Change-Id: I2e7d35c9f6e8add3e7438d163850bc5fda5a99b2 Signed-off-by: Richard Marko <srk@48.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-10-31mb/google/brya/var/*: Mark fingerprint reader as hiddenMatt DeVillier
Windows doesn't have / will likely never have a signed driver for the FPR, so set the device status as hidden so it will not appear as an unknown device in Windows Device Manager. Linux does not check/care about the ACPI device status. TEST=build/boot Win11 on google/brya (kano), verify FPR does not show up as unknown device under Device Manager. Change-Id: Ie73fd9d448ecca9e9112abc0d92b4ab46ce3618d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-31mb/google/hatch/var/*: Mark fingerprint reader as hiddenMatt DeVillier
Windows doesn't have / will likely never have a signed driver for the FPR, so set the device status as hidden so it will not appear as an unknown device in Windows Device Manager. Linux does not check/care about the ACPI device status. TEST=build/boot Win11 on google/hatch (jinlon), verify FPR does not show up as unknown device under Device Manager. Change-Id: Ia4a908afdabad0ae8db45c4731a00c9cb17b42bb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-31soc/intel/cannonlake: Implement SoC sleep state arrayMatt DeVillier
Adapted from Alderlake implementation, modified as needed. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/hatch (akemi). Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-31soc/intel/tigerlake: Implement SoC sleep state arrayMatt DeVillier
Copied from Alderlake implementation, modified as needed for Tigerlake. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/volteer (drobit). Change-Id: I34999891ea0d386328698109b6315d481de7c43a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78521 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-31mb/amd/onyx: Include soc.asl fileVarshit Pandya
This patch includes the soc.asl from Genoa (SoC) folder, which in-turn includes pci_int_def.asl Change-Id: Id7a3b9c752546638f7b446510e17c44e9f10106d Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78496 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31soc/amd/genoa: Add PCI interrupt supportVarshit Pandya
This patch adds PCI interrupt details as per the Processor Programming Reference (PPR) version 0.25 (#55901), table 319. Change-Id: I81251bd60aac1d7bd3181699d3adca315291f336 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78392 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31mb/google/rex/var/screebo: Disable FVMSubrata Banik
This patch disables FVM for IA and SA VRs as per the OEM requirement. BUG=b:307237761 TEST=Able to build and boot google/screebo. Change-Id: Icb0611331ac7090d11d646a5ad5201593a90aacb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-31mb/google/rex/var/screebo: Set Baseline Power LimitSubrata Banik
This patch allows google/rex mainboard to choose between "Performance" (PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs). This is important for platform to meet balance between power and performance. The OEM design google/screebo selects baseline power limit to maintain the balance performance in lower power. BUG=b:307237761 TEST=Able to build and boot google/screebo. w/o this patch: screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL" [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 57 Watts [INFO ] CPU PL4 = 114 Watts w/ this patch: screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL" [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 40 Watts [INFO ] CPU PL4 = 84 Watts Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-30Documentation: Update 4.22 release notes with x86 CBFS cache supportJeremy Compostella
Change-Id: I7c9ecdc3f8316fdec0bc1bc188f1959fb8b5a458 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78655 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30MAINTAINERS: Spell Jérémy’s name with accentsPaul Menzel
Change-Id: I4c025bbcb205fa5bd3dcb35c685a3db289a3f824 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78803 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30mb/system76/adl/dt: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the device scope of them. While on it, remove superfluous comments related to modified lines. Change-Id: I2f641ce1fc44a9d7c9f9c403d255997214021f47 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-10-30mb/system76/rpl/dt: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the device scope of them. While on it, remove superfluous comments related to modified lines. Change-Id: I15f326774850b3c9562f7eebb78f29430dec1031 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78667 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30mb/system76/{tgl,skl}/dt: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the device scope of them. While on it, remove superfluous comments related to modified lines. Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30mb/system76/cannonlake/dt: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the device scope of them. While on it, remove superfluous comments related to modified lines. Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30mb/google/hatch/var/palkia: Use chipset devicetree referencesMatt DeVillier
Switch palkia overridetree to use chipset devicetree references. Change-Id: Ic5fd2d139d22824d3ada09325022c37e69b5e2a9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30mb/google/hatch/var/nightfury: Use chipset devicetree referencesMatt DeVillier
Switch nightfury overridetree to use chipset devicetree references. Drop USB port overrides which are identical to the baseboard. Change-Id: I9bb028ad12b97fd4510f6d1026fdc16232c64dba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78570 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30mb/google/hatch/var/mushu: Use chipset devicetree referencesMatt DeVillier
Switch mushu overridetree to use chipset devicetree references. Change-Id: Iac05b0b2c5785f2cb69a29aa4d4c3088f164385f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30mb/google/hatch/var/kohaku: Use chipset devicetree referencesMatt DeVillier
Switch kohaku overridetree to use chipset devicetree references. Drop USB port overrides which are identical to the baseboard. Change-Id: Idcfde6882fc433e6a248aff6baf23b1a5bf7d201 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30mb/google/corsola: Add new board 'Chinchou'wuyang5
Add a new Krabby follower 'Chinchou'. BUG=b:307161347 TEST=make # select Chinchou Change-Id: Ic90f85621598ab253d3ec9fe44aa076712248223 Signed-off-by: wuyang5 <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78596 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-29cbfstool: Fix CBFS header buffer overflowJeremy Compostella
In the unlikely but possible event where the name of the CBFS file is longer than 232 characters, `cbfs_create_file_header()' would overflow the buffer it allocated when it copies the CBFS filename. Change-Id: If1825b5af21f7a20ce2a7ccb2d45b195c2fb67b0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-29mb/google/brya/variants/craask: Enable DDR RFIM Policy for CraaskSumeet Pawnikar
DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Craask variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=None BRANCH=None TEST=Build and boot Craask. - Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I5560bbedb26e88edd9d35f16b639fe63ef42c30e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-29mb/lenovo/t430: Disable SuperSpeed capabilities for WWAN USBBill XIE
Just as in commit 38569d061099: ("mb/lenovo/{x230, x230s}: Disable SuperSpeed capabilities for WWAN USB") Although on ThinkPads with Panther Point PCH the usb port inside wwan socket is usually wired to XHCI, it has actually no SuperSpeed lines, so maybe it is okay to disable SuperSpeed capabilities, and wire them to EHCI #2 by making use of XUSB2PRM and USB3PRM. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I61e61283a821686558f7f3fdfac7073bb3557e93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78680 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28payloads/LinuxBoot: Add uImage to clean targetArthur Heymans
uImages are generated for non-x86 arch. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Icb1184497087d66a7cc6fd27402365a028cc4eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-10-28soc/intel/meteorlake: Expose In-Band ECC UPD config to mainboardMarx Wang
Meteor Lake has a UPD config called In-Band ECC(IBECC) which uses a part of the system DRAM to store the ECC information. There are a few UPD parameters in FSP-M to configure this feature as needed. This patch adds code to expose these parameters to the devicetree so that they can be configured on the mainboard level as needed. Change-Id: Ice1ede430d36dff4175a92941ee85cc933fa56d5 Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header fileJeremy Compostella
Export Power State Current 1, 2 and 3 Threshold configuration entries. BUG=b:308002192 Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-28mb/google/rex: add dptf settings for 2+4 SOC SKUKane Chen
This patches privides settings based on 2+8 15w. BUG=b:306543967 TEST=boot on rex with 2+4 SOC and power limit settings are overridden correctly in variant_update_cpu_power_limits Change-Id: I0560e44ce8e0d91bb5fb9c7cc9ffe68ab050bf00 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78688 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-28soc/intel/meteoerlake: Add power limits for 2+4 15W SOC SKUKane Chen
This commit adds power limit settings for 2+4 15w SOC sku and renames MTL_P_282_CORE to MTL_P_282_242_CORE since they are sharing same 15w settings. BUG=b:306543967 TEST=boot on rex with 2+4 SOC and power limit settings are correct Change-Id: Id738303d1652f964142f8f27110426d6b84609bf Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78495 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28mb/google/rex/var/rex0: Configure EN_WWAN_PWR GPIO based on CBIJeremy Compostella
GPP_B17 (aka. EN_WWAN_PWR) should be kept low when the device does not have a WWAN module. TEST=Power consumption drops to 0 in S0iX Change-Id: I95150c20c98b037a47827a7b83e4373c6e9070e3 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78684 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-28mb/google/brya/var/dochi: Update overridetree for touchscreenMorris Hsu
Update overridetree for ILI2901 and eKTH7B18U touchscreen. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: Ib45f3c7c92ea525ca13a6137dd87eeb318f30384 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2023-10-28util/cbfstool: Enable "ms-extensions" compiler flag on mingw onlyPatrick Georgi
The flag activates some Win32 compatibility quirks and on clang/openbsd it enables so many of them that the code doesn't compile anymore. Therefore move it into the "Win32 area" in that Makefile. Change-Id: Ic77c04941e40a568f1d74cec09eb3d22a66e69b0 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78724 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28mb/{sm/x11,razor,libretrend}/dt: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they will be moved into the devicetree to their related root ports at some later point. While on it, remove superfluous comments related to modified lines. Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28mb/google/zork: Clean up Kconfig entriesMatt DeVillier
Alphabetize board entries, Kconfig selections, and config options. Change-Id: I94e6e584809888fc9cab1b4cff6c0368803c1d47 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-10-28mb/google/zork/Kconfig.name: Alphabetize board entriesMatt DeVillier
Change-Id: I6843fd2eb752cd35d8c67ad7487f6dbb1c1afc62 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78707 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-10-28mb/google/guybrush: Clean up Kconfig entriesMatt DeVillier
Alphabetize board entries, Kconfig selections, and config options. Change-Id: I599eda8c136d072471f022be9397faeb0e061472 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78706 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28mb/google/guybrush/Kconfig.name: Alphabetize entries, add namesMatt DeVillier
Alphabetize entries and add consumer product names for boards where available. Change-Id: I22a18ba85d6ff203765f984fba51784757a2a4df Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78705 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28mb/google/skyrim: Clean up Kconfig entriesMatt DeVillier
Alphabetize board entries, Kconfig selections, and config options. Reverse default logic of PERFORM_SPL_FUSING for simplicity / clarity. Change-Id: Ib25bb8c7bbf994f2f0675c4599c70a7db5d9f7ef Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-28mb/google/skyrim/Kconfig.name: Alphabetize entries, add namesMatt DeVillier
Alphabetize entries and add consumer product names for boards where available. Change-Id: I7459ee0a63025c12c7dbe75c578c7496c49fa475 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-28doc/lib/flashmap: Fix incorrect path to FMD implementationNicholas Sudsgaard
Change-Id: I6864cd041d7173cd284f47d09f4388341a7ee756 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78690 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28mb/google/{rex, ovis}: Introduce devicetree.cb for pre-prod SoCSubrata Banik
This patch introduces a dedicated devicetree.cb file for platforms built with pre-production SoC. This will help to keep the SoC configuration separate for platforms with ESx and QSx silicons. For example, the SaGv WP configuration is different between pre-production (aka ESx) and production (aka QSx) silicon. BUG=b:306267652 TEST=Able to build and boot google/rex4es. Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
2023-10-27mb/google/hatch/var/*: Disable unused device in SerialIO cfgMatt DeVillier
For variants without a digitizer, disable I2C2. For variants without a proximity sensor, disable I2C3. For variants without a fingerprint reader, disable SPI1. For all variants, disable I2C5 as it is unused. Adjust comment blocks as needed. Change-Id: I27e9eb2b0dcc869d1964c0b17c656d6691c0f05e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78553 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27mb/google/hatch/var/jinlon: Use chipset devicetree referencesMatt DeVillier
Switch jinlon overridetree to use chipset devicetree references. Change-Id: I663a1d051d287f8484c5d4d175337f4f24081044 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-27mb/google/hatch/var/kindred: Use chipset devicetree referencesMatt DeVillier
Switch kindred overridetree to use chipset devicetree references. Change-Id: I2c54406948d2db53d25aa7c3dc79cfb5661c4a69 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78564 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27mb/google/nissa/var/joxer: Override tdp pl1 value for DTT tuningMark Hsieh
Follow thermal validation, override tdp pl1 in 6w ADL_N platform to 10w and override tdp pl1 in 15w ADL_N platform to 20w. BUG=b:307365403 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I8dd743e65b9e5fbd6aa2fd9c1b87c7bd487c8174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78650 Reviewed-by: ChiaLing <chia-ling.hou@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2023-10-27security/intel/stm: Remove check that can never be trueMartin Roth
STM_RSC_MEM_DESC defines rws_attributes as 3 bits, which can't be greater than 7. Found-by: Coverity Scan #1430578 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1efd007e96abd6d5d36f314752abfadffb0024d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-27mb/intel/skylake/devicetree: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they will be moved into the devicetree to their related root ports at some later point. While on it, remove superfluous comments related to modified lines. Change-Id: I769233a5baabbea920c9085f8008071ba34bb9dd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78598 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27Kconfig: Add vendorcode debugMartin Roth
This includes Kconfig.debug files under vendorcode into the debugging menu. Currently it's being added to pull vc/amd/opensil/Kconfig.debug in. Change-Id: Ie7c8235354ea5a0b156dcbb147d35c157fbd14da Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-27soc/amd/genoa: add PCI domain resource reportingFelix Held
Use the common AMD data fabric resource reporting code to report how openSIL distributed PCI buses, MMIO, and IO resources to coreboot's resource allocator. This replaces the original CB:76521 which was written back when the common AMD data fabric resource reporting code didn't exist yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ifcd655ea6d5565668ffee36d0d022b2b711c0b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-10-27soc/amd/genoa: select PSP gen 2 supportFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iffe21fb0c0bff0fc21ce1ac3af71d39bb62fd384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78660 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27mb/google/rex: Update FMD to support CBFS verificationAnil Kumar
This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. These blobs were kept separate originally to avoid hash loading and verification every time and hence save boot time. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed. BUG=b:284382452 TEST=Build CB image for google/rex board and test CSE FW update/downgrade with CONFIG_VBOOT_CBFS_INTEGRATION config enabled. Also confirm there is no increase in boot time with this change. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I56865a9e5c8b5f9e908e00e1a7e7e187d5d6a2f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-27soc/intel/cse: remove cbfs_unverified_area_map() API in cse_liteRizwan Qureshi
With CBFS verification feature (CONFIG_VBOOT_CBFS_INTEGRATION) being enabled, we can now remove cbfs_unverified_area_map() APIs which are potential cause of security issues as they skip verification. These APIs were used earlier to skip verification and hence save boot time. With CBFS verification enabled, the files are verified only when being loaded so we can now use cbfs_cbmem_alloc()/cbfs_map function to load them. BUG=b:284382452 Change-Id: Ie0266e50463926b8d377825142afda7f44754eb7 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78214 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-10-26mb/google/brox: Add Arbitrage generated gpio.c fileShelley Chen
Checking in gpio.c generated by arbitrage. Used this command line to generate: arb export-coreboot-gpio --refdes=U1 brox:proto1_20231017 BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I1098bd4cfde393ed9e78cd90158c3534fdf0dc09 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78657 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26mb/google/brox: use Alderlake-P SoC instead of Alderlake-SShelley Chen
Skolas is actually using the SOC_INTEL_ALDERLAKE_PCH_P config, so fixing Brox to reflect this as it's using the same SoC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I632ec055d523956983d2053cd8e7000b1eaabf92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78656 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26mb/prodrive/hermes: Rework UART devicetree entryMatt DeVillier
Rework the UART devicetree entry so that it doesn't conflict with the to-be-added chipset devicetree for CNL. This should be functionally equivalent to the previous entry, but needs testing to verify. Change-Id: Iae60cb8e0746e7dc2928da3687762b81928fb5f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78546 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-26mb/google/hatch/baseboard: Use chipset devicetree referencesMatt DeVillier
Switch baseboard devicetree to use chipset devicetree references. Drop any devices whose status (on/off/hidden) matches the default in the chipset DT. TEST=build/boot google/hatch (akemi) Change-Id: I5954c304f3c0e04be7e061c1c23a278f81b6ff4d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-26soc/intel/cannonlake: Add/use chipset devicetreesMatt DeVillier
Change-Id: I8ceae832e60cd3094b4a34ab3a279e5a011f2c80 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-26mb/google/hatch/var/helios_diskswap: Use chipset devicetree referencesMatt DeVillier
Switch helios_diskswap overridetree to use chipset devicetree references. Change-Id: I0a3385139c74a59c2006b8963850d00ee39f70a8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78560 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/hatch/var/helios: Use chipset devicetree referencesMatt DeVillier
Switch helios overridetree to use chipset devicetree references. Change-Id: If7901066a0c77231779eb298dc40962d8ac62814 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/hatch/var/hatch: Use chipset devicetree referencesMatt DeVillier
Switch hatch overridetree to use chipset devicetree references. Change-Id: Icccb433ba3e5a1ecb192f8db830674047e801623 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/hatch/var/dratini: Use chipset devicetree referencesMatt DeVillier
Switch dratini overridetree to use chipset devicetree references. Change-Id: I9f365077291ee9fa5f4dcf8835756f4cfd6eeab4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/hatch/var/akemi: Use chipset devicetree referencesMatt DeVillier
Switch akemi overridetree to use chipset devicetree references. Drop USB port overrides which are identical to the baseboard. TEST=build/boot google/hatch (akemi) Change-Id: Ic25fbe4a634f8166047107a33c9fcee764f1159a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78552 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26drivers/intel/gma/Kconfig: Add VBT compression configuration entryJeremy Compostella
Introduce Kconfig choice to pick between lzma, lz4 and no compression at all of the VBT binary. If VBT is needed in romstage, it can be used to set VBT lz4 compression as an alternative to enabling lzma compression support. Indeed, the extra lzma code needed to de-compress VBT undermines the compression size reduction between lzma and lz4. BUG=b:279173035 TEST=Verified that vbt.bin is lz4 compressed with VBT_CBFS_COMPRESSION_LZ4 and not compressed at all with VBT_CBFS_COMPRESSION_NONE Change-Id: I1df6a96c2ec122f0ef8ee6a1e96ffbd621b14941 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/starlabs/*/Kconfig: Fix default power state after failureMatt DeVillier
POWER_STATE_OFF_AFTER_FAILURE can't be directly selected since it's a choice, so instead set POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n, as it's functionally equivalent. This fixes the warnings generated by the pre-commit hook Kconfig check. It is necessary to override and set default n in the mainboard Kconfig as it is set to default y in src/soc/intel/common/block/pmc/Kconfig. TEST=select starlabs/starbook_adl in menuconfig and verify the default power-on setting is S5/soft off. Change-Id: I3ce33517dcc0af693b8db8d1de2926117ad3c16b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78627 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/zork: Add FP enable for MorphiusJon Murphy
Add FP enable/disable based on SKU ID for Morphius. This is meant to resolve a UMA issue with Morphius devices that had the FPMCU populated on non-fp devices. Since the FPMCU is present, and the firmware enables the power GPIO's based on variant, not SKU, the devices were reporting data on fingerprint errantly. BUG=b:258040377 TEST=Flash to Morphius, test FP. Disable test SKU, flash on Morphius, test FP. Change-Id: If5794a9a1b7eb3daaa4cdfd1354dfb0c688624fd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78622 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-26Add Intel maintainers for x86, soc/intel, FSP, ACPIHannah Williams
Change-Id: I67bf98ee7661b031be6d1d77a4db8d816c4a6a0b Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78272 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-26soc/intel/apollolake: Select USE_LEGACY_8254_TIMERSean Rhodes
CB:77409 corrected what the UPD `Timer8254ClkSetting` was set to; this stopped a few boards from booting. Selecting USE_LEGACY_8254_TIMER ensures that the previous behaviour is maintained. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibf898cae6c9fbaf3dc7184eee745278d9b5eade4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78504 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25arch/arm64/cache: Implement helpers to obtain CPU cache detailsBenjamin Doron
This is required for compliant ACPI/SMBIOS implementations on AArch64, and can optionally be displayed to the user. Change-Id: I7022fc3c0035208bc3fdc716fc33f6b78d8e74fc Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>