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2024-01-15sb/intel/bd82x6x/early_usb: Add USB TX/RX gainsPatrick Rudolph
Describe the USB 'current' settings based on MRC.bin that converts the USB trace length to a predefined register value. MRC.bin decides which setting to use based on the PC type, mobile or desktop, and the trace length. Tested: Lenovo X220 still boots. Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-15util/autoport: Improve USB codePatrick Rudolph
Currently autoport fills in USB current '0' if the detected setting isn't one of the known settings. This works as 0 is a valid setting from C point of view, but it's not supported on desktop PCs and on mobile platform results in the lowest possible USB PHY gain. Thus this might cause instabilities as the original firmware had stronger USB drive currents and gain settings. Add more known USB current fields to the map and generate a FIXME as comment when the detected current isn't one of the known entries instead of defaulting to 0. Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78828 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-15sb/intel/bd82x6x/early_usb: Print error for invalid USB settingPatrick Rudolph
According to BWG the USB current setting 0 should not be used for desktop boards. As autoport defaults to 0 if the USB current doesn't match one of the lookup table entries most of the desktop boards in tree have such a setting. Print an error to alert users of such boards to update the USB current settings. Tested: Lenovo X220 still boots. Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78827 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/lenovo/x230: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I38ef315dbdadb140e8e7163e755a078bc906e1b5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t430: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ib94dd2778cf89ae8b97b43031d729c728f59a29e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t530: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ied9f37355432d58f83cb8453111a261c4eddc14a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/x220: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/x220 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/x220: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ife8f3bc8b7fd14bb9a0e8dd4bc3d33b44c8f794f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asrock/b75m-itx: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-by: Janik Haag Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/h61-series: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from asus/h61_series are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I1ba2cb08e60cf806c5d749be15265e577a7abc25 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/h61-series: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I8008fcc994e49c1626fd366c74661fcceb21a323 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/maximus_iv_gene-z: Remove superfluous comments from dtFelix Singer
Since all devicetrees from asus/maximus_iv_gene-z are using the reference names for PCI devices, remove the equivalent comments documenting their function. Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/p8x7x-series: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79967 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/lenovo/t520: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t520 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I307dbf7a7d6fc9086e868d8315ba7a66b94a24e7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t520: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I18ce899516fd38b21ded1e3144aa22e705c534b8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79965 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14sb/intel: Use boolean for pcie_hotplug_map attributeFelix Singer
Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79932 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14libpayload: Make sure to install into the right DESTDIRNico Huber
A recent update broke installation of commonlib headers with a relative path in $(DESTDIR), which is the default. Make sure to install into the right location in case we changed the current directory. Change-Id: I61fa4aa0ecd0f81ee03ff89183e1b65e7875dea6 Signed-off-by: Nico Huber <nico.h@gmx.de> Fixes: ee53dfd07d3b (libpayload: Remove shell for loops in install Makefile target) Reviewed-on: https://review.coreboot.org/c/coreboot/+/79908 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14drivers/mipi: Update init code for BOE_NV110WUM_L60Ruihai Zhou
1. Correct bank1 to bank0 2. Adjust CLK duty 3. Fix abnormal power off setting 4. Change VDDE power off frame from VGL to VGH Fixes: 0d50536("drivers/mipi: Add support for BOE_NV110WUM_L60 panel") BUG=b:319398058 TEST=boot Ciri with BOE_NV110WUM_L60 and see firmware screen Change-Id: I2f068ba0ec9dede3e3361b55c38a8eca8793905a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-14mb/google/geralt: Enable IVO_T109NW41 MIPI panel for CiriRuihai Zhou
The IVO_T109NW41 will be the second source MIPI panel for Ciri. BUG=b:319025360 TEST=boot Ciri with IVO_T109NW41 panel, see firmware screen BRANCH=None Change-Id: I9dc2228d39bb8bb048d1f37727c96b0ad621e912 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-01-14mb/google/geralt: Enable BOE_NV110WUM_L60 panel for CiriRuihai Zhou
The MIPI panel BOE_NV110WUM_L60 will be used for Ciri, enable it. Also remove the `mdelay(10)` after mtk_i2c_bus_init, because MTK confirms this is not needed. Add mdelay(2) between VDD18 and VSP/VSN to meet the panel datasheet. BUG=b:308968270 TEST=Boot to firmware screen BRANCH=None Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78957 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14tree: Use accessor functions for struct region fieldsNico Huber
Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: Iaae116a1ab2da3b2ea2a5ebcd0c300b238582834 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-14mb/hp/compaq_elite_8300_usdt: Add VBTRiku Viitanen
Extracted from a system running OEM BIOS v03.08 (latest as of now). Build-tested and boots Linux (through SeaBIOS). Command used: intelvbttool --inlegacy --outvbt data.vbt Change-Id: Ibd999d30d6e8fea1368afae67f4dc1c3039d3ae1 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-13tree: Remove duplicated includesElyes Haouas
Change-Id: I09dd5871cb366ef95410efc1ca6c4337f23b52fd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79912 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-13lib/fw_config: Remove redundant stdbool and stdintElyes Haouas
<types.h> already includes <stdbool.h> and <stdint.h> Change-Id: Ie8676769127d21a3b4693ed947a7231b94e99241 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-13lib/smbios: rename segment group parameter of smbios_write_type41Felix Held
Rename the segment group parameter of smbios_write_type41 from 'segment' to 'segment_group' to be in line with the PCI specification. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6ca0ce8b6b3b0357df72bafa2b6069132d0937e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79926 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-13lib/smbios: add segment_group parameter to smbios_write_type9Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I48b393913913db8436f5cbca04d7411e68a53cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-13soc/amd/common/data_fabric/domain: write _SEG method in SSDTFelix Held
As a preparation for the multi PCI segment group support, use acpigen_write_BBN to generate the _SEG method that returns the segment group number of the PCI root. Until the multi PCI segment group support is enabled in coreboot, it will always return 0. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2a812dcc564c5319385e9ad482d29b2984a71b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79924 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-13acpi/acpigen: add acpigen_write_SEG for segment group number methodFelix Held
Introduce acpigen_write_SEG to generate the ACPI method object that returns the PCI segment group number for a PCI(e) host bridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94837fdbe140ee1ff904ffd20bdab3e86f850774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-13mb/google/brox: Enable Elan trackpadShelley Chen
BUG=b:311450057,b:300690448 BRANCH=None TEST=to be tested on a device with i2cdetect Change-Id: If6da1c722e87a50c6d422b300f16a52d884fa08f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-13mb/google/brox: Configure vGPIOs for NVMeShelley Chen
This is needed for NVMe to work when PCIe device is connected to the CPU side of RPL soc. BUG=b:311450057,b:300690448, b:319058143 BRANCH=None TEST=Tested on device and was able to boot to the OS Change-Id: Ic8a1fdcedf2ec6c7bf1dd00e02ef7c13e9338aac Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-13mb/google/brox: Disable package c state demotionShelley Chen
This needs to be disabled for RPL otherwise we'll hit the assertion: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', line 1066 There is a comment in the referenced file/line in the assertion that says that "C state demotion must be disabled for Raptorlake J0 and Q0 SKUs." So, disabling it. BUG=b:311450057,b:300690448 BRANCH=None TEST=Tested that we didn't hit this assertion on the device after this change Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79855 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-12Documentation: Start administrator handbookPatrick Georgi
Let's spread the work of maintaining various of our services, but to achieve that, we need to document what needs to be done. Change-Id: I87021ee62d18fa464f70351ea8bad732889d55f1 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79901 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-12lint/kconfig_lint: Remove SOUTH_BRIDGE_OPTIONSElyes Haouas
SOUTH_BRIDGE_OPTIONS Kconfig symbol is no longer used. Change-Id: I2380f1ce48afd191755d8b3dcab0b51909f5231f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79913 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-12sb/intel/bd82x6x: Remove dummy SOUTH_BRIDGE_OPTIONS Kconfig symbolElyes Haouas
Change-Id: If4ae9c800325f5de8f170f8922bacffad1c9bb20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77532 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-12mb/google/nissa/var/anraggar: add FW config to apply the wifi sarJianeng Ceng
1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings. - WIFI_6 for MTK Wi-Fi module MT7921L - WIFI_6E for Intel Wi-Fi module AX211NGW BUG=b:315418153 TEST=emerge-nissa coreboot Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-01-12soc/intel/xeon_sp: Allocate resources above 4GArthur Heymans
This makes sure that prefetchable mem64 memory gets allocated above 4G which allows non prefetchable resources to be allocated in the tight window below 4G. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79058 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-12device/Kconfig: Add an option to allocate above 4G by defaultArthur Heymans
Historically resource allocation in coreboot was 32bit x86 thing. To remain compatible with this behavior (e.g. to keep 32bit payloads happy), resource allocation limits resources to 32 bits unless explicitly overridden. However this behavior is not always appropriate: e.g. on non x86 platforms the PCIe mem decode window could be above 4G. Another case on x86 is where the decode window(s) below 4G are not adequate for fitting all resources and the payload is 64bit capable (e.g. Linux). This adds a Kconfig flag to override the behavior to limit resources to 32bit by default and to allocate resources according to the real hardware limits. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78331 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-01-12util/ifdtool: Enable Read Access for SPI device expansion 2 regionSubrata Banik
As per Intel Meteor Lake SPI programming doc, the BIOS region should have a read access enabled for device expansion 2 region (aka region 9). This patch ensures that BIOS region is able to read the device expansion 2 region for Intel Meteor Lake platform as known as SPI padding region. BUG=b:274356894 BRANCH=firmware-rex-15709.B TEST=Able to flash screebo AP FW image using flashrom on DUT. Without this patch: > flashrom -p internal -r /tmp/bios.rom flashrom 1.4.0-devel on Linux 6.1.67-09255-ge8ae3115f8b0 (x86_64) ... ... Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific) on internal. Reading flash... Transaction error between offset 0x0072f000 and 0x0072f03f (= 0x0072f000 + 63)! read_flash: failed to read (0x72f000..0x7fffff). Read operation failed! FAILED. FAILED With this patch: > flashrom -p internal -r /tmp/bios.rom flashrom 1.4.0-devel on Linux 6.1.68-09294-g001fdda5287d (x86_64) ... ... Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific) on internal. Reading flash... done. SUCCESS Change-Id: I18c44aa9a0f890f01a889247da118b69a58936e8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-12mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324Robert Chen
driver Since DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER value on dedede cannot meet DRIVERS_I2C_SX9324 on nissa, need to update the tuning value. Update proximity sensor fine tune value with quandiso EVT machine. BUG=b:314550601 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and verify p-sensor watch 'cat /sys/bus/iio/devices/iio:device*/*raw' Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-12mb/pcengines/apu2/Kconfig: select HUDSON_FADT_LEGACY_DEVICESFelix Held
The APU boards have an NCT5104D chip on the LPC bus that implements some serial ports that have the legacy IO port interface to the host and doesn't describe this in the ACPI tables, so select HUDSON_FADT_LEGACY_DEVICES to have the corresponding FADT bit set. Since this chip doesn't provide an 8042-compatible keyboard controller, don't select HUDSON_FADT_8042. TEST=Surprisingly, this doesn't seem to make a difference to the Linux kernel; is creates all ttyS[0..3] devices with and without this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8872b8c3d6e0610630ba17a0fccdcf8cebb1d3c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-12sb/amd/pi/hudson/Kconfig: replace HUDSON_LEGACY_FREE optionFelix Held
HUDSON_LEGACY_FREE controlled both if the legacy devices and the 8042 flags are set in the IA-PC boot architecture filed of the FADT. Since some systems have legacy devices on the LPC bus, but no 8042-compatible keyboard controller, replace this option with the two new options HUDSON_FADT_LEGACY_DEVICES and HUDSON_FADT_8042. TEST=The FACP table doesn't change on APU2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ff85630c90fb2ae8c8826bbc9049a08668210d Reviewed-on: https://review.coreboot.org/c/coreboot/+/79893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-11cpu/x86/smi_trigger: use call_smmFelix Held
Use call_smm instead of writing the command number directly to the APMC SMI command IO port. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iefbdb3d17932d6db6a17b5771436ede220c714fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/79828 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11arch/x86/include/smm_call: improve documentation of call_smmFelix Held
Since the inline assembly code in call_smm doesn't make it exactly obvious how this function to call the APMC SMI handler works in detail, add a more detailed explanation as comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3566af191492ce00a3033335ff80e01c33e98e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-11arch/x86/include/smm_call: use pm_acpi_smi_cmd_portFelix Held
Use pm_acpi_smi_cmd_port() to get the APMC trigger IO port instead of using the hard-coded APM_CNT define. This makes sure that the correct APMC IO port will be used even when a system doesn't use the default APM IO port. TEST=SMMSTORE V2 still works with the EDK2 payload on Careena Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb79c91cfcd75db760bd80cff7f3d0400d1f16cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/79568 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11drivers/smmstore/ramstage: use call_smmFelix Held
Use call_smm instead of open-coding the same in inline assembly functionality in init_store. The local ebx variable is dropped, since call_smm takes a pointer to the argument instead of an integer, and the local eax variable is renamed to res to make the code a bit clearer, since the EAX register is used for both passing the command and subcommand to the APMC SMI handler and to get the return value from the handler. TEST=SMMSTORE V2 still works with the EDK2 payload on Careena Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib14de0d120ae5c7db3bb7a529837ababe653e1a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-11libpayload: Move back the ttb_buffer sectionYi Chou
Moving it into the .ttb_buffer section will accidentally set the LOAD flag. So, move it back to .bss.ttb_buffer section to prevent the binary size bloating. BUG=b:248610274 TEST=Make sure the device is still bootable with this change. BRANCH=none Cq-Depend: chromium:5173448 Change-Id: I9bb08878dd4be01d9ed3f96933f774dd6296f76e Signed-off-by: Yi Chou <yich@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79800 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodesFelix Held
Tell binaryPI to not disable the LPC decodes for the IO ports used by the serial ports on the Super I/O chip during the AmdInitReset binaryPI entry point. Checked the Stoneyridge binaryPI source code which is closely enough related to be reasonable sure that this option only controls which LPC decode bits get cleared and won't have any other side effects. TEST=Now the full console output from the APU2 board gets printed on the serial console. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I91ef4423bd7bf6c1d7a175336f0f89479f2cde02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79852 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11mb/starlabs/starbook/rpl: Enable C1eSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3a317d031e71f86afc50b229d1b97197552f4fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-11soc/amd/stoneyridge/acpi: use common AMD MADT codeFelix Held
Now that Stoneyridge also reports the GNB IOAPIC on the domain and with the IOMMU_IOAPIC_IDX resource index the common AMD MADT code expects, we ca switch over to using this common code on Stoneyridge too. TEST=The resulting MADT doesn't change on Careena Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If4ce71a47827e144c4d4991152101650904901f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-11soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domainFelix Held
Move the GNB IOAPIC resource from being reported in the GNB PCI device to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the common AMD MADT code will be able to find the resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-11soc/amd/stoneyridge/acpi: drop wrong comment in MADT codeFelix Held
The IOAPIC structure that this function created is for the IOAPIC in the GNB and not the one in the FCH which is called Kern in this SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6eec02578f2b2e8b8c10dad7eeecff961ef45e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79883 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.hFelix Held
Move the IOMMU_IOAPIC_IDX define from amdblocks/data_fabric.h to amdblocks/ioapic.h which is both a more logical place for it to be and this is also a preparation to use the common AMD MADT code for the Stoneyridge SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-11.gitignore: Ignore payloads/libpayload/generated/Yu-Ping Wu
Add 'generated/' to .gitignore. Change-Id: Ief7afe3cf6ffcaba6aa5be27f41c6a32de9e6bbb Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79873 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSPLean Sheng Tan
Update the VBT version from 249 to 251. It is the same VBT settings as the previous one, but update it based on ADL-P MR5 FSP so it will work with MR5 GOP driver to fix the error "no graphic HOB found". Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79020 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11arch/x86/c_start.S: Add proper x86_64 codePatrick Rudolph
Don't truncate upper bits in assembly code and thus allow loading of ramstage above 4GiB. Tested on qemu with cbmem_top set to TOUUD. Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Co-authored-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11mb/google/nissa/var/craaskov: Enable PIXA touchpadIan Feng
Add PIXA touchpad for variants of craaskov. BUG=b:289962540 TEST=build craaskov firmware and test with PIXA touchpad Change-Id: Iccf19b275548f44aec00be8631590b8a7ad1aa23 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79872 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-01-11vc/google: Show different logos for different ChromeOS devicesShelley Chen
This commit adds support for showing different logos on the ChromeOS firmware splash screen based on the device model (between Chromebook-Plus and regular ChromeOS devices like Chromebook and Chromebox). This allows OEMs to customize the branding on their devices. This patch also introduces three new Kconfigs: - CHROMEOS_FW_SPLASH_SCREEN - CHROMEOS_LOGO_PATH - CHROMEBOOK_PLUS_LOGO_PATH which allow users to enable the fw splash screen feature in the vendorcode. Previously, we were using the BMP_LOGO Kconfig in drivers/intel/fsp2_0, but we didn't want the top level Kconfigs to be located inside the architecture specific files. BUG=b:317880956 BRANCH=None TEST=emerge-rex coreboot chromeos-bootimage verify that FW splash screen appears Change-Id: I56613d1e7e81e25b31ad034edae0f716c94c4960 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79775 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-11mb/google/rex: Remove redundant HAVE_FSP_LOGO_SUPPORT configSubrata Banik
Removes unnecessary HAVE_FSP_LOGO_SUPPORT config from google/rex baseboard. Intel Meteor Lake SoC now selects this config automatically for supported platforms. BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex and intel/mtlrvp. Change-Id: I89bdd54cb73b11f74db2927a5eb86ab826c60517 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79860 Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11soc/intel/meteorlake: Enable FSP logo support by defaultSubrata Banik
Enables FSP logo support for Meteor Lake SoC config, covering both Intel Meteor Lake RVP and ChromeOS devices. Applies HAVE_FSP_LOGO_SUPPORT configuration only for platforms with native FSP support. Ensures successful builds and boots for google/rex and intel/mtlrvp. BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex and intel/mtlrvp Change-Id: Ic99bfdc2d33db48bdb015525981c1ef76df8203b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79859 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-11soc/amd/common/acpi: factor out common MADT codeFelix Held
The acpi_fill_madt implementation from the Genoa PoC also works for the other AMD SoCs that select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN, so factor out this function to the common AMD ACPI code and change those other SoCs to use the new common functionality instead of having their own implementations. The old code on the single-domain SoCs used the GNB_IO_APIC_ADDR base address to create the MADT entry for the additional IOAPIC in the root complex. The new code iterates over all domains and looks for a resource with the IOMMU_IOAPIC_IDX index in each domain and if it finds it, it creates an MADT entry for that IOAPIC. This resource is created earlier in the boot process when the non-PCI resources are read from the IOHC registers and reported to the allocator. TEST=The resulting MADT doesn't change on Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4cc0d3f30b4e6ba29542dcfde84ccac90820d258 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79861 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10arch/x86/include: rename smm.h to smm_call.hFelix Held
Rename smm.h to smm_call.h to make including this file look less ambiguous. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia907ad92459e835feeddf7eb4743a38f99549179 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79833 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10arch/x86/include/smm: use inline asm from drivers/smmstore/ramstageFelix Held
The call_smm function is currently unused and the inline assembly code for more or less the same functionality in drivers/smmstore/ramstage is both a bit easier to understand since it uses the register names in the 'outb' instruction instead of positional arguments, and also tells the compiler that this piece of code might change global memory. Having too much in the clobber list might only have some performance impact, which should however be negligible compared to the SMI handler being called, while missing something in the clobber list might cause hard to debug problems. This is a preparation to make drivers/smmstore/ramstage use call_smm instead of having its own inline assembly implementation for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I73837cab75429014897486b38a5c56f93a850f96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10mb/google/nissa/var/anraggar: Add FW_CONFIG probe for mipi cameraWeimin Wu
Due to some without mipi camera SKUs can't entering S0i3. BUG=b:317670018 TEST=suspend_stress_test -c 1 Change-Id: Ifa8649a603c59946b530abd315113b405ceaf35a Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-10mb/google/byra/var/*: Set WLAN device type back to pciDavid Ruth
This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the WLAN device type to generic broke ACPI SSDT table definition, so set it back to pci. BUG=b:318576073 TEST=build/boot google/nissa (pujjo), verify WLAN ACPI SSDT tables contain the appropriate device entry. Change-Id: If5dad9deb040c8cb0c507e11726f0ba44ccb2909 Signed-off-by: David Ruth <druth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-10sb/amd/pi/hudson/smhandler: use apm_get_apmc() in APMC SMI handlerFelix Held
Instead of open-coding this functionality and using non-common defines, call the apm_get_apmc() helper function. This also brings this more in line with the newer AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic16596404f46bf431e1c5db56859ddfea5fccbf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10sb/amd/pi/hudson: select HAVE_CONFIGURABLE_APMC_SMI_PORTFelix Held
Select HAVE_CONFIGURABLE_APMC_SMI_PORT and implement the pm_acpi_smi_cmd_port helper function. TEST=APU2 still compiles with HAVE_SMI_HANDLER selected and NO_SMM select removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f79d8c1d59aa1b6c1145dd0b1cbc9010a1c57e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10sb/amd/pi/hudson/smhandler: use common APM_CNT_ACPI_* definesFelix Held
The Hudson southbridge code for the AMD binaryPI SoCs had its own ACPI enable and disable APMC command numbers that didn't match the common defines in coreboot, so use the common define here to be consistent with the command numbers in the corresponding FADT fields. Since the only SoC that still would use this code doesn't select HAVE_SMI_HANDLER, this won't fix any observable bug, but better fix this before anyone possibly runs into this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e596071e1b5269b616b7a93151648cb86ae77bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10sb/amd/pi/hudson: drop unused ACPI_SMI_CMD_* definesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf02d8bee70fd654b3e71d1ead6dc0414fb6de40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79847 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10sb/amd/pi/hudson: fix gpio.h and smi.h include locationFelix Held
This fixes the following compile error when trying to build the APU2 board with HAVE_SMI_HANDLER selected and the NO_SMM select removed: In file included from src/soc/amd/common/block/gpio/gpio.c:8: src/include/gpio.h:6:10: fatal error: soc/gpio.h: No such file or directory 6 | #include <soc/gpio.h> /* IWYU pragma: export */ | ^~~~~~~~~~~~ Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie06044b12f5cbcc55a2706ec566afd2eb294c62b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79846 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/amd: use apm_get_apmc() in APMC SMI handlerFelix Held
Instead of open-coding this functionality, call the apm_get_apmc() helper function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac6b614d900e51d91a0c155116a5edc29775ea99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10cpu/x86/smi_trigger: use enum cb_err as apm_control return typeFelix Held
Even though the return value from apm_control isn't checked at any of its call sites, using the cb_err enum instead of an integer as return type makes it clearer what the returned value means. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I07ced74cae915df52a9d439835b84237d51fdd11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79835 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10mb/google/cherry: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on dojo Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-10mb/google/corsola: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on Steelix, Tentacruel and Starmie Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79777 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/mediatek: Add common implementation to configure displayYidi Lin
The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on() - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to mediatek/common/display.c and refactors `struct panel_description` to generalize the display init sequences. configure_display() is also renamed to mtk_display_init(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79776 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/amd/glinda: Increase maximum CPU threads to 24Anand Vaikar
glinda SOC has 24 maximum CPU threads as per PPR documentation(#57254). TEST=Boot logs print the CPU initialization happens for 24 threads. Change-Id: Id48a5c62d6156c046daffd2648aeebeee380bd88 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-10mb/intel/mtlrvp: define a new config for Chrome ECDeepti Deshatty
Introduce new config MTL_CHROME_EC_SHARED_SPI, tailored for Chrome ECs utilizing an external shared SPI flash. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Cq-Depend: chrome-internal:6691498 Cq-Depend: chrome-internal:6741356 Change-Id: I462c34c5adaefa37c652de293152243c58bad7c5 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-10mb/intel/mtlrvp: streamline Chrome EC configsDeepti Deshatty
Chrome EC configuration options that are common among various boards have been consolidated under the "BOARD_EXT_EC_SPECIFIC_OPTIONS" config. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79211 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-09Makefile.inc: Enable Wold-style-declaration command optionElyes Haouas
Warn for obsolescent usages, according to the C Standard, in a declaration. For example, warn if storage-class specifiers like static are not the first things in a declaration. Change-Id: Ida3fa59edb07e4105ef3cfb6a20cb29680699586 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71892 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-09soc/nvidia: Put static keyword at the beginning of declarationsFelix Singer
In order to comply with the more recent style of declarations, put the static keyword at the beginning. Fixes following GCC error when the related flag is set: error: 'static' is not at beginning of declaration [-Werror=old-style-declaration] Change-Id: Ida683319f7a0c428a9e4808821075abdd9fcb504 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79856 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-093rdparty/vboot: Update submodule to upstream mainFelix Singer
Updating from commit id 7c3b60bb: 2023-12-21 20:34:49 +0000 - (firmware/2lib: Use SSE2 to speed-up Montgomery multiplication) to commit id 32402941: 2024-01-08 19:53:43 +0000 - (treewide: Put the static keyword at the beginning of declarations) This brings in 4 new commits: 32402941 treewide: Put the static keyword at the beginning of declarations 242d198b crossystem: Use external tool the clear the TPM c8a0802f tests: Remove unnecessary vb2_verify_fw.c from TEST20_NAMES list 706088b8 tests: Test HW crypto RSA signature verification Change-Id: I667376dfc3021fa6d213e3d89917ee228fd14a28 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-01-09mb/ibm/sbp1: Set FSP loglevelPatrick Rudolph
Change-Id: Ia97dbda30f657f0b1568364d712eaea8d134b3b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79791 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-09mb/google/brox: Fix error in DDR DQS configShelley Chen
The DQS mapping for DIMM idx 6 was discovered to be incorrect to what was in the schematics. Correcting the mistake in this CL. BUG=b:311450057,b:300690448 BRANCH=None TEST=tested on device and it passed memory training Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2024-01-09soc/intel/mtl: Override the `SOC_PHYSICAL_ADDRESS_WIDTH` as integerSubrata Banik
This patch enforces consistent override handling for integer `SOC_PHYSICAL_ADDRESS_WIDTH` config Change-Id: Ib5bdfdb8c2689803c9d3c2bfd353609edae91ab3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-09drivers/mipi: Add support for IVO_T109NW41 panelRuihai Zhou
Add IVO_T109NW41 serializable data to CBFS. Datasheet: T109NW41 R0 Tentative Product Specification.docx BUG=b:319025360 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: Id740e3a21f72bbcd6e5c2b56b31ac90f4990d475 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79844 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-08util/lint: Remove the extra `\` in lint-stable-003-whitespaceRuihai Zhou
A following error occurred when I commit, it seems that the extra `\` after `\.md$` is unnecessary. File Binary file src/mainboard/google/guybrush/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/skyrim/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/zork/data.apcb matches has lines ending with whitespace. test failed Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79782 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-01-08src/arch/x86/exit_car: Add proper x86_64 codePatrick Rudolph
Don't truncate upper bits in assembly code and thus allow loading of postcar stage above 4GiB. Tested on qemu with cbmem_top set to TOUUD. Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-08cpu/x86/smi_trigger: call pm_acpi_smi_cmd_port to get APMC SMI IO portFelix Held
Instead of hard-coding the APMC SMI command IO port in the FADT, call pm_acpi_smi_cmd_port() to get the APMC SMI command IO port. Also update the comment in apm_get_apmc to match what it's doing. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f36b8a0e93a82b8c6d23c5c5d8fbebb1bc6b0bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-08arch/x86/acpi: call pm_acpi_smi_cmd_port to get APMC SMI IO portFelix Held
Instead of hard-coding the APMC SMI command IO port in the FADT, call pm_acpi_smi_cmd_port() to get the APMC SMI command IO port. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I731c780bc6db7e7fd59688340bab1da86fc93c11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79565 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-08arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORTFelix Held
Introduce the HAVE_CONFIGURABLE_APMC_SMI_PORT Kconfig option that when not selected will result in a default implementation of pm_acpi_smi_cmd_port to be included in the build that returns APM_CNT. SoCs that provide their own pm_acpi_smi_cmd_port implementation, need to select this Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaceb61b0f2a630d7afe2e0780b6a2a9806ea62f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-08mb/google/nissa/var/craaskov: Implement touchscreen power sequencingrex_chou
For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:317746281 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79764 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-08util/ifdtool: Add support for extended region read/write accessReka Norman
Platforms from CNL onwards support up to 16 flash regions, not 12. The permissions for regions [15:12] are stored in extended region read/write access fields in the FLMSTR registers. Currently ifdtool treats these fields as reserved, so they're not modified when locking or unlocking. Add support for extended regions so that they are locked/unlocked by the --lock/--unlock options. This will make the locked/unlocked descriptors generated by ifdtool match those generated by mFIT. BUG=b:270275115 TEST=Without this change: `ifdtool -lr -p adl` on unlocked image: Before: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff After: 00000080 ff 07 20 00 ff 05 40 00 ff 00 00 00 00 00 00 00 00000090 ff 00 00 00 `ifdtool -u -p adl` on locked image: Before: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 After: 00000080 00 ff ff ff 00 ff ff ff 00 ff ff ff 00 00 00 00 00000090 00 ff ff ff With this change: `ifdtool -lr -p adl` on unlocked image: Before: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff After: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 `ifdtool -u -p adl` on locked image: Before: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 After: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff Change-Id: Iaa43524d91c399a996ade56f2f613b4110a44aad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-08nb/intel/gm45/raminit: Use read32p()Elyes Haouas
Built roda/rk9 with BUILD_TIMELESS=1 and the resulting coreboot.rom remains identical. Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77971 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-08drivers/mipi: Add support for BOE_NV110WUM_L60 panelRuihai Zhou
Add BOE_NV110WUM_L60 serializable data to CBFS. Datasheet: B5NV110WUM-L60 V5.0Product SpecificationRev.P0 BUG=b:308968270 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78956 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-07vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85Kulkarni, Srinivas
Update header files for FSP for Meteor Lake platform to version 3471_85, previous version being 3424_88. FSPM: 1. Add 'DisplayGpioPinMux' UPDs 2. Address offset changes BUG=b:318772151 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79829 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-06Documentation/getting_started: Add a FAQ documentMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: Ia324e4800bf9dfc7ad86f4f99272c87ac566304e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79441 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-06soc/rockchip/rk3399/mipi: Remove space before semicolonElyes Haouas
Change-Id: I7e02173c296689ef3143a1079658006ec91c4dc2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77156 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05mb/hp/z220_series: Rename to snb_ivb_desktopsRiku Viitanen
In preparation for adding other similar boards under it as variants. Tested that z220_cmt still builds. Change-Id: I96dec173e0d97d8564bad14778333b8231684ef8 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79434 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05soc/amd/picasso/Kconfig: select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFFFelix Held
Commit 850b6c6254ab ("soc/amd/picasso: add eMMC MMIO device to devicetree") broke both S3 resume on Morphius SKUs that use an NVMe SSD instead of an eMMC and boot on the currently out-of-tree ASRock X370 Killer SLI board. In the latter case, commenting out the power_off_aoac_device call inside the emmc_enable function fixed things. TEST=This fixes S3 resume on Morphius with NVMe SSD and an equivalent change discussed in the patch mentioned above that caused the regression also fixed boot on the ASRock board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: Id976734c64efe7e0c3d8b073c8009849be291241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-05soc/amd/common/emmc: add Kconfig option to skip powering off eMMCFelix Held
Add a Kconfig option to skip powering off the eMMC controller via the AOAC block in the case where the eMMC controller is disabled in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0dbe819222972d9bf0789671b031ad83648e8917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79825 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05arch/x86/include/mode_switch: Add more wrapper functionsPatrick Rudolph
Add a protected mode wrapper function that takes three arguments. This is already supported by the called assembly code. Change-Id: Ia8c91eebae17e4ca27e391454c2d130a71c4c9f3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>