diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-01-09 00:19:19 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-01-09 23:23:24 +0000 |
| commit | d74ee60f71fd45449cd710a58a7f2ca9fae2ca49 (patch) | |
| tree | f9d74da6de6a6ead013b886345c6db42b76f3744 | |
| parent | a4a65b202517871aee2f6b01c2530d25636c337d (diff) | |
soc/nvidia: Put static keyword at the beginning of declarations
In order to comply with the more recent style of declarations, put the
static keyword at the beginning.
Fixes following GCC error when the related flag is set:
error: 'static' is not at beginning of declaration [-Werror=old-style-declaration]
Change-Id: Ida683319f7a0c428a9e4808821075abdd9fcb504
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79856
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
| -rw-r--r-- | src/soc/nvidia/tegra124/clock.c | 4 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/clock.c | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index f8a232f875..0dae02d3de 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -80,7 +80,7 @@ union __attribute__((transparent_union)) pll_fields { * PLLU: 1 MHz < CF < 6 MHz, 480 MHz < VCO < 960 MHz * PLLDP: 12 MHz < CF < 38 MHz, 600 MHz < VCO < 1200 MHz * (values taken from Linux' drivers/clk/tegra/clk-tegra124.c). */ -struct { +static const struct { int khz; struct pllcx_dividers pllx; /* target: CONFIG_PLLX_KHZ */ struct pllcx_dividers pllc; /* target: 600 MHz */ @@ -89,7 +89,7 @@ struct { struct pllu_dividers pllu; /* target; 960 MHz */ struct pllcx_dividers plldp; /* target; 270 MHz */ /* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */ -} static const osc_table[16] = { +} osc_table[16] = { [OSC_FREQ_12] = { .khz = 12000, .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 95507e3950..4433d7e177 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -27,7 +27,7 @@ enum { PLL_MAX_INDEX, }; -struct pll_reg_info { +static const struct pll_reg_info { u32 *base_reg; u32 *lock_enb_reg; u32 lock_enb_val; @@ -40,7 +40,7 @@ struct pll_reg_info { u32 kcp_shift:5; /* kcp bits location */ u32 kvco_shift:5; /* kvco bit location */ u32 rsvd:7; -} static const pll_reg_table[] = { +} pll_reg_table[] = { [PLLX_INDEX] = { .base_reg = CLK_RST_REG(pllx_base), .lock_enb_reg = CLK_RST_REG(pllx_misc), .lock_enb_val = PLLPAXS_MISC_LOCK_ENABLE, @@ -127,10 +127,10 @@ struct pll_fields { * PLLM is set up dynamically by clock_sdram(). * PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD). */ -struct { +static struct { int khz; struct pll_fields plls[PLL_MAX_INDEX]; -} static osc_table[16] = { +} osc_table[16] = { [OSC_FREQ_12] = { .khz = 12000, .plls = { |