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USB3 is used for both typeA and WWAN based on different DB.
BUG=b:287159026
TEST=change FW config and check typeA and WWAN can work.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75819
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:284388714
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75834
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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TCSS and TBT use the same lane on schematic. Update the port start
from 0 to match the Intel schematic. You can better follow the it
without convert the port number.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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MTL FSP uses 202302 Edk2. select UDK_202302_BINDING Kconfig for MTL SoC.
BUG=b:261689642
TEST= Build and boot to Google/rex.
Change-Id: I9167e3b08a2a1fa2f4cc6ca11cb8308dc56fd940
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75728
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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edk2-stable202111 is older release of edk2. MTL FSP uses 202302 Edk2.
There are structure definition changes between 202111 and 202302. One of
change is in FSP_INFO_HEADER structure. Also, Next Gen Intel SoC needs
202302 Edk2.
This patch includes (edk2/edk2-stable202302) all required
headers for edk2-stable202302 EDK2 tag from EDK2 github
project using below command:
git clone -b edk2-stable202302 https://github.com/tianocore/edk2.git
commit hash: f80f052277c88a67c55e107b550f504eeea947d3
Only include necessary header files.
MdePkg/Include/Base.h was updated to avoid compilation errors
through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE.
Add UefiCpuPkg/Include Because `MpServices2.h` file is part of
`UefiCpuPkg/Include/Ppi/`
Add following fixes from edk2-stable202111
060492ecd2 Safe guard enum macro in SmBios.h
2bf9599cf1 Use fixed size struct elements
BUG=b:261689642
TEST= select UDK_202302_BINDING Kconfig for MTL, Test Build and boot rex
Image
Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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- Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this. (it
disables all probed devices when fw_config is unprovisioned.).
- Removed `bootblock-y += variant.c` from Makefile.inc based on
CL:3841120.(The infrastructure for selecting an appropriate firmware
image to use the right descriptor is now ready so runtime descriptor
updates are no longer necessary.).
BUG=b:285477026
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I6920d88dfec86676ff6733146f748e06d4085c49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75743
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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There are two baseboards within the set of mainboards built
here, with baseboard name appended in the filenames.
Take the style and variable BASEBOARD_DIR from google/brya,
then move and rename the supporting files under separate
directories.
Change-Id: I2046b6f82519540b8596ce925203bd60d1870c1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74471
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the initial USB PHY tuning values that were a copy of the ones
from the Chausie mainboard to the values used in the Birman UEFI
firmware reference implementation. The USB3 PHY tuning values are still
the same while some of the USB2 PHY tuning values are different. The
last two USB2 PHYs that are used by the USB4 controllers have a
different parameter set compared to the other USB2 PHYs.
TEST=All USB ports on Birman function as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75823
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add following config options.
1. TME_GENERATE_NEW_KEY_ON_WARM_BOOT
Program Intel TME to generate a new key for each warm boot. TME
always generates a new key on each cold boot. With this option
enabled TME generates a new key even in warm boot. Without this
option TME reuses the key for warm boot.
2. TME_EXCLUDE_CBMEM_ENCRYPTION
This option allows to exclude the CBMEM region from being encrypted
by Intel TME. When TME is enabled it encrypts whole DRAM. TME
provides option to carve out a region of physical memory to get
excluded from encryption. With this config enabled, CBMEM region
does not get encrypted by TME. If TME is not programmed to generate
a new key in warm boot, exclusion range does not need be programmed
due to the fact that TME uses same key in warm boot if
TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is
programmed to generate a new key in warm boot, contents of the CBMEM
get encrypted with a new key in each warm boot case hence, that leads
to loss of CBMEM data from previous warm boot. So enabling this
config allows CBMEM region to get excluded from being encrypted and
can be accessible irrespective of the type of the platform reset.
Bug=b:276120526
TEST=Able to build rex
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Id5008fee07b97faadc7dd585f445295425173782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75625
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add additional ram parts and generate strapping ids.
BUG=b:285216975
TEST=Build myst image
Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75821
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This patch disables the ACPI PM timer which is necessary for XTAL OSC
shutdown. Also, disabling ACPI PM timer switches off TCO.
BUG=b:274744845
TEST=Able to boot and verify S0ix is working even with EC reset and
cold boot scenarios.
w/o this cl:
> iotools mmio_read32 0xfe4018fc
0x0
w/ this cl:
> iotools mmio_read32 0xfe4018fc
0x2
Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM.
BUG=b:216393391
TEST=build pass
Change-Id: I3797de01629fdb5ace4c610943d88db525da112b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75826
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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It seems that using a wildcard (*) in the import path is not supported
in the context of the Makefile.
This to fix this error:
malformed import path "cmd/cbnt-prov/*.go": invalid char '*'
Change-Id: I953e06f1ff70a2b61bc5f505f7df9936b7f9b55b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This patch enables BT offload feature on Rex over SSP1.
BT mode is selected via FW_CONFIG and corresponding VGPIOs are
programmed.
BUG=b:275538390
TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72881
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pujjo does not support GPIO based D-SAR,
so set GPP_D15 and GPP_H23 to NC.
BUG=b:275264095
TEST=boot on pujjo and no impact WWAN dynamic SAR function
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I4fe40b32a572a8d914e01e5cd7927766ccf17c02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75403
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Lay the groundwork to prepare for enabling PSP verstage. This change
adds PSP verstage callback to enable eSPI, TPM etc.
BUG=b:284984667
TEST=Build Myst BIOS image with PSP verstage enabled.
Change-Id: Ifc800e8bb27cc4c3fbccc2ab9f51138a7c4b03a6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75585
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0.
TEST=check dmidecode dump the max speed.
Handle 0x000C, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 16 GB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR5
Type Detail: Unknown Synchronous
Speed: 5600 MT/s
Manufacturer: Micron
Serial Number: 3f064d84
Asset Tag: Channel-0-DIMM-0-AssetTag
Part Number: MTC8C1084S1SC56BG1
Rank: 1
Configured Memory Speed: 5200 MT/s
Minimum Voltage: 1.1 V
Maximum Voltage: 1.1 V
Configured Voltage: 1.1 V
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In commit e59f18bf29a8 ("drivers/i2c: Add PI7C9X2G608GP PCIe switch
driver (pi608gp)"), there were some suggestions after it's been already
merged.
This patch addresses the points regarding the code style and comments.
BUG=none
TEST=Build OK, no behavioral changes in the pi608gp driver, console logs
without changes.
Change-Id: I5fc54708e0085fea4bd1f2fbf2afb400d2ccbd46
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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In commit e59f18bf29a8 ("drivers/i2c: Add PI7C9X2G608GP PCIe switch
driver (pi608gp)"), there were some suggestions after it's been already
merged.
This patch addresses the points regarding the number types - fix of the
printk format strings, inclusion of 'stdint.h' and marking the set of
allowed values as constant.
BUG=none
TEST=Build OK, no behavioral changes in the pi608gp driver, console logs
without changes.
Change-Id: I34c664f6a8a257b260facdbf9043825ff4a4c932
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75500
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Based on:
- Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
- 7th Generation Intel Processor Families I/O for U/Y Platforms
Datasheet Vol.2 August 2017:
https://cdrdv2.intel.com/v1/dl/getContent/334659
- edk2-platforms source for Whitley and Purley platforms (Xeon SP)
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI
rate selection unlike other chipsets which use GEN_PMCON_A. Select
PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register
difference.
Based on Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If182e1285ad6bd3f7c54760440010c50f57f7013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72072
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI
rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to
indicate the register difference.
Based on Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I11241836ecc9066d323977b030686567c87ed256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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This makes sure that the resource allocator won't use this address range
for anything else. In the systems I looked at, this was between the end
of the above 4GB memory and the beginning of the above 4GB PCI BAR MMIO
region, but better reserve it here so nothing else will get allocated
there if this expectation isn't met.
TEST=Reserved region is printed in the console logs:
update_constraints: PCI: 00:00.0 09 base fd00000000 limit fdffffffff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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It's been decided not to use the USB 3.0 port 1 on this board anymore,
so disable it also with the corresponding USB 2.0 lane.
BUG=none
TEST=USB 3.0 port 1 not functional anymore after boot, while others
continue working.
Change-Id: I2799e3d9d7232743c9480dd9611d94ed3249f53b
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch reduces the redundant config check to understand if an ISH FW
partition is available and to fetch the ISH FW version.
The goal is to fetch the ISH FW version if the ISH FW belongs to the CSE
firmware partition table.
Change-Id: I689a71377e7aea0fa3bc1835f355708c33c2caea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75811
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch calls get CSE RW version function from .final hook if
the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected.
BUG=b:280722061
TEST=Able to build and boot google/rex.
> cbmem -c | grep "CSE RW Firmware Version:"
[DEBUG] CSE RW Firmware Version: 18.0.0.1682
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75749
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch renames `cse_store_rw_fw_version` function that store
currently running CSE RW FW version inside CBMEM.
Additionally, perform the CSE RW FW storing operation unconditionally.
TEST=Able to build and boot google/marasov.
Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config
to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config
is clear.
Any platform would like to fetch the currently running ISH firmware
version should select this configuration.
TEST=Able to build and boot google/marasov.
Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Boxy audio codec chip uses ALC5682I-VD, not ALC5682I-VS.
It needs to modify codec HID to "10EC5682" in coreboot to fix audio no
output sound issue.
BUG=b:286970886
BRANCH=dedede
TEST=confirm audio soundcard can be list by command "aplay -l"
Change-Id: Icd69a9d757ba817b586a703a17375682db684224
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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This patch enables adding variant specific ASL code
TEST=Kernel driver is able to communicate with device
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I231482d56dd4afa150766c07cfde105158e5e124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add driver to support ELAN touchscreen using SPI for rex
* See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum
* https://www.microsoft.com/en-us/download/details.aspx?id=103325
BUG=b:278783755
TEST=Kernel driver is able to communicate with device. Also tested
S0ix, ran 'suspend_stress_test -c 1' - no issues in suspend/resume.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74885
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Update all the required sources to lay the ground work to enable PSP
verstage.
BUG=b:284984667
TEST=Build Myst BIOS image with PSP verstage enabled.
Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75584
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder
Lake-S SKUs have GT TDC of 22A.
Based on the default settings of ADL-S FSP.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
|
|
In soc/amd this function is unused so drop it and rename
_acpi_fill_ivrs_ioapic().
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
|
|
By adding all DXIO IOAPIC with the same resource index, the IVRS code
can always pick that resource which simplifies the code.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I10345e2337dcb709c2c1a8e57a1b7dd9c04adb9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
|
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Sometimes systems don't boot to the OS due to wrong ACPI tables.
Printing the tables in an ACPICA compatible format makes analysis of
ACPI tables easier.
The ACPICA format (acpidump, acpixtract) is the following:
"
FACS @ 0x0000000000000000
0000: 46 41 43 53 40 00 00 00 E8 24 00 00 00 00 00 00 FACS@....$......
0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
"
To achieve analyze ACPI tables capture the coreboot log between
"Printing ACPI in ACPICA compatible table" and "Done printing ACPI in
ACPICA compatible table". Remove the prefix "[SPEW ] " and then call
'acpixtract -a dump' to extract all the tables. Then use 'iasl -d' on
the .dat files to decompile the tables.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75677
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Time elapsed for a single board build with ccache typically measures
well below 10 seconds. Improve the measurements to milliseconds
resolution using bash EPOCHREALTIME (pseudo) environment variable.
Change-Id: Iaedc470bb45cf9bb6f14ff8b37cd6f7ae3818a08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
One specific Hynix LPDDR5x DRAM part requires an ABL workaround to
eliminate DRAM-related failures during a FAFT test, but due to the
use of generic/common SPDs, there is no way for the ABL to determine
the DRAM part # itself.
Consequently, we will have coreboot check the DRAM part #, and set/clear
a CMOS bit as appropriate, which the ABL will check in order to apply
(or not apply) the workaround.
The ABL already uses byte 0xD of the extended CMOS ports 72/73 for
memory context related toggles, so we will use a spare bit there.
BUG=b:270499009, b:281614369, b:286338775
BRANCH=skyrim
TEST=run FAFT bios tests on frostflow, markarth, and whiterun without
any failures.
Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75698
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
|
|
Add a Dockerfile for Alpine to build-test with musl-libc.
Change-Id: If90412146acc94f01a89cd681539aad48e92dd2e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
|
|
"current" points to the start of HEST table, so "next - current" already
includes the size of its header, no need for increment here. This issue
was found on SPR-SP platform. The length of HEST table is now correct
with this patch.
Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db
Signed-off-by: Jeff Li <lijinfeng01@inspur.com>
Signed-off-by: Ziang Wang <ziang.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75738
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on joxer.
BUG=b:285477026
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.
Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA-FQ
After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I69b00f0281f4493db157783840d9cdcbb138017f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75758
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add default Intel DPTF.
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75580
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
+-------------+----------------+------------+---------------------------------+
| PCH USB 2.0 | Connector Type | OC Mapping | Remarks |
+-------------+----------------+------------+---------------------------------+
| 1 | Type-C | OC_0 | Type C port - TCP1 |
| 2 | Type-C | OC_0 | Type C port - TCP0 |
| 3 | Type-C | OC_0 | Type C port - TCP2 |
| 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0|
| 7 | Type-A | OC_3 | TAP1 |
| 8 | Type-A | OC_3 | TAP2 |
| 9 | Type-A | OC_3 | TAP3 |
+-------------+----------------+------------+---------------------------------+
+---------------------+-------------------+------------+---------+
| PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks |
+---------------------+-------------------+------------+---------+
| 1 | Type-A | OC_3 | TAP0 |
| 2 | Type-A | OC_3 | TAP1 |
+---------------------+-------------------+------------+---------+
+------+-------------------+------------+-----------------------------+
| TCPx | Connector Details | OC Mapping | Remarks |
+------+-------------------+------------+-----------------------------+
| 1 | Type C port 0 | OC_0 | To onboard Type-C connector |
| 2 | Type C port 1 | OC_0 | To onboard Type-C connector |
| 3 | Type C port 2 | OC_0 | To onboard Type-C connector |
+------+-------------------+------------+-----------------------------+
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
When fw_config is unprovisioned, devicetree will disable all probed
devices. However, boot-critical devices such as storage devices need to
be enabled.
As a temporary workaround while adding devicetree support for this,
remove the fw_config probe for storage devices so that all storage
devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled
by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI
scan, but keeping it enabled should have no functional impact, only a
possible power impact.
BUG=b:285477026
TEST=On joxer eMMC and UFS SKUs, boot to OS and
`suspend_stress_test -c 10`
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I834bd81ce636a6f32d50434cbf07b1d572620492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75757
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This fixes format string vulnerability issues with snprintf statement
found by klocwork scan.
Foundby=klocwork
BUG=NONE
TEST=Boot to OS on Meteor Lake rex platform and run klocwork scan.
Check related ACPI tables and modem driver behavior after changes.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ia6b7d70c0b2b86d0918e58348dccd206a7ee9193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75733
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds UPD entries into the FSP header file to configure VRs
(IA, GT and SA).
- `IccLimit` : VR Fast Vmode ICC Limit support
- `EnableFastVmode` : Enable/Disable VR FastVmode
- `CepEnable` : Enable/Disable CEP (Current Excursion Protection
BUG=b:286809233
TEST=Able to build google/rex.
Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75761
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
PCIE_RST_L is attached to a pull down, change the init to NC.
BUG=None
TEST=Boot to OS
Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75700
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update PCIe GPIOs during rom stage to properly initialize the
PCIe devices and allow the NVMe/eMMC to be properly detected.
BUG=b:284213391
TEST=Boot to OS
Change-Id: I24ad6c1addedb414afade2512b6628022d000a47
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
Rename get_smee_reserved_address_bits to get_sme_reserved_address_bits
since the feature is called secure memory encryption and the last 'e' in
SMEE bit in the SYSCFG MSR just stands for enable. The function will
return a valid number of reserved address bits no matter if this is
enabled or not, so drop the second 'e'.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Move the WP signal to GPP_E12 from the current GPP_E15 to
match the design.
BUG=b:285084125
TEST=WP signal reports as we expect
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I8772173fcdcabf78b0c7d605cd495ebe04b63242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Some references are pointing to non-existing paths. Fix that.
Change-Id: I298370c69edc41a50c859684cc5a2c1dbfc85559
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75800
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Change-Id: I4cffd141ef74e20ef13b204955b44c07acd88edf
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75805
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM.
BUG=b:216393391
TEST=build pass
Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Currently the data to be put to cache region is 0x14FF90. With the
limit size 0x150000, the data for S3 can not be put into. So we expand
it a little.
Change-Id: If6b03b713059c54c7dae8f2db0f6426d8aa1aab1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69782
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is a complete rewrite of the UHCI root-hub driver, based on
the xHCI one. We are doing things by the book as far as possible.
One special case is uhci_rh_reset_port() which does the reset se-
quencing that usually the hardware would do.
This abandons some quirks of the old driver:
* Ports are not disabled/re-enabled for every attachment anymore.
* We solely rely on the Connect Status Change bit to track changes.
* Further status changes are now deferred to the next polling round.
The latter fixes endless loops in combination with commit 7faff543da
(libpayload: usb: Detach unused USB devices).
Change-Id: I5211728775eb94dfc23fa82ebf00fe5c99039709
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
The original clock rate 416MHz is insufficient for 4K resolution and
causing the screen to glitch. Set the clock rate to 594MHz to support
4K resolution.
BUG=b:236328487
TEST=Glitching screen was fixed after applying this patch
Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75661
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Define a CMOS layout for Librem Mini v1/v2 spanning both banks. The
only setting provided is the automatic power-on setting, which is
implemented by the EC. This can now be configured in a firmware image
by replacing cmos.default in CBFS.
Since cmos.default is applied early in bootblock, the EC BRAM interface
must now be configured in bootblock, including opening the LPC I/O
range.
Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74363
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Geralt SoC does not support 'persist certain regions' across reboots.
Considering the impact of missing ramoops for debugging, set
MEDIATEK_DRAM_SCRAMBLE to default n to disable this feature in
production FW image.
BUG=b:269049451,b:278478563
TEST=emerge-geralt coreboot and confirm CONFIG_MEDIATEK_DRAM_SCRAMBLE=n
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75562
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix a typo in an enum type name, "PIM2_MI" -> "SPIM2_MI".
TEST=emerge-cherry coreboot
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ib43a044dc69a93ad1dcaa5e65c66a82046a40777
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Enable ILI2901 and eKTH7B18 touchscreen for Google Screebo.
BUG=b:278167967
BRANCH=none
TEST=Build and boot to Google Screebo. Verify touchscreen works.
Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
|
|
As per AMD64 Architecture Programmer's Manual, section 10.2.5 SMRAM
Protected Areas:
The TSEG range must be aligned to a 128 Kbyte boundary and the minimum
TSEG size is 128 Kbytes.
The SMM TSEG size should be less than SMM reserved size.
AMD TSEG mask works like an MTRR. It needs to be aligned to it's size
and it's size needs to be a power of 2.
Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75405
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Add support of variant_devtree_update() function to override
devtree settings for variant boards. Also, add CPU power limit
values for mtlrvp baseboard.
BRANCH=None
BUG=None
TEST=Built the changes
Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Currently if a rails PG fails to assert, the power on sequence
continue after the 20ms timeout. Instead, we should abort
and enter a power down.
BUG=b:285980464
TEST=sequence now aborts and powers down on failure
Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This commit introduces a refactored version of the IVRS (I/O
Virtualization Reporting Structure) table generation. The main objective
of this refactoring is to generalize the process of generating the IVRS
table based on the IOMMU (Input/Output Memory Management Unit) domains
and their corresponding resources.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75451
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4c269248a3a1e078204882d04964fd5af4b5f51a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Daniel Maslowski <info@orangecms.org>
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BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: I6f3fa6543a4cec8c2562196105f17fbc7831bab7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch configures external V1p05/Vnn/VnnSx rails for Joxer
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:285477026
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Updating from commit id 9df5910:
2023-05-10 15:42:44 +0100 - (mb/starlabs/starbook/adl: Update EC binary to 1.13)
to commit id 797e7fc:
2023-06-10 03:59:43 +0000 - (00730F01/binaryPI: fix firmware table lookup)
This brings in 8 new commits:
797e7fc 00730F01/binaryPI: fix firmware table lookup
ba23e82 cpu/intel/stm: Use URLs so a link is generated
ecad6f8 cpu/intel/stm: Mark up file name as code/monospace
3434921 cpu/intel/stm: Use *firmware* over *BIOS*
a683e04 cpu/intel/stm: Use official spelling of *Kaby Lake*
ec80479 cpu/intel/stm: Remove blank line at end of README.md
22248b1 cpu/intel/stm: Remove blank line at start of README.md
475dce4 mb/google/utils: Add script to prepare PSP verstage for signing
Change-Id: I0005c3950bcbdf407c2abfc254123931806952f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Updating from commit id acf7395:
2023-01-10 11:27:48 -0800 - (phoenix: rename morgana to phoenix)
to commit id 1cd6ea5:
2023-05-20 10:00:36 -0700 - (mendocino: Upgrade SMU to 90.41.0)
This brings in 4 new commits:
1cd6ea5 mendocino: Upgrade SMU to 90.41.0
229fcf1 mendocino: Upgrade SMU to 90.40.0
8f2610c Add Mendocino FSP binaries
ebee2c1 mendocino: Upgrade SMU to 90.39.0
Change-Id: I7b40e3de15d4e2ad64274c267eec07c521b1b059
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75791
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 4c985e867:
2023-03-14 19:53:19 +0100 - (Merge "fix(cpus): workaround for Neoverse V1 errata 2743233" into integration)
to commit id c161772f4:
2023-06-08 15:47:09 +0200 - (Merge "refactor(el3-spmc): add emad_advance()" into integration)
This brings in 598 new commits.
Change-Id: I4008ebfffa1ff5176fa9cfe262cfd1598e6751c7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Updating from commit id 066e52e:
2022-10-04 14:04:23 +0000 - (Fix "unnecessary with of ancestor [-gnatwr]")
to commit id 732feb4:
2023-06-04 12:14:31 +0000 - (gma i2c: Update for Tiger Lake)
This brings in 17 new commits:
732feb4 gma i2c: Update for Tiger Lake
fc49b60 gma: Update PCH Rawclk programming for TGL
1b65b84 gma: Update BDSM register offset for TGL onwards
79a5379 gma pcode: Add Mailbox_Read procedure
b6df683 gma registers: Update for Tiger Lake and Alder Lake
24748f3 dp aux: Add support for TGL
e9631d8 gma: Begin Alder Lake (ADL) integration
605660b gma: Begin Tiger Lake (TGL) integration
0dadb67 gma pch-transcoder: Work around GNAT issue
fe80fbb common: Turn off VGA when not in use anymore
793f4f8 gma: Correct Global annotation for Initialize()
1dff38c gma: Make HW.GFX.GMA.SPLL package private
c68cafa gma skylake: Avoid aliasing of Config.State
17b513e gma: Shuffle warning justifications to support old and new tooling
3c1ac18 display probing: Update warning justification
b636d81 framebuffer filler: Extend loop invariant to assist prover
420e863 dp info: Provide Link_Status'Object_Size and padding
Change-Id: I17a95cc0b8e9dc4bffe8c82f0f53ee411281061b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75786
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id bdd55e4:
2022-08-11 13:59:07 +0200 - (Add json minify to remove comments in JSON files)
to commit id 567a1c9:
2023-01-18 20:38:13 +0100 - (Fix README.md uSWID table)
This brings in 5 new commits:
567a1c9 Fix README.md uSWID table
f5fd52f Add PlantUML Documentation
cd56b5b Add uSWID Documentation
1a294af Add more comprehensive example in README
b0e66ae Add plantuml output
Change-Id: Ib399578a20c5c64978edf4b6198439bf6983ea44
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Updating from commit id 65a6d94:
2019-07-17 17:47:14 -0600 - (Free image buffer on read error)
to commit id 80c499e:
2019-09-19 12:41:46 -0600 - (Correct spelling mistakes)
This brings in 1 new commits:
80c499e Correct spelling mistakes
Change-Id: I0557e7116052e98266ee1d078a078d698232bb2c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75798
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 33cc4f2:
2022-10-26 14:21:20 +0530 - (sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69)
to commit id a252198:
2023-05-23 11:00:31 +0000 - (sc7180/boot: Update qclib blobs binaries from 50 to 55)
This brings in 4 new commits:
a252198 sc7180/boot: Update qclib blobs binaries from 50 to 55
3fbd986 sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 50 to 69
7a3f064 sc7280/boot,shrm: Update qclib blobs binaries from 35 to 52
9884189 sc7280: Update AOP firmware to version 454
Change-Id: I938b768318d31d5e105d7c98823947cf8c02b195
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Starting with ccache 4.4 it is possible to collect statistics about
cache miss/hit rates in a separate file.
Add the info of the build at end of created make.log file or on stdout.
Change-Id: I1bab712712f4d6379ec6733fdc55b234e3845da7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All emulated targets properly compile and boot to the same extent as
with gcc.
Change-Id: I11ddd9347c2638fb7c26cd4939aa96ff8ddd1e66
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74571
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Daniel Maslowski <info@orangecms.org>
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Building with clang is currently broken as /usr/bin/ld.bfd is used
rather than the proper crosstoolchain linker.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Idd8006a26b2c2f9f777fdffe231c3c774320d805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75397
Reviewed-by: Daniel Maslowski <info@orangecms.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clang complains about the stack pointer register variable being
uninitialized. This can remediated by making the variable global. Change
the variable name to be more unambiguous.
Change-Id: I24602372833aa9d413bf396853b223263fd873ed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74570
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Daniel Maslowski <info@orangecms.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds a pointer to the README and to the wiki in the header of
board_status.sh.
Change-Id: I5877a3bf3544f175ac74a5e5a8e1ef1cab366ab8
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21569
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Make sure __always_inline is defined.
2. To test if we're on Linux, check presence of __linux__
instead of __GLIBC__.
Change-Id: I2ccfc4d2ef4c60877e24508f9926b533cffec0ed
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: Ib80efd7d1ba516cb0ae4bdb86f95877855195ce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63999
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This add's an option to use EDK2's Universal Payload instead
of the standard UefiPayloadPkg. Universal Payload requires
a ShimLayer, to build the required HOBs and pass them to Universal
Payload.
The ShimLayer is built to encompass UniveralPayload, so only
one ELF binary is added to coreboot.
Universal Payload is based on Intel's USF specification:
https://universalscalablefirmware.github.io/documentation/
This has been added with the repository pointing to
https://github.com/starlabsltd. The required ShimLayer patches
will be merged into edk2 master once corresponding coreboot
patches are merged.
This is because the EDK2 engineers believe it is an impossible
task to patch coreboot to build and use Universal Payload.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I17cc86d5eac0d5d91551ba5bea73fbc07ebdf0d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Properly shutdown NV12 rail in the off sequence (current
implementation leaves it asserted).
BUG=b:286287940
TEST=NV12 now shuts down on GCOFF entry
Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75533
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Hook up edk2 build flag PcdPcieResizableBarSupport to coreboot
Kconfig CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I5cc12d32c5e132b9f99ec650377d7683377c2a9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74926
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The stable version was over 5 years old. Update it to the current
main branch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic9cbe5e3dad9f2ff06e1fa8f0582d4c8b3e81a22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I08057576c23cef0343816c3b14c48db77b8dc416
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75695
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add pen detect support on the SOC pen detect GPIO.
BUG=b:286296762
TEST=Verify pen detect works on Myst
Change-Id: I922d643a83c5cd8ea0ab9fe6733f7aa05d935802
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I46d5caa0af95ec27fd49b0cf8fa704d656c89e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75684
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow spec[1] to modify WWAN power sequence. The WWAN power sequence
of warm reset is fail. The correct sequence is WWAN_EN should keep high when doing warm reset. Set GPP_D6 to PWROK which is not to do PAD
reset when warm reset.
[1]:
[JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing
Review_V1.6_20230602.xlsx
BUG=b:285065375
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power sequence meets spec.
Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75690
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable wifi sar function for yavilla/yavilly/yavijo.
Use the fw_config to separate SAR setting for different wifi card.
BUG=b:286141046
BRANCH=firmware-nissa-15217.B
TEST=build, enabled iwlwifi debug, and check dmesg
Change-Id: I1bd111a734a250df49535a07ef056d5b68fccb33
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add new memory parts
DRAM Part Name ID to assign
Hynix H58G66AK6BX070 3 (0011)
Hynix H9JCNNNFA5MLYR-N6E 4 (0100)
Micron MT62F2G32D8DR-031 WT:B 4 (0100)
BUG=b:279325772
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id
Change-Id: I2e6a916de08e7c05e95909d2b69bc839d13192d9
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74713
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
The memory parts being added are:
1. K4U6E3S4AB-MGCL
2. K4UBE3D4AB-MGCL
BUG=b:285504022
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I87a4dcdb6196c3ca7bed4b5c1bc654297339c16d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75605
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The file VGA_BIOS_FILE points to is right now the Mendocino VBIOS. Since
the default value probably shouldn't point to a location in site-local,
drop this for now, but leave a TODO to put that back once the correct
VBIOS files are available in 3rdparty/amd_blobs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifbc6cbe1e371d8d247f86555a5361ed237897dea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Instead of adding the new PCI IDs of the XHCI controllers in every new
chip generation to the pci_xhci driver, bind the driver to the internal
PCI devices of the XHCI controllers via the device ops statement in the
chipset devicetree. The PCI device function of the XHCI2 controller in
Mendocino can be either a dummy device or the XHCI controller, so the
device ops are attached to that device in the mainboard devicetree
instead. The Glinda code is right now just a copy of the Mendocino code,
so it'll change in the future, but for consistency the equivalent
changes to those in Mendocino are applied there too.
Since the device ops are now attached to the devices via the static
devicetree entry, also remove both the xhci_pci_driver struct and the
amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c.
TEST=SSDT entries for the XHCI controllers are still generated on
Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Initialize the SPI Flash in bootblock to ensure that
CONFIG_SPI_FLASH_EXIT_4_BYTE_ADDR_MODE will exit 4-byte addressing mode.
BUG=b:285110121
TEST=boot myst and verify flash operations work correctly
Change-Id: Ia88d2b46884b096b4c558bc86513159ec6d35eb5
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75588
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM.
BUG=b:216393391
TEST=build pass
Change-Id: I0abf1f1105f9a6f16af23b0ed3eb4faeb669eee6
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75716
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Include the GPU ACPI methods for all of Hades baseboard.
BUG=b:285981616
TEST=built for Hades and verify shutdown works
Change-Id: Iec3c4b59a9e7a9d4a902db51d40b60e114521774
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The PCI root complex itself isn't on an enumerable bus, so without
providing an _STA method, the device will still be assumed to be present
and visible, so this won't change behavior. This also brings Stoneyridge
more in line with the newer SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I663c7bcba89ffe25d0819d83461cb95e10f49028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75671
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCI root complex itself isn't on an enumerable bus, so without
providing an _STA method, the device will still be assumed to be present
and visible, so this won't change behavior. This also brings Picasso
more in line with Cezanne and newer SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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