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authorJon Murphy <jpmurphy@google.com>2023-06-08 15:05:49 -0600
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2023-06-13 23:55:48 +0000
commit5da5156ce3a1e32230d03da4eee37c45eaef896a (patch)
treea66b5b0007175c35183f82502a5ef81a7729640b
parent86e05e8e7309a927271d5dbeca5c83d3a74fe513 (diff)
mb/google/myst: Update PCIE_RST_L drive
PCIE_RST_L is attached to a pull down, change the init to NC. BUG=None TEST=Boot to OS Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75700 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/myst/variants/baseboard/gpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c
index f97cc16459..d6cbe1e194 100644
--- a/src/mainboard/google/myst/variants/baseboard/gpio.c
+++ b/src/mainboard/google/myst/variants/baseboard/gpio.c
@@ -52,7 +52,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_NC(GPIO_24),
/* GPIO_25-26: Not available */
/* SOC_PCIE_RST1_R_L */
- PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
+ PAD_NC(GPIO_27),
/* GPIO_28: Not available */
/* SD_AUX_RST */
PAD_GPO(GPIO_29, LOW),