summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2022-12-22mb/google/volteer: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple volteer variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I0448d12a36f522b715e1fbeb8d37eb5a925ebc93 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71183 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Set touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I269361f90a838d7766ad429afe82ef885f0d9371 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71182 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on volteer variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: Ie4c3b94594253ced6a875af78e6390cda8dcbc7d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71181 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Ib3c2a0e849006b7bf70cbd0bf6f32aa01ccf1bc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71180 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/starlabs/*: Bind console serial output to EDK2_DEBUGSean Rhodes
Configure the UART port but only enable UART debug for EDK2 debug builds. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I54e1dc5768fd765254c7ede91eaa45842fed3bd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69322 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22inc/dev/pci_def.h: add definitions for RCEC EA Ext. CapbilityJonathan Zhang
Root Complex Event Collector Endpoint Association Extended Capability is defined in section 7.9.10 of PCIe 5.0 spec. Add its Extended Capability ID, association bitmap for RCiEPs register, and RCEC associated bus numbers register. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7bede8ed88304a2925e6e1e4128bcdd625ee0e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/xeon_sp: Move codes to support new PCHTim Chu
Different PCHs have different definitions for registers. Here create a lbg folder and move lbg specific codes to this folder so that we can add new PCH code under xeon_sp folder. * Create lbg folder and move lbg specific codes from pch.c to soc_pch.c under lbg folder. * Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg folder. * Rename gpio.c to soc_gpio.c and move to lbg folder. * Move pcr_ids.h to lbg folder. * Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg folder. * Create and revise makefile for files under lbg folder. TEST=Can boot into OS on OCP Delta Lake. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22doc/mb/ocp/deltalake: add section on how to work on corebootJonathan Zhang
Update Delta Lake documentation to add some clarification. Add a section on how to work on coreboot for the Delta Lake server. Change-Id: Id756ee0a09cdcd1200752a03e980441db1537ad1 Signed-off-by: Jonzhang Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/meteorlake: Add ASPM setting in pcie_rp_configDinesh Gehlot
This change provides config for devicetree to control ASPM per port TEST=Build and Boot verified on google/rex Port of 'commit 6e52c1da4a22 ("soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config)' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I284bf51628193aa5f82f21fbf29c57a6ea5f9cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70661 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22drivers/intel/fsp2_0: Don't include <commonlib/bsd/compiler.h>Elyes Haouas
<commonlib/bsd/compiler.h> is automatically included in all compilation units by the build system. (see Documentation/contributing/coding_style.md) Change-Id: I09ed0c5eb2054c3add026f200c0fd3f609f73197 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67905 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22drivers/ocp: add VPD processing frameworkJonathan Zhang
Add VPD processing framework to be shared by OCP mainboards: * define VPD configuration items in vpd.h. * add helper functions: ** get_bool_from_vpd() ** get_int_from_vpd_range() Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-12-22soc/intel/xeon_sp: Lock down LPC configurationJonathan Zhang
For LPC, set BIOS interface lock. Also set the LPC BIOS control to match the SPI BIOS control settings. BIOS control EISS and WPD are set when the BOOTMEDIA_SMM_BWP config option is set. Change-Id: I3e3edc63c0d43b11b0999239ea49304772a05275 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-12-22soc/intel/alderlake: Add Raptor Lake device IDsMarx Wang
Add system agent ID for RPL QDF#Q2MB/Q2PS TEST=able to build coreboot successfully Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22mb/skyrim/var/frostflow: enable dptc tablet mode switchChris.Wang
add dptc power parameter for tablet mode sustained_power_limit_mW_tablet : 12w BUG=b:257187831 BRANCH=none TEST= validate the parameter changes for each mode by AGT Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I22d3f9c79a1eaaccfbef3766019516edb3523964 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70674 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-12-22coreboot_tables: Make existing alignment conventions more explicitJulius Werner
There seem to be some recurring vague concerns about the alignment of coreboot table entries. While the existing implementation has been producing tables with a well-defined alignment (4 bytes) for a long time, the code doesn't always make it very clear. This patch adds an explicit constant to codify that alignment, assertions to check it after each entry, and adds explicit padding to the few entry structures that were relying on compiler padding to return a correct sizeof() value. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaeef29ef255047a855066469e03b5481812e5975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70158 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2022-12-22soc/intel/meteorlake: Disable L1 substates for PCIe compliance test modeSubrata Banik
Disable L1 substates for PCIe compliance test mode in order to get continuous clock output. This patch is backported from commit 8c46232005767ecbdebb7290f15cacf2756c9586 (soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I490a3e8158472fdd3bbc1aec74b2658b0fab56e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71169 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-22soc/intel: Set `use_eisa_hids` based on `DPTF_USE_EISA_HID` configSubrata Banik
This patch avoids hardcoding to the `use_eisa_hids` variable instead relying on the SoC config to choose if the SoC platform supports EISA HID. If any SoC platform has the support then the `use_eisa_hids` variable would be set to `true` based on the selection of `DPTF_USE_EISA_HID` config. Note: Prior to Tiger Lake, all DPTF devices used 7-character EISA IDs. If selected, the 7-character _HIDs will be emitted, otherwise, it will use the "new" style, which are regular 8-character _HIDs. Ideally, the platform prior to Tiger Lake would set `use_eisa_hids` to `true` and platform posts that would set `use_eisa_hids` to `false`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I869bebc8e17c1e65979ca3431308d69771a34fa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/{apl,cnl,jsl}: Enable EISA HID support for DPTFSubrata Banik
This patch selects `HAVE_DPTF_EISA_HID` config for APL, CNL and JSL platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice01c5720ba7f15861899d89981225cb76f9fcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71109 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22drivers/intel/dptf: Add new config for EISA HID supportSubrata Banik
This patch adds config to let SoC users (config) to choose if EISA HID is supported. All SoC config would like to support EISA HID need to select `HAVE_DPTF_EISA_HID` config. Prior to Tiger Lake, all DPTF devices used 7-character EISA IDs. If selected, the 7-character _HIDs will be emitted, otherwise, it will use the "new" style, which are regular 8-character _HIDs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6bf64f74c447b28665d31a64181c33df882d5d06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71108 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/tigerlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Volteer. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I111fa9b2672ad01268bb2620b47a53a7a5b00f3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71107 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/jasperlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibb31ab29c803dde70ef9ccf2b7c7c2ca0845b568 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71106 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/cannonlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Hatch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7a9218a41825d2fa40a1c1b96a333465b7f617c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71105 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/apollolake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Reef. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0ce956351afc06871c465b67f51cba8786ce52db Reviewed-on: https://review.coreboot.org/c/coreboot/+/71104 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/alderlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ied32eb301b0702ad7cf12b662886c9060415eb72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71103 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/elkhartlake: Add DPTF ACPI Device IDs into header fileSubrata Banik
This patch adds DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia4c3f1dbca2c0099cbf00137008c1aa1bcb196b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71125 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22drivers/intel/dptf: Add `soc_` prefix for `get_dptf_platform_info()`Subrata Banik
This patch makes the SoC specific callback code more readable by adding `soc_` prefix into the `get_dptf_platform_info()`. In nutshell this patch renames `get_dptf_platform_info()` to `soc_get_dptf_platform_info()`. TEST=Able to build Google/Rex without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-12-22soc/intel/meteorlake: Update scaling factor MTL big coreSridhar Siricilla
The patch updates the scaling factor for MTL big core. TEST=Build the Rex code Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ife069fb29f4e913c5ef1af1f719b3392a70c55c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70355 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/mediatek: Move dapc_init to commonYidi Lin
dapc_init flow is the same on MT8186, MT8188 and MT8195. So move this function to common/devapc.c TEST=emerge-corsola coreboot; emerge-cherry coreboot; emerge-geralt coreboot TEST=devapc log is shown as expected and the system boots to kernel Change-Id: I979c3a3721a82d40c9e2db7fbe62e14a9bbd53d8 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71137 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-22lib/device_tree.c: Change log level messageElyes Haouas
Move a "NOTE" message from BIOS_DEBUG to BIOS_NOTICE log level. Change-Id: If92c1ccb5b10a4b29a5006a41ebd0855294f354e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69498 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22payloads/libpayload/arch/x86/rom_media.c: Change log level messageElyes Haouas
Move a warning message from BIOS_INFO to BIOS_WARNING log level. Change-Id: I4210901a183b54e47fa62a6146ce754c544aab2c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71157 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22nb/intel/sandybridge/raminit_common.h: Add needed <device/dram/ddr3.h>Elyes Haouas
Change-Id: I059e94ef46fdc959a6e37365eb335409698b987a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22mb/google/nissa/var/yaviks: Extend sd_hold for touchpad/touchscreenWisley Chen
Extend sd_hold to meet touchpad/touchscreen SPEC. touchscreen: tHD > 0.2 us touchpad: 0.3 us < tHD < 0.9 us After applied the change, the tHD meets reqirement. touchscreen: 0.056 us -> 0.28 us touchpad: 0.056 us -> 0.384 us BUG=b:263340540 TEST=build and measure the timing meet SPEC Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I172d2ec8a4b16d8005106f55a37795cc72d69e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization errorLeo Chou
Configure eMMC DLL tuning values for Pujjo board Kioxia sku. BUG=b:261676386 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I46991f26571771620dcd94b90e1112484ade63bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-12-21soc/intel/meteorlake: Select INTEL_GMA_OPREGION_2_1Dinesh Gehlot
Meteor Lake supports IGD Opregion version 2.1. BUG=b:190019970 (for alderlake) BRANCH=None TEST=Build and Boot verified on google/rex Port of 'commit 81d367feee13 ("soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I89e42b481834ed5ab35909b31b76215eaf8c7b36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-21treewide: Remove duplicated includesElyes Haouas
<types.h> provides <commonlib/bsd/cb_err.h>, <stdint.h> and <stddef.h>. Change-Id: I966303336e604b1b945df77e5d4c3cccbf045c56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-21security/vboot: Drop assert call from vbnv_udc_enable_flag()Sridhar Siricilla
It's true that vbnv_udc_enable_flag() is called after vbnv_init() (that's why the assertion was added). However, the former is called in the ramstage, while the latter in verstage. This means that vbnv_initialized will be false in ramstage, which leads to the assertion failure: [EMERG] ASSERTION ERROR: file 'src/security/vboot/vbnv.c', line 88 Since the ctx->nvdata will be restored in ramstage (by vb2api_reinit()), simply remove the assertion. So, the patch drops assert call from vbnv_udc_enable_flag() function. TEST=Verify Rex system boots to OS without assert error. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I49022155239febd5c5be5cf2c5eca2019ca61c12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-12-21mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKENick Vaccaro
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as kano is using a converged firmware image. BUG=b:253337338 BRANCH=firmware-brya-14505.B TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", disable hardware write protect and software write protect, flash and boot kano in end-of-manufacturing mode to kernel. Cq-Depend: chrome-internal:5246998, chromium:4119763 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I30ab7d829a6cb45b4e0cd38747501ba0eb6bd6cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71175 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21drivers/pc80/tpm: probe for TPM family of a deviceSergii Dmytruk
At the moment this is to handle the situation when device ID is the same for TPM1 and TPM2 versions of a device. Later this TPM family will be returned to the caller. Change-Id: I5464771836c66bcc441efb7189ded416b8f53827 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69023 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21drivers/spi/tpm: verify device supports TPM2Sergii Dmytruk
This is to handle the situation when device ID is the same for TPM1 and TPM2 versions of a device. Change-Id: Ib2840a21b3be8928d39570281f86a0e26b38b5f9 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69022 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21security/tpm/: turn tis_{init,open} into tis_probeSergii Dmytruk
Init was always followed by open and after successful initialization we need only send-receive function, which is now returned by tis_probe on success further reducing number of functions to export from drivers. Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68991 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21drivers/i2c/tpm: splice tpm_vendor_specific structSergii Dmytruk
Move `locality` field to `struct tpm_inf_dev` and put the rest directly into `tpm_chip`. Change-Id: Ic3644290963aca9f8dc7cd8ef754352865ef8d2c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-21soc/intel/skl; mb/google/eve,poppy: Update NHLT methodsMatt DeVillier
Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309. Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514 codecs to program the render and feedback slot numbers as appropriate. TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify audio functional with both Google project campfire drivers as well as coolstar's AVS audio drivers. Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-21lib/nhlt, soc/intel/skl: Update NHLT to program feedback configMatt DeVillier
Adapted from WIP (and abandoned) patch CB:25334, this patch: 1. Ensures SSP endpoint InstanceId is 0 2. Adds capability_size parameter at the end of the nhlt 3. Adsd more config_type enum values to accommodate feedback stream 4. Programs virtual_slot values for max98373, max98927, and rt5514 nhlt files 5. Adds NHLT feedback_config parameters Default feedback configs are added here to the max98373, max98927, and rt5514 codecs; in a follow-on patch, these will be overridden at the board level. TEST=tested with subsequent patch Change-Id: I59285e332de09bb448b0d67ad56c72a208588d47 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-21mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0Jan Samek
Remove the PSE TSN GbE device #0 as it's unused on the board and not visible during the PCI enumeration. Change-Id: I4a7d0e437c4f4a12d3a07564cddeafb7c697c6d3 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70700 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/siemens/mc_ehl3/mainboard.c: Remove XIO2001 register tweaksJan Samek
Contrary to mc_ehl2, which this variant is based on, this board doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the attempts to modify the bridge's registers unnecessary. Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21util/testing: Disable tegra and gitconfig tests until they're fixedMartin Roth
Both the tegra builds and the gitconfig tests are causing issues. They're disabled until someone fixes them. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1ed272e3579a2e7cdd6b58df24e719410d47082c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-21mb/google/octopus: Use runtime detection for touchscreens/digitizersMatt DeVillier
Switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens and digitizers. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. Test: build/boot Windows/Linux on various octopus variants, verify touchscreens/digitizers functional, dump ACPI tables and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I67c5bbae42e96ae21d37309e382b635321e6ef01 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63214 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I13bc6920a0dfaf769091b1764a7584902d1f85d6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63213 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Implement touchscreen/digitizer power sequencingMatt DeVillier
For octopus variants with a touchscreen/digitizer, drive the enable and reset GPIOs high in romstage, then disable the reset GPIOs in ramstage. Where available, only set the GPIOs for SKUs which have a touchscreen. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). TEST=tested with rest of patch train Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63212 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/amd/common/psp_verstage: Report previous boot statusKarthikeyan Ramasubramanian
Add support to report previous PSP boot failure to verified boot. This is required specifically on mainboards where the signed AMDFW blobs are excluded from vboot verification. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Corrupt either one of SIGNED_AMDFW_A/B sections or both the sections to ensure that the appropriate FW slot is chosen. Cq-Depend: chromium:4064425 Change-Id: Iada0ec7c373db75765ba42cb531b16c2236b6cc3 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70382 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUSKarthikeyan Ramasubramanian
Add an SVC command to get the previous boot status. If there is any pre-x86 boot failure in the previous boot cycle, PSP stores it in warm reset persistent register and triggers a warm reset. PSP verstage on the subsequent boot gets the previous boot status and reports any failure to the vboot before a FW slot is selected. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure scenario by corrupting certain firmware blobs and observe that PSP reports the failure boot status. On a normal boot, observed that PSP reports successful boot. Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21payloads/seabios: Update stable from 1.16.0 to 1.16.1Elyes Haouas
Short summary: - virtio-blk.{mmio,pci} and virtio-scsi.{mmio,pci} improved. - Several fixes and code refactor pci_config_*() functions. - Improved AML parsing. Change-Id: I04b35d006a2bcd1621e28ac2f1b12b9af99b7552 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71064 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/intel/mtlrvp: Enable ChromeOS build for mtlrvpHarsha B R
This patch enables building ChromeOS for mtlrvp. Patch includes, 1. Add cros_gpios for mtlrvp 2. Add chrome OS configuration in Kconfig 3. Add Chromeos.c BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train (CB: 69886) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/intel/meteorlake/romstage: Rewrite the if conditionSridhar Siricilla
The patch rewrites `if` condition by connecting two different conditions using the logical and(&&) operator without changing the semantics to improve the code readability. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2022-12-21soc/intel/{adl,mtl,tgl}: Drop unnecessary `dptf.asl`Subrata Banik
This patch drops unused `dptf.asl` from the latest IA SoC platforms as DPTF ACPI code generation is now relies on runtime aka SSDT rather than having fixed dptf.asl files to include inside the mainboard dsdt.asl. TEST=Able to build Google/Kano without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-21mb/google/skyrim: Fix Bluetooth configurationKarthikeyan Ramasubramanian
Power resource for Bluetooth device is not configured correctly in the device tree. Fix Bluetooth devicetree configuration. BUG=b:262785310 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able to connect to a Bluetooth headset. Change-Id: Id980424349537be35860dec04cc823d419cefe2f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/amd/mendocino: add dptc tablet mode supportChris.Wang
add dptc support for different power parameter on tablet/clamshell mode. BUG=b:257187831 BRANCH=none TEST=validate the parameter change for each mode by AGT. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20mb/google/skyrim/var/frostflow: Config I2C frequency for touchpad.Rex Chou
1.Config setting for touchpad I2C BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: 1.I2C0 (Touchpad): 385.7kHz Change-Id: I4ca72ee7fabd4b641eb17451ed8d942c5df52dde Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20soc/intel/xeon_sp: Set IA32_SMRR_PHYSMASK lock bitJohnny Lin
smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the same MSR that has been locked by another thread. Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock bit. Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-20mb/starlabs/starbook/adl: Set thermal trip based on power profileSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07be0aa2144b7718e28f1f675978b4b4b92752ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/69492 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/intel/cmn/block/cnvi: Add missing CNVI IDs for ADLKapil Porwal
Add missing CNVI IDs for ADL - ADL-P: 0x51f2, 0x51f3 ADL-S: 0x7af1, 0x7af2, 0x7af3 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I189be9a8c8895a93d98886e6591e771bbce5f564 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-20doc/contributing/coding_style: change example to use __fallthroughFelix Held
While the fall through comment is sufficient for gcc to notice that the fall-through is intentional, clang requires a special attribute which also works for gcc. Update the documentation to use this attribute instead of the comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I08dbac8ff1f9e04770a03fb74fabf0d397b50989 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71102 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-20soc/intel/*/crashlog.[ch]: Remove unused includesElyes Haouas
Change-Id: I126d49c27302e1ed2e00ff491d59cadda7101d12 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Add files required for ramstage and SMMHarsha B R
This patch adds files required for ramstage and SMM. 1. Add file required for ramstage (mainboard.c) 2. Add smihandler.c for SMM BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Enable EC for mtlrvpJamie Ryu
This patch will initialize EC for mtlrvp which includes, 1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC) 2. Add respective ACPI configuration 3. Add ec.c required for ramstage 4. Program EC ranges as part of devicetree.cb 5. Enable VBOOT in Kconfig BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with CHROME_EC using subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20src/soc: Remove unneeded <assert.h>Elyes Haouas
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-19Update intel-microcode submodule to upstream masterMartin Roth
Updating from commit id 6c0c469: 2022-05-10 15:51:47 -0700 - (Merge pull request #59 from esyr-rh/microcode-20220510-releasenote-fixes) to commit id 262f0c9: 2022-11-08 08:00:36 -0800 - (microcode-20221108 Release) This brings in 2 new commits: 262f0c9 microcode-20221108 Release cffdeb8 microcode-20220809 Release Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I92d2f68e99fe92e0b0f8c472a893fa6ea0e39958 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-19Update amd_blobs submodule to upstream masterMartin Roth
Updating from commit id 4ed38e5: 2022-10-25 15:14:53 -0700 - (glinda: add placeholder blobs) to commit id a2c1529: 2022-12-15 17:46:33 -0800 - (mendocino: Upgrade SMU to 90.35.166) This brings in 2 new commits: a2c1529 mendocino: Upgrade SMU to 90.35.166 2898385 Update Picasso FSP binaries Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie13237e2bc1a0c6552396410cb8470b7137f3a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-19Update fsp submodule to upstream masterMartin Roth
Updating from commit id 2047412: 2022-11-29 17:52:03 +0800 - (Elkhart Lake MR5 FSP) to commit id 6f2f17f: 2022-12-14 12:36:46 -0700 - (Deleted old Release Notes and Integration Guides) This brings in 6 new commits: 6f2f17f Deleted old Release Notes and Integration Guides 3868f73 Updated for SGXFlex - New UPDs available a649f0f Whitley FSP 2.2.0.3A f99be62 Merge branch 'master' of https://github.com/intel/FSP 1787bc7 Updated IoT ADL-PS MR1 (3404_00) FSP 1e833b0 Elkhart Lake MR5 FSP Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1dbd85ef06b057305428d42dd6cd6de0f2618439 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-19Update qc_blobs submodule to upstream masterMartin Roth
Updating from commit id e8efa5d: 2022-05-30 15:47:07 +0530 - (sc7180/boot: Update qclib blobs binaries from 44 to 46) to commit id 33cc4f2: 2022-10-26 14:21:20 +0530 - (sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69) This brings in 10 new commits: 33cc4f2 sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69 6c82214 sc7180/boot: Update qclib blobs binaries from 48 to 50 e570e02 Reland "sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063" 6206ab8 Revert "sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063" 82bbf78 sc7280/aop: Update aop blobs binaries and release notes version from 379 to 410 e3a760d sc7180/boot: Update qclib blobs binaries from 46 to 48 741abaa sc7280/boot/shrm: Update qclib blobs binaries from 30 to 35 436cb87 sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063 3f44ba0 sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes update from 044 to 050 eef51c6 sc7280/qcsec: Update qcsec blobs binaries and release notes for 27 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I72b91e384b74e4e44864ef5f29be78ebac4262fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-19tree: Replace Or(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b)` with `a | b`. Change-Id: I73842cd4843ebb0b48440059ae9dcf6c82235a76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70845 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19tree: Replace LAnd(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: I6b7b958e2d2a43926663a8dc8755613abb07e949 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70844 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19tree: Replace XOr(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `XOr (a, b, c)` with `c = a ^ b`, respectively `c ^= b` where possible. Change-Id: Ic5f67684bbd4ea115c4dae8a4417d88bea0d6b77 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70843 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19soc/intel/meteorlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. This patch is backported from commit 8409f156d588e74932924ae8aac69478a4b6388e (soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module) Change-Id: I7d9fb37ca1cd4bf325edc951ee7293e459fa2ea4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-19soc/intel/meteorlake: Implement MultiPhase SI Init Index 2 callbackSubrata Banik
The details about how the CPU multiprocessor init (MP) has migrated from coreboot to FSP can be found in https://doc.coreboot.org/soc/intel/mp_init/mp_init.html. The major reason behind this migration is to support the Intel proprietary and restricted CPU feature programming which can't be performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part of coreboot MP Init flow (prior to calling FSP-S). Hence, the new flow introduced with Tiger Lake platform forced having monolithic MP Init peformed by FSP (using coreboot MP PPI wrapper code). The last 3-4 years of FSP doing MP Init has demonstrated ample issues during platform bringup which is specific to UEFI MP Service implementation and not relevant to open source coreboot. This new flow makes the debug and validation aspect complicated where any FSP MP Init code changes should have been validated with coreboot MP PPI wrapper else might cause some failure, unfortunately, the validation commitment has never been met, hence, issue debugging is the only solution that remains in practice. Most importantly, the restricted feature programming which demanded closed source MP Init (for features like SGX and C6DRAM) has never been enabled in coreboot (starting with Alder Lake, the SGX feature has been dropped). This patch attempts to decouple FSP-S doing MP Init from the rest of the FSP-S silicon init and introduces 2nd MultiPhase SI init which allows bootloader to perform the mandatory SoC programming before FSP-S has done with PM programming (a.k.a set the reset CPL). The core/uncore BWG suggests the minimum SoC programming before BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2 to perform the required CPU programming before enabling the BIOS Reset CPL. This implementation would allow us to get rid of FSP running CPU feature programming and additionally make several EDK2 MP service modules optional (those are packed to create FSP-S blob). In summary, this change would allow coreboot to utilize open source MP init without running into FSP-S related code blocks. Note: At present, Intel Meteor Lake FSP doesn't have support for MultiPhase SI Init, Index 2 (submitted a FSP code changes over chrome-internal to enable this feature to decouple MP Init from FSP-S init). This patch is backported from commit b6c3a0325b9b0462cca81ea4134efb6b73756577 (soc/intel/alderlake: Implement MultiPhase SI Init Index 2 callback). BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Perform several thousands cycles of suspend test and power cycle without running into any issue. Change-Id: I2ea1a8bb2b142e39c2bc9d248b7fd0041366c0db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70558 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-19drivers/intel/fsp2_0: Implement `mps2_noop_get_number_of_processors()`Subrata Banik
This patch implements mps2_noop_get_number_of_processors() API with minimal information required for Intel MTL FSP to utilise the `MP_SERVICES_PPI_V2_NOOP` config. The major difference between Intel ADL and MTL FSP in terms of doing CPU feature programming aka utilizing MP PPI wrapper code is that, starting with MTL, FSP has dropped the `SkipMpInit` UPD. It means now, coreboot doesn't have any way to skip FSP doing MP Init operation. But during ADL, coreboot had introduced the MP_SERVICES_PPI_V2_NOOP config that is used to skip FSP about actually running any CPU feature programming on APs. The idea is to use the same config even in MTL to provide only the must have information (to bypass any assert in FSP during debug image) to FSP. Passing `FSP_UNSUPPORTED` from mps2_noop_get_number_of_processors() results in `assert` while compiling FSP in debug mode hence, implementing the function to pass only the information about BSP being the active processor along with passing `FSP_SUCCESS` (eventually it makes FSP happy and doesn't run into any issue in debug and/or release mode). TEST=Able to build and boot Google/Rex and Google/Kano while coreboot skip calling into FSP for doing MP init. Change-Id: I75d7e151699782210e86be564b0055d572cacc3f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70555 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-19ec/starlabs/merlin: Add EC related files for Cezanne laptopsSean Rhodes
Add EC memory layout and Q events for AMD Cezanne based boards, the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE 5570E. Change-Id: I87806b830b3d58a6ce3b89f45b5a07f4502a87f3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68333 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-19mb/google/octopus: Add NHLT endpoints for Cirrus Logic codecMatt DeVillier
Add NHLT endpoints for octopus boards using CS42L42 codec. Reuse method to add da7219 endpoint as the routing is identical. TEST=boot Windows, verify audio working with coolstar's audio drivers. Change-Id: Id68997073752f5d90b6fe21f666a6140e22d65eb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/octopus: update variant VBTsMatt DeVillier
Remove flag in VBTs for 'Use fixed resolution at boot' to allow FSP/GOP display init to use native panel resolution instead. TEST=build/boot multiple google/octopus variants with edk2 payload, verify boot logo not distorted/stretched. Change-Id: Ia31ff28379282619dfa22a955bee1a768bb54bb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/hatch/kohaku: set VBT boot resolution to 1080pMatt DeVillier
Boot menus are too small at native 4K res on some panels, so set fixed display resolution to 1920x1090p TEST=build/boot KOHAKU with 4K display, verify boot menu text legible. Change-Id: I82563c83de7ab302151f60d86b8a6824330d03ea Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/brya/var/marasov: Configure I2C high and low timeFrank Chu
Adjust I2C speed for codec, TPM, touchpad, touchscreen. BUG=b:260565911 TEST=Built and verified adjusted I2C speed Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2022-12-18util/crossgcc: Add option to get packages from coreboot's mirrorMartin Roth
coreboot has been keeping a mirror of all the toolchain packages used for releases for quite a while now. This adds an option to fetch the packages from the coreboot mirror directly to buildgcc. This can help with both our releases and when one of the various servers experiences interruptions or changes a path. To do this, the URL and filename needed to be split apart, which led to quite a few changes in the buildgcc script. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-17lib: Hook up libhwbase in romstageJeremy Compostella
It's hidden behind the configuration option `CONFIG_ROMSTAGE_LIBHWBASE'. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. Running Ada code in romstage and more particular libhwbase brings a few challenges as global initialized variables are not supported in Cache-As-Ram mode. 1. The libhwbase dynamic mmio driver implementation makes the Gnat compiler generate some global initialized variables. For this reason, when compiled for romstage or for romstage and ramstage the static mmio driver is enforced (`HWBASE_STATIC_MMIO'). 2. The Gnat compiler generates elaboration functions to initialize program data at runtime. These elaboration functions are called by the romstage_adainit() function. The data references symbols suffixed by `_E'. Even though these symbols, at compilation time, do not contain any data and are filled with zeros, the Gnat compiler installs them in the .data section. Since these symbols are actually filled with zeros, it is safe to install them in the .bss section. cf. https://docs.adacore.com/gnat_ugn-docs/html/gnat_ugn/gnat_ugn/elaboration_order_handling_in_gnat.html#elaboration-code This patch requires the libhwbase https://review.coreboot.org/c/libhwbase/+/69854 CL. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libhwbae compiles for romstage and loads successfully Change-Id: I670249d33506e886a683e55d1589cb2bf9b16aa3 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70275 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17Add option to use Ada code in romstageJeremy Compostella
If selected, libgnat is linked into romstage. In addition, a call to romstage_adainit() is added to support Ada program data initialization. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Ada code compiles for romstage and loads successfully Change-Id: I74f0460f6b14fde2b4bd6391e1782b2e5b217707 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70274 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17util/chromeos/gen_test_hwid.sh: Replace usage of hexdumpMichał Żygowski
Hexdump command is not available in coreboot-sdk. Replace it with equivalent implementation using commands that are present in the container. TEST=Passed "VP46XX" as prefix variable and it produced the same crc32 result before and after the change. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Icad93933335b8c5ebd8fee74cc9aaed36bb56482 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-17soc/intel/cmn: Clear interrupt status after HECI-1 has been receivedJohnny Lin
According to Intel doc#630774, BIOS should clear Host Interrupt Status if it has read all the slots of the message from the ME circular buffer. Since this is not found in client ME document, add a Kconfig SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server ME SKU. On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the change can avoid seeing below Linux warning during boot with Linux v5.12: [ 17.868929] irq 16: nobody cared (try booting with the "irqpoll" option) [ 17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0 [ 17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1 [ 17.922327] Call Trace: [ 17.927780] <IRQ> [ 17.932253] dump_stack+0x64/0x7c [ 17.939640] __report_bad_irq+0x37/0xb1 [ 17.948206] note_interrupt.cold.11+0xa/0x63 [ 17.957713] handle_irq_event_percpu+0x6a/0x80 [ 17.967626] handle_irq_event+0x2a/0x50 [ 17.976163] handle_fasteoi_irq+0x9e/0x140 [ 17.985305] __common_interrupt+0x38/0x90 [ 17.994255] common_interrupt+0x7a/0xa0 [ 18.002821] </IRQ> [ 18.007514] asm_common_interrupt+0x1e/0x40 Change-Id: I1cf21112870e53a11134d43e461b735ead239717 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17lib: Introduce fw_config_get_fieldEric Lai
In some cases, fw_config is used for ids like sar_id, sku_id etc. To avoid calling fw_config_probe over and over, hence provide the method to return the value then caller can use the switch case instead of if else statement. TEST=get fw_config field value on nivviks. [INFO ] fw_config get field name=DB_USB, mask=0x3, shift=0, value =0x1 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iae89668e8fe7322d5a4dcbf88a97d7ed36619af5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17util/cbfstool: Change %lu to %zu for size_t argumentReka Norman
With commit 34a7e66faa46 ("util/cbfstool: Add a new mechanism to provide a memory map"), builds are failing on 32-bit platforms with: ../cbfstool/cbfstool.c:397:30: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] printf("Image SIZE %lu\n", image_size); ~~~ ^~~~~~~~~~ %zu Change the format specifier from %lu to %zu. TEST=`emerge-cherry coreboot-utils` now succeeds Change-Id: I3602f57cf91c330122019bfa921faef6deb2b4ce Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70848 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-17mb/siemens/mc_ehl3/devicetree.cb: Adapt PCIe root port settingsJan Samek
Based upon hardware differences from mc_ehl2, disable RP7 and enable RP3 and RP5. Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17mb/siemens/mc_ehl3: Add board variant based on mc_ehl2Jan Samek
Add a new mc_ehl variant, which is based on mc_ehl2 implementation. This patch uses a copy of mc_ehl2 with changes only in naming as a starting point for the new mc_ehl3 variant. Follow-up patches will introduce the functional changes against mc_ehl3. Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-17util/genbuild_h: Only use version tags in expected formatReka Norman
With commit 0110e1abe0ba ("util/genbuild_h: Update printf %d to %s for sh compatability"), the ChromeOS coreboot build is failing with: In file included from src/lib/version.c:4: /build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5473/work/build/nivviks/build.h:10:32: error: 'v1' undeclared here (not in a function) 10 | #define COREBOOT_MAJOR_VERSION v1 | ^~ src/lib/version.c:35:46: note: in expansion of macro 'COREBOOT_MAJOR_VERSION' 35 | const unsigned int coreboot_major_revision = COREBOOT_MAJOR_VERSION; | ^~~~~~~~~~~~~~~~~~~~~~ /build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5473/work/build/nivviks/build.h:11:32: error: 'v9308' undeclared here (not in a function) 11 | #define COREBOOT_MINOR_VERSION v9308 | ^~~~~ src/lib/version.c:36:46: note: in expansion of macro 'COREBOOT_MINOR_VERSION' 36 | const unsigned int coreboot_minor_revision = COREBOOT_MINOR_VERSION; | ^~~~~~~~~~~~~~~~~~~~~~ This is because the ChromeOS coreboot repo has a tag which is not in the expected <major>.<minor> format: $ git tag v1.9308_26_0.0.22 Change genbuild_h.sh to only use the version from `git describe` if it's in the expected <major>.<minor> format. TEST=ChromeOS coreboot build now succeeds, with versions set to 0: #define COREBOOT_MAJOR_VERSION 0 #define COREBOOT_MINOR_VERSION 0 Building upstream coreboot, the versions are still set correctly: #define COREBOOT_MAJOR_VERSION 4 #define COREBOOT_MINOR_VERSION 18 Change-Id: I81b2317a83cdec4cc2aad60af2990e5e3f4ad694 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Usha P <usha.p@intel.com>
2022-12-17soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE for ADL-NReka Norman
On nissa, sending EOP late improves boot time by about 57ms. Before (SOC_INTEL_CSE_SEND_EOP_EARLY): 943:after sending EOP to ME 931,206 (58,431) 943:after sending EOP to ME 932,911 (58,427) 943:after sending EOP to ME 930,908 (58,429) 943:after sending EOP to ME 941,357 (61,748) 943:after sending EOP to ME 933,289 (62,050) 943:after sending EOP to ME 939,578 (62,453) 943:after sending EOP to ME 932,491 (62,050) 943:after sending EOP to ME 929,693 (62,655) 943:after sending EOP to ME 942,247 (62,654) 943:after sending EOP to ME 936,984 (61,751) After (SOC_INTEL_CSE_SEND_EOP_LATE): 943:after sending EOP to ME 1,107,816 (3,498) 943:after sending EOP to ME 1,053,286 (25,212) 943:after sending EOP to ME 1,124,095 (3,511) 943:after sending EOP to ME 1,098,591 (3,498) 943:after sending EOP to ME 1,107,772 (3,499) 943:after sending EOP to ME 1,080,008 (45,969) 943:after sending EOP to ME 1,081,754 (8,024) 943:after sending EOP to ME 1,109,193 (4,102) 943:after sending EOP to ME 1,088,866 (4,201) 943:after sending EOP to ME 1,081,684 (4,203) BUG=b:247902068 TEST=EOP time is improved on nissa (measurements above). Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17tests/Makefile.inc: Build utilities in separate directoryJakub Czapiga
Utilities like kconfig/conf now will be built inside tests build tree. It will eliminate possible colisions of target names when using test framework in more than one place (see CB:70110) Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I4c1eb901c921f4ec6ee8985b154362153c5fd0e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70359 Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17tests/Makefile.common: Remove unnecessary dependency to kconfig/confJakub Czapiga
Utility will be built while executing kconfig targets so it is not necessary to keep hard dependency on kconfig here. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I578f3e1d9de63e91ded44746539265bcd55bf579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70298 Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17tests/Makefile.common: Allow to override tests defconfigJakub Czapiga
Some tools based on test framework might require defconfig other than one set in tests framework. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If53b9a54ef7389dd979dfe772e6946439f7d6a62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70109 Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17tests/Makefile.common: Describe available test attributesJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I8ce702b4be254e206e2018deabde985b56cc6cd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70475 Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17tests: Support linking with system libcJakub Czapiga
This patch allows for linking selected files with system libc. This allows for creating libraries interacting with filesystem, standard I/O and other parts of system. Until now it was only possible using CMocka proxy functions or functions not masked by code under test. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I652362ba61a25e974d706357fc36479ccee763e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com>
2022-12-17drivers/generic/nau8315: Change method for HID assignmentDavid Lin
This patch is to change method of HID assignment with compatible id style in nau8315_config and allow mainboards to set it. Signed-off-by: David Lin <CTLIN0@nuvoton.com> Change-Id: Ia6f02e495eeb06290947edc9e44fa25a4ce18956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69965 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-17mb/google/nissa/var/yaviks: Enable wifi SARWisley Chen
Enable wifi sar function for yaviks. Use the fw_config to separate SAR setting for different wifi card. BUG=259199095 TEST=build, enabled iwlwifi debug, and check dmesg Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 02:44:01 +0000