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Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
TEST=boot to OS, read PCI 0:0.0 config register 0x80, value is 0x31
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0c3e16edeab6f85a79eb10e1477d95952b554a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some FSPs provide a UPD to allow the bootloader to set the PAM lock bit
instead of the FSP, therefore add a function in the common code to do
this. Source: ADL & TGL FSP integration guides
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1d6642b496617b6e8ccda8a0aa6bfd88ea9dc3ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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WWAN_PERST_L (GPP_E0) is wrongly configured to NC in ramstage.
So, remove it.
BUG=b:192052098
TEST=FW_NAME=redrix emerge-brya coreboot
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: If8e96045a0d78a942f77d8d8e371ab75dff0c202
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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4 MAX98390 Speaker Amps are connected to i2c0 and device addresses are
0x38/0x39/0x3a/0x3b
BUG=b:191931762
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ie8f01e6a7e09e18f6d34f3ceb1db8e2e238197bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57114
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename soc_validate_fsp_version to soc_validate_fspm_header, since it
can not only be used to check the version info in the FSP-M binary's
header, but also to check every other field in the binary's header. This
is a preparation for a follow-up patch that implements this function to
check the FSP-M binary's size.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The FSP-M binary needs to fit into the memory region that starts at
FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time
if the uncompressed FSP-M file is larger than the size of the region it
will be copied into.
BUG=b:186149011
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Sounds like we prefer to have this under drivers/ instead of device/.
Also move all MIPI-related headers out from device/ into their own
directory.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Create the dewatt variant of the guybrush reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:196460993
BRANCH=None
TEST=util/abuild/abuild -p none -t google/guybrush -x -a
make sure the build includes GOOGLE_DEWATT
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: I57860a7cad1bf202bd3ef3eed5f498fbf1d29af8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57108
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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clang seems to like to do some aggressive optimizations that break our
approach of mocking functions for test by using objcopy to turn them
weak after the fact on individual compiled object files. For example, in
CB:56601 the function cbfs_get_boot_device() is mocked this way. When
compiling the cbfs_boot_lookup() function in src/lib/cbfs.c with clang,
it will generate a normal callq instruction to a relocation for
cbfs_boot_lookup(), which can then later be pointed to the mocked
version of that function. However, it will also somehow infer that the
version of cbfs_boot_lookup() in that file can only ever return a
pointer to the static local `ro` variable (because CONFIG_VBOOT is
disabled in the environment for that particular test), and instead
generate instructions that directly load the address of a relocation for
that variable into %rdi for the following call to cbfs_lookup(), rather
than using the real function return value. (Why it would do that is
anyone's guess because this seems unlikely to be faster than just moving
the function return value from %rax into %rdi like a normal compiler.)
Long story short, this optimization breaks our tests because
cbfs_lookup() will be called with the wrong pointer. clang doesn't
provide many options to disable individual optimizations, so the only
solution seems to be to make clang aware that the function is weak
during the compilation stage already, so it can be aware that it may get
replaced. This patch implements that by marking the mocked functions
weak via #pragma weak lines in the per-test autogenerated config header.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1f9011f444248544de7a71bbefc54edc006ae0cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Change-Id: I3bea9e1f9cc25a4476ddbaa8bd8e434609eb28f7
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Iec6ec8bbf3cc5c9230ba6bcb0126ff6085f26464
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Cannon Point PCH-H does not implement the eMMC, I2C4 and I2C5 devices.
Guard the IRQ constraints for these devices to prevent FSP assertions.
Tested on Prodrive Hermes, debug FSP builds no longer fail to boot.
Change-Id: I58674d1c3c5fe4535c022020674d48d6a5315bf9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. According to the Maxim's comment and schematic diagram of proto, Modify I2C slave address to 0x38, 0x3c.
2. According to the schematic diagram of proto, Change GPD11 to NC.
BUG=b:191811888, b:1191213263
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ibf8adf2ed8dda9ae6da06e7e995bef9395cdee35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57059
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Touchscreen will be no function with R93-14092.19.0 image or be later.
It just happened to work because elants_i2c driver would bind
to the device first based on "ELAN0001" HID ID
BUG=b:195994810
TEST= verify only update RW FW can fix touchscreen no function issue
1.Build test firmware
2.prepare DUT enviroment (R93 image + update RW to test firmware)
3.verify touchscreen function normally
Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ie9e0fe726854d0128ad1bb430544640dc8f034ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
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Update DPTF parameters from internal thermal team.
BUG=b:180875580
BRANCH=dedede
TEST=emerge-dedede coreboot
Change-Id: I06d8a543dbd77137cb97c4ea695a1f2b9f8ee76c
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57116
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:192052098
TEST=FW_NAME=redrix emerge-brya coreboot
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I45ecab8c036a7e75cc0c564867119c027175ed06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook up microcode from 3rdparty repo for:
- 06-8d-01 (CPUID signature: 0x806d1)
Verified microcode blob was found in CBFS on system76/gaze16 (TGL-H).
CBFS: Found 'cpu_microcode_blob.bin' @0x11700 size 0x18400 in mcache @0x76c2d0ac
microcode: sig=0x806d1 pf=0x2 revision=0x2c
Change-Id: Icf0d8bc700a73697f06503e9d1bb40ce26741cdf
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57067
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Primus has MX98360A, which Linux kernel 5.10 currently does not support
and, therefore, audio does not work. As the device is compatible with
the MX98357A, use that until Linux’ SoF driver supports the new version
(https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268).
BUG=b:194749863
BRANCH=none
TEST=build coreboot and audio function works
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I893d9a31dc2c7726599c150be01b9585fb6c8a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Commit e7f3e6a0558 added PL4 limits for brya0, but the units were mW,
whereas the `tdp_pl4` field is expected to be in whole Watts, therefore
divide all of the settings by 1000.
BUG=b:197468828
TEST=boot brya0 to OS
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6da6bae4eb8c83188d813828cdc4f7c1e20f1b5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Init basic override devicetree based on schematics
BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I283517427612e24eabe2ce736d677253065c7859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch enabled the SaGv support for brya0 baseboard.
BUG=b:187446498
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I2a71e159fa49f677660af8279f2b582a3916eee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable DRIVERS_GENESYSLOGIC_GL9755 support for primus.
BUG=b:195611000
BRANCH=None
TEST=build pass
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I0c60979a2d42f836e0f0261c42fcfc36c41e113a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add G2Touch G7500 touchscreen into devicetree for cret.
BUG=b:180547621
BRANCH=dedede
TEST=Built cret firmware and verified touchscreen function.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I57638bf8a3eb4efcd819f5433fa54c22b7af3054
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add the support RAM parts for felwinter.
Here is the ram part number list:
DRAM Part Name ID to assign
K4U6E3S4AA-MGCR 0 (0000)
K4UBE3D4AA-MGCR 1 (0001)
H9HCNNNBKMMLXR-NEE 0 (0000)
MT53E1G32D2NP-046 WT:A 2 (0010)
BUG=b:197308861
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I76febefc251b02a047819242e23c02dc50891c2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Prepare to confine all `pei_data` references in raminit.c and refcode.c
so that mainboards don't need to know about its existence.
Change-Id: I55793fa274f8100643855466b6cca486896fb2c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55801
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Do early ME init before adding the "start of raminit" timestamp.
Change-Id: If8b27a9d4eb3b801e3e05dc2f2b95bf748985707
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55800
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia1c1c3d172366ddcc8c194cb2e0b0c2fb2acf678
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I9a316b91b31166831f23eaf9e271a7d67ac4ccff
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ie8a28d8e03d7176df5409e6cb507a0a802ff026f
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56951
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I89e300adce2edeb9d9c2bba1782c212ee656a532
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add TGL-H GPIO definitions, based on existing TGL definitions and how
CNP/CNP-H handles the split.
Reference:
- Intel doc 619207
- TigerLake FSP
- linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Reference:
- TigerLake FSP
Change-Id: I666eb710762f6b00d173ee1a473f1f5a612953a6
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Based on the base TGL devicetree, add one specific to TGL-H that adds
the additional supported devices.
Introduces a new Kconfig for selecting the PCH support.
Reference:
- Intel doc 615985
Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Convert the power limit defines to an enum and add TGL-H entries.
Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56942
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 68d8357dab55660058ad1ab8dca34fd03e0adbb5.
Reason for revert: Device NVS is expected by mainboard samus
in payload depthcharge:
https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icb5fa6da3412a51aae56c3658163e5b98d57bab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit 34bd6ba97917b0bc54bb1f1e106a56b5c03e19ac.
Reason for revert: Device NVS is expected by mainboard samus
in payload depthcharge:
https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60
Not reverted:
* ACPI_HAS_DEVICE_NVS does not exist anymore in ToT and hence it's
selection in broadwell is not required.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic31d7ae62c5df72708b724160e96e10b46002eb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Create the moonbuggy variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=191356135
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_MOONBUGGY
Signed-off-by: Rehan Ghori <rehang@google.com>
Change-Id: Iaf545dcd5ff537afdf029f510553d16a1239763e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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gooey is the same design as boten, and differs only in replacing Cr50
with discrete TPM.
BUG=b:193366710, 197247706
TEST=FW_NAME=gooey emerge-keeby coreboot
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I2a54f872a7d5c0bee76a9e6e309613d9357b380b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/
Also, the license is changed from GPL to BSD.
This is because it is needed from "utils" (see CL in the chain).
For reference bin2bcd() & bcd2bin() are very simple functions.
There are already BSD implementations, like these ones (just to
name a few):
https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/include/lib/math.h#67
http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
BUG=b:172210863
TEST=make (everything compiled Ok).
Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56904
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables L1.1 and L1.2 on all real Guybrush PCIe devices.
BUG=b:188123142
TEST=Boot to ChromeOS and verify L1SS are functional by dumping the
settings with "lspci -vv". Leave system on for 20 minutes and no hang.
Also perform 20 reboots and suspend operations
Cq-Depend: chrome-internal:4012927
Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Override GPIO pad configurations based on the latest bugzzy schematics.
BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image and boot on bugzzy board
Change-Id: I7c3580e7eb34efed0441ead243343d2d7875d50f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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To reduce suspend power consumption,
1. Disable unused CLKSQ2.
2. Set CLKSQ_EN to sleep control for SPM 26M sleep control.
No bus clock when enter 26m sleep control, and only control
clock square by side band.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: Ia9a1735d6f508ce35b9af2d67831a3474255198b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57043
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add HDMI low power setting to reduce power consumption.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ica91645789e5de3401131e7050d2b1ee06c535dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57042
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id3eb18cae2dd9a7b148bc9f3dcaf387f35dbd2fb
Fixes: 312fb716 ("mb/google/brya: Add ALC1019_NAU88L25B support")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Also add a config file to ensure the code gets build-tested.
Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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IDS (Integrated Debug Services) options are meant to be enabled when one
wants to debug AGESA. Since they are compile-time options, using Kconfig
is the logical choice. Currently, none of the options builds.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and Asus A88XM-E does not change.
Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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|
Subsequent commits will add Kconfig options to configure IDS.
Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical.
Change-Id: I861762280b274566ce14969a30e2e0c98e120a69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
|
|
The `ASSERT` macro is already defined in `src/include/assert.h`, and
AGESA's definition is never used. On Asus A88XM-E, toggling the value of
the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary
when using reproducible builds. Attempting to use AGESA's definition of
the `ASSERT` macro results in build errors:
In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info':
src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value]
#define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
Given that coreboot's definition of `ASSERT` is more useful, drop
AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro.
Also remove the `IdsAssert` function, as it is no longer used anywhere.
Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical.
Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
|
|
In preparation to replace OptionsIds.h with Kconfig options, use the
same settings on all AGESA f15tn boards. The only difference this makes
is that the `IDS_LATE_RUN_AP_TASK` macro no longer expands to nothing.
It is expected that the impact this difference makes is minimal.
Note that the `IDSOPT_TRACING_ENABLED` option currently fails to build.
Tested on asus/f2a85-m, still boots.
Change-Id: Iedd4d1f255650012f3efd9a27718e18c1c904dc1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53982
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch changes the sc7180 boards to use the new common MIPI panel
framework, which allows more flexible initialization command packing and
sharing panel definitions between boards. (I'm taking the lane count
control back out again for now, since it seems we only ever want 4 for
now anyway, and if we ever have a need for a different lane count it's
not clear whether that should be a property of the board or the panel or
both. Better to leave that decision until we have a real use case.)
Also, the code was not written to deal with DCS commands that were not a
length divisible by 4 (it would read over the end of the command
buffer). The corresponding kernel driver seems to pad the command with
0xff instead, let's do the same here. (Also increase the maximum allowed
command length to 256 bytes, as per Qualcomm's recommendation.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add ALC1019_NAU88L25B DB support.
BUG=b:195891240
TEST=audio is functional when playing youtube.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9209c4cab00fc03b2a6107b5c32804786cd2e242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Update SKU specific power limits for ADL-M as per document 643775.
BUG=None
BRANCH=None
Change-Id: I40b9b3a508c549d940e1c2c9e8b4079695b694e6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Update PCI ID for ADL-M as per document 643775.
BUG=None
BRANCH=None
Change-Id: Ia2c5ce270bc421d8a41cc4bc6ce0b51987d2aaec
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
An MST hub is only present on some devices that are configured with a
particular daughterboard indicated by EC fw_config, so add a fw_config
probe that matches the USB daughterboard ID from CBI to only enable it
on devices where present, using variant-specific daughterboard IDs.
BUG=b:185862297
TEST=RTD2141 remains in ACPI tables on a berknip with Dali DB, and is
not present on the same system if probe is changed to enable it
for picasso DB.
BRANCH=zork
Change-Id: I4ada9b492ab221fa98350bf2faf27a23342f3a55
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
PSP_Verstage will take almost the entire time to run that
is allotted to S0i3 resume. Since coreboot isn't running,
the PSP needs to handle any security requirements. The long-
term plan is that the PSP won't even load psp_verstage on S0i3
resume, but when it is loaded, this makes sure we exit
immediately
BUG=b:177064859
TEST=Verify that PSP_verstage doesn't run on S0i3 resume
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Change-Id: I8c8b49d519b7c6a3d1e4946818b2fc5a1dd1d3e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56663
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This reverts commit 66dbb0c5d67279722fcbcb547d9c6b61e606d50e.
The numbers were meant for Cannon Lake, but the code was also meant
to be used for all other platforms using the Cannon Point PCH. Now
Cannon Lake support is even dropped, so we can cleanly revert to the
recommended values for the other platforms.
Change-Id: Iea56c6a29ca4b34c9852393fed2e3be4de128ec6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56662
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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According to received feedback, FSP-T enables MMCONF at address
0xe0000000 with 256 busses. Sanity-check that Kconfig matches that.
Add MMCONF_BUS_NUMBER such that MCFG in ACPI will be correct.
Change-Id: I01309638a9f4ada71e5e3789db34892ed4abfa3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch enables eNEM flow for Alder Lake SoC hence drop INTEL_CAR_NEM
Kconfig from ADL-P RVP. ALDERLAKE_CAR_ENHANCED_NEM Kconfig will select all
relevant Kconfig required to enable eNEM for Alder Lake.
Additionally, select INTEL_CAR_NEM Kconfig for ADL-M RVPs from Kconfig.name.
BUG=b:168820083
TEST=Able to build and boot ADL-P RVP using eNEM mode.
Change-Id: I08561c8f50bbc4afe2bcdff4cc50e74d8fa2f68e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48345
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch decouples the selection of eNEM feature enablement from SoC
to ensure the ADLRVP does the validation first prior enabling this
feature on OEM/ODM reference designs.
BUG=b:168820083
TEST=No changing is being observed in .config with and without this CL.
Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Add the support RAM parts for Driblee.
Here is the ram part number list:
1. Hynix H9HCNNNBKMMLXR-NEE
2. Micron MT53E512M32D2NP-046 WT:F
3. Samsung K4U6E3S4AA-MGCR
4. Micron MT53E512M32D1NP-046 WT:B
BUG=b:195619346
BRANCH=keeby
TEST=emerge-keeby coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I683acb91ec13cbd772e732d7f81152ceb3cefc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56924
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature. This value is suggested by
Thermal team.
BUGb=b:195706434
BRANCH=None
TEST=Built for brya platform and verified the MSR value
Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Set default PL4 values for various Alder Lake CPU SKUs as per
bug#191906315 comment#10.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board.
Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56917
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add TGL-H PCI IDs from the Processor and PCH EDS docs.
Reference:
- Intel doc 615985
- Intel doc 575683
Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Use `strcpy()` instead of `memcpy()` to copy string literals.
Change-Id: I8ebf591e3348d992739ed7cc2e4015aa650f115a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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- Enable EN_PP3300_SD
- Configure SD_PE_RST_L correctly
BUG=b:195625340
TEST=Able to boot with SD card
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I33c17e88cabdc9b13634fc8f341aa6a09b7bfde5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
primus supports USB4 and so needs to reserve bus numbers and prefmem and
mem resources for potential hotplugs of devices.
BUG=b:193377625
BRANCH=None
TEST=build pass
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I1d1f8cc3460c1b89dade4f01690c77efcd799098
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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We're running out of SKU IDs in the base2 system, so convert it to
binary-first base3.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia7f749fa042d3eac76bfe1e74531905c6e279ad2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57004
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are gremlins in the system. thread_coop_enable has an assert. This
is currently problematic for two reasons.
assert(current->can_yield <= 0);
When doing smm_do_relocate we are entering a deadlock. The root cause
hasn't been quite found yet, but it's related to co-op multi-threading.
For some reason the assert in thread_coop_enable is firing when
releasing the console_lock spin lock. I'm assuming cpu_info hasn't been
initialized yet. The assert tries to perform a printk, but since the
console_lock is still held we end up in a dead lock. This dead lock will
generally not happen after a warm reset. Again I'm assuming because the
cpu_info struct has some valid values at this point.
For now disable multi-tasking until we fix the cpu_info initialization.
BUG=b:194391185
TEST=Boot guybrush to OS
Co-developed-by: nikolai.vyssotski@amd.corp-partner.google.com
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia3143f538a31b5aaaea104aa1d8bcf44e6dcb528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57005
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use correct format for constraint list as expected by kernel driver.
With this change, kernel is able to correctly list dummy device in
constraint list.
BUG=b:194687976
TEST=Build and boot to OS in Guybrush.
Change-Id: I7af1941ffd21cd5864c7285f44cb2d063d2f225f
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57012
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the `_HID` value of device in SSDT depending on the fw_config.
According to value of AUDIO_CODEC_SOURCE field in fw_config(SSFC) which
stored in CBI:
AUDIO_CODEC_ALC5682: _HID = "10EC5682" /* ALC5682I-VD */
AUDIO_CODEC_ALC5682I_VS: _HID = "RTL5682" /* ALC5682I-VS */
BUG=b:193623380
BRANCH=dedede
TEST=ALC5682I-VD or VS audio codec can work normally
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Ic8840454e4934162ea59c742634a56f70b153238
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Enable Skin Temperature Tracking with initial configuration settings.
BUG=b:190732595
TEST=Confirm that AGT tool can successfully complete data collection
Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55434
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All boards that are trying to use MIPI panels eventually run into the
problem that they need to store physical parameters and a list of DCS
initialization commands for each panel, and these commands can be very
different (e.g. a large amount of very short commands, a few very large
commands, etc.). Finding a data format to fit all these different cases
efficiently into the same structures keeps being a challenge, and the
Kukui mainboard already once put a lot of effort into designing a
clean, flexible and efficient solution for this. This patch moves that
framework into a common src/device/mipi/ library where it can be used by
other boards as well. (Also, this will hopefully allow us to save some
duplicated work when using the same panel on different boards at some
point.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idc4d98fd35d1b2f2d8165909c0fce141c6ca100d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56855
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Cezanne FSP headers are located in that directory, so add it to the
Cezanne SoC folders in the maintainers file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4f4894f0b01fa916492f57a730c62f29c5f7c796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The change from Synaptics S7817 to Elan 3915N and pin distribution
of touch IC is the same.
The original Elan section was copied from reference design and
was never used before.
According to vendor spec definition IRQ trigger method needs to
change to level.
BUG=b:190574692
TEST=Build coreboot and check that device works
Change-Id: I44ee779242779c78ceafdddd34dca2571e714dd3
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56380
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds the ability to output MSRs dump for the specified range of CPU
cores. This makes it easier to reverse engineer server multicore
processors using the inteltool utility.
The range is set using --cpu-range <start>[-<end>] command line option:
$ sudo ./inteltool -M --cpu-range 0-7
$ sudo ./inteltool -M --cpu-range 7-15
$ sudo ./inteltool -M --cpu-range 32
$ sudo ./inteltool -M will print a register dump for all cores, just
as before.
Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35919
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SPD support to lantis for MT53E512M32D1NP-046 WT:B
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage
Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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irq(ACPI_IRQ_LEVEL_LOW) -> ACPI_DESCRIPTOR_INTERRUPT -> IO-APIC,
will assert interrupt frequently;
irq_gpio(ACPI_GPIO_IRQ_EDGE_BOTH) -> ACPI_DESCRIPTOR_GPIO -> INT34C8;
will not assert interrupt frequently;
Because IRQ configuration can't be setted to both EDGE trigger.
BUG=b:195635555
BRANCH=dedede
TEST=Cirrus audio codec PLT pass
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I65bca519f75af84848284f039b6ad67cb1887823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56973
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"Latched" GPIOs like this one are a virtual representation of the
pending interrupt flag for the edge-triggered pin and not a direct
representation of line state, so they should always be marked
ACTIVE_HIGH or depthcharge will incorrectly negate them. This has always
been wrong and meant that depthcharge doesn't correctly wait for Cr50
flow control responses on these platforms. Thankfully it doesn't seem
like we've seen any practical issues from this, but it's still very
wrong.
BRANCH=trogdor
BUG=none
TEST=Booted CoachZ (no visible difference)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie1586b0e10b64df0712e28552411c4d540a7e457
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
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Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources.
In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device.
BUG=b:186384256
BRANCH=none
TEST=Verify the config setting can update to the GPPCLKCONTROL registers.
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56895
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Kconfig options and enable TPM device in devicetree
BUG=None
TEST=Booted the image and checked the successful TPM
communication in verstage,romstage & ramstage from
coreboot logs.
Signed-off-by: Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com>
Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Create the driblee variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:191732473
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_DRIBLEE
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the corori variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:194356176
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CORORI
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56796
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All Atlas devices have the touchscreen controller, so probing for its
presence is unnecessary. Removing the probe requirement allows the
touchscreen ACPI device in Linux to re-enumerate when rebinding its
I2C adapter device.
Without this change, after rebinding the touchscreen's I2C adapter
device using sysfs the touchscreen ACPI and HID devices are absent, and
the touchscreen is unresponsive.
With this change, the touchscreen ACPI and HID devices are re-created
after rebinding its I2C adapter device, and the touchscreen becomes
responsive again.
BUG=b:177350937
TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds
with Linux 4.4 and 5.4.
Built new AP FW from Atlas Chrome OS firmware branch with this change
applied. Tested shipping RO + new RW, and new RO + new RW.
Test sequence:
1) Boot DUT, verify basic touchscreen functionality.
2) $ cd /sys/bus/platform/drivers/i2c_designware
3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}}
lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6
drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00
drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002
drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw
drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1
4) $ echo i2c_designware.0 > unbind
5) Verify touchscreen is unresponsive (as expected after unbind).
6) $ ls -ld i2c_designware.0
ls: cannot access 'i2c_designware.0': No such file or directory
7) $ echo i2c_designware.0 > bind
*** Without this change: ***
8) Touchscreen remains unresponsive.
9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}}
ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory
lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6
*** With this change: ***
8) Touchscreen is functional again.
9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}}
lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6
drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00
drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003
drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw
drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1
Signed-off-by: Matthew Blecker <matthewb@chromium.org>
Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
MT53E512M32D1NP-046 WT:B
MT53E1G32D2NP-046 WT:B
BUG=b:192052098
TEST=FW_NAME=redrix emerge-brya coreboot
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Add I2C parameters to make sure each bus speed is around 390kHz.
BUG=b:188793264
TEST=Measure by scope.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Update initial gpio configuration for kano
BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Recent change "7a8c68a: mb/google/brya: Configure H21 as GPO and A17
as low" turned EN_FCAM_PWR low since EN_FCAM_PWR is turned ON and
OFF by IPU driver while MIPI UFC probing. However USB UFC also
requires 3.3V which is enabled by A17. This caused USB UFC
enumeration to fail
BUG=b:196014678
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56882
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The "silentoldconfig" target has been removed in Linux 5.13's kconfig
(CB:37152). As explained by Michal Marek at
https://lkml.org/lkml/2011/8/31/189, the "silentoldconfig" target has
become an internal interface and "oldconfig" is just as silent now.
Therefore, correct the target for syntax checking.
Change-Id: I8416bd4a96d15415f46c591ceb26ebb29aef1ab0
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
|
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modify reset_gpio as active low to meet touchscreen spec
BUG=b:195490284
BRANCH=none
TEST=build coreboot and touchscreen works
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Enable MKBP (Matrix Keyboard Protocol) interface for all Brya family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.
BUG=b:170966461
TEST=manual test on Brya P1: Volume Up/Down buttons
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add mainboard finalize and shutdown call to match zork.
Deassert EN_PWR_FP in bootblock, power up correctly in finalize.
| Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume |
|-----------|--------------|-----------|----------------------|
| Bootblock | **Low** | **Low** | Maintain High / High |
| Romstage | Low | Low | Maintain High / High |
| Ramstage | Low | **High** | Maintain High / High |
| Finalize | **High** | High | |
| Shutdown | **Low** | **Low** | |
BUG=b:191694480
TEST=Build, verify GPIO configuration.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Change-Id: I9f9aa5bf6ed4e1430e7067bfe5d3ce8e59e85812
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
