Age | Commit message (Collapse) | Author |
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from 2.1x to 1.1x or from 4x(SERIAL_CPU_INIT) to 1.1x
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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olpc and rumba can now boot linux out of flash. vsa was resized to 64K.
olpc and rumba now used compressed payload -- thanks stefan!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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goodrich pll code
disable havedmi
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YhLu's suggestions are all there..
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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We lost a few things, but this is still worth it.
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Default is 255.
This allows mainboard configs for working across various groups
of boards that differ a device that may not loaded.
If you search for a device that is not loaded and max buses is 255
then there can be up to a 8 second delay to search the entire PCI space.
Board configs that know thier max bus can limit this search space.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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You may specify '-d bus:dev.func' or '-d dev.func'. If you do '-d <value>'
then the behavior reverts back to the orginal where <value> is taken to be
the 16-bit packed notation of busdevfn.
It also add a sanity check to try and detect when people have not specified
the -d option and they should have, or when the -d bus:dev.fn evals to a packed
busdevfn of 0x0000.
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northbridge.c
builds fine on lippert
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Add cpureginit.c
added called to cpureginit to model_gx2_init.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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http://snapshots.linuxbios.org/stats/abuild-LinuxBIOSv2-2247.log
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the result should be ok though..
the purpose is dropping the old i82801er southbridge code
and using the ich5r code instead because its the same chip
but the code looks more solid and is used by many more systems.
Some of the old i82801er features have been ported (like hpet enable)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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again.
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try to fix 0x10000026
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on a SOM-DB2301 baseboard with a SOM-2354 cpu module.
- Also does a slight tweak to the ram test code to make it more
obvious when it fails.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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support for flashrom
* https://openbios.org/roundup/linuxbios/issue99 - add ICH4-M support to flashrom
both from scott.tsai <AT> arima.com.tw
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* Support for ATI SB400 (RS480 chipset)
* Support for Intel ICH7 (from Scott Tsai, scott.tsai <AT> arima.com.tw)
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adding vsm support now.
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msr set in northbridge that conflicted with the cpubug support.
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add ts5300 flag as comment in flashrom utility Makefile
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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cleaning
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- some ts5300 code. Let's push this upstream for now.
- fix a typo in device.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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another flash chip that doesn't clog the serial line
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