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2014-03-14cbfstool: add relocation parsing to ELF parserAaron Durbin
Optionally parse the relocation entries found within an ELF file. Change-Id: I343647f104901eb8a6a997ddf44aa5d36c31b44b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5374 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14cbfstool: introduce struct parsed_elf and parse_elf()Aaron Durbin
In order to make the ELF parsing more flexible introduce a parse_elf() function which takes a struct parsed_elf parameter. In addition take a flags parameter which instructs the ELF parser as to what data within the ELF file should be parsed. Change-Id: I3e30e84bf8043c3df96a6ab56cd077eef2632173 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5373 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: remove incorrect section size checkAaron Durbin
I was overzealous in checking the section size with respect to the file size. That check makes no sense as the section only deals with link sizes -- not on-disk sizes. Remove the check as it doesn't make any sense. Change-Id: I348e7847ae3a50badc22693439614f813462445a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5384 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13mainboard/jetway/nf81-t56n-lf: Fix HWM base addr.Edward O'Callaghan
The target board has a different base addr. for its hardware monitor (fans, temp, etc) from the Fintek Super I/O datasheet. Change-Id: Ifc025cb92d0fc4e8f813091d00a6c87deae05863 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5383 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13mainboard/jetway/nf81-t56n-lf: Remove hard-coded IMC fan craft.Edward O'Callaghan
Fan controls in 0x400-0x4ff are not programmed here. Thus fan control from amd/persimmon in the devicetree.cb does not apply to this board. Change-Id: I9156143476df0a7b44c7af90fa2107e8a8ba851e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5381 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13cbfstool: elfparsing: check segment and section regionsAaron Durbin
While parsing the section and program headers ensure the locations of their contents are within the elf file proper. Change-Id: I856f7de45f82ac15977abc06e51bedb51c58dde1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5372 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: elfheaders: use proper parameters to calloc()Aaron Durbin
Though the result doesn't matter much, the callers of calloc() should order the parameters correctly. i.e. the first paramter is the number of elements in an array and the second is the size of each element. Change-Id: Ic7c2910d623d96f380feb4e5f6fa432376f49e9b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5371 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: add eflparsing.hAaron Durbin
elfparsing.h serves as the header to working with the elf parser. Additionally, only include what is needed by the other files. Many had no reason to be including elf.h aside from fixing compilation problems when including cbfs.h. Change-Id: I9eb5f09f3122aa18beeca52d2e4dc2102d70fb9d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5370 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: move iself() to eflheaders.cAaron Durbin
The only user of iself() was in elfheaders.c. Move it there, and make it local to the compilation unit. Change-Id: I0d919ce372f6e2fce75885fb4fcba20d985979b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5369 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: elfheaders: use common checks and buffer helpersAaron Durbin
The elfheaders code was manipulating struct buffers. Use the introduced buffer helper functions. Additionally fix up offset and size checks for the program headers and section headers by using common code paths. Change-Id: I279c77f77aaa1860a0be43fb111df890dd1d84d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5368 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-12Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"Alexandru Gagniuc
This reverts commit b845636ce67f6e7c96bf3fb3008738f596a5d5ce. This commit changed the board status script to describe all boards in terms of x86 terminology, such as CPU->southbridge->northbridge. This terminology does not apply to a number of SoCs, in which the buses are not connected via successive bridges, and as such it is misleading and misguided to describe ideas of southbridge and northbridge for these devices. Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5177 Tested-by: build bot (Jenkins)
2014-03-12drivers/spi: Add support for adesto SPI flash partsChris Douglass
Adds support for the following Adesto Technologies SPI Flash parts. AT25DF081 AT25DF321 AT25DF641 It has been tested on an Orion VPX7654 board populated with an AT25DF321A part. The "08" and "64" densities have not been tested. These parts are the successors of the Atmel AT26DF line that was spun out or purchased by Adesto. In this patch, adesto.c is identical to winbond.c with part entries for the Adesto parts. The datasheet for the AT25DF parts includes a "100MHz" programming command in addition to the "85MHz" command that is currently used but this patch does not add support for that enhanced programming mode. Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5225 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11chromeos: provide option to dynamically allocate ram oops bufferAaron Durbin
Fixing the location of the ram oops buffer can lead to certain kernel and boot loaders being confused when there is a ram reservation low in the address space. Alternatively provide a mechanism to allocate the ram oops buffer in cbmem. As cbmem is usually high in the address space it avoids low reservation confusion. The patch uncondtionally provides a GOOG9999 ACPI device with a single memory resource describing the memory region used for the ramoops region. BUG=None BRANCH=baytrail,haswell TEST=Built and booted with and w/o dynamic ram oops. With the corresponding kernel change things behave correctly. Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11baytrail: Reserve memory between ASEG and 1MB and for ramoopsDuncan Laurie
Low system tables are in this region, and it is probably safer to keep ASEG reserved. Also keep the region used by ramoops from being used by the OS and from being cleared by developer mode boots. Lots more work needed to make the ACPI tables fully functional. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4932 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-11rambi: Enable USB boot with EHCI controllerDuncan Laurie
This adds the EHCI driver back to libpayload and configures the devicetree to route ports to EHCI. This is hopefully just temporary until the issues with XHCI can be worked out. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot from USB on rambi Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175513 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4931 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: Add EHCI initializationDuncan Laurie
This adds required steps to initialize the EHCI controller on the baytrail platform. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot from USB on rambi Change-Id: I3a5487791e2305616036d4550e260a178c0e1c4d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175512 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4930 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: Add XHCI initializationDuncan Laurie
This adds required steps to initialize the XHCI controller on the baytrail platform. Actually using XHCI is causing lots of bad behavior including apparent memory corruption. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot on rambi Change-Id: Ic43e04f4b47e107ec3bb0c387a9fc72c3cae0271 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175511 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4929 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: add audio clock workaround for LPEAaron Durbin
Apparently the LPE device needs a 25MHz clock. Provide the work around to enable this clock. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Confirmed setting being applied. Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175493 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4928 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: add ccu iosf access functionsAaron Durbin
The clock control unit needs to be accessed to configure some of the devices properly. Therefore. provide a way to access the CCU. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built. Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175492 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4927 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: HDA function disable workaroundAaron Durbin
Parts of the audio path are common between the HDA and LPE. However, those parts are power-controlled by the D-state of the HDA device. Therefore, one cannot put the HDA into D3Hot because those audio paths will be shutdown. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Disabling HDA still causes a shutdown when performing warm reset, however I was able to verify the magic sequence was being performed. Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175491 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4926 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: allow function disable on TXEAaron Durbin
Previously it was not known how to put the TXE pci device into D3Hot. It's been disseminated that this is not a requirement for disabling the TXE pci device in the function disable register. Therefore, allow this by returning 0 from place_device_in_d3hot(). BUG=chrome-os-partner:22871 BRANCH=None TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being set accordingly. Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175490 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4925 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: Switch graphics init to use reg_scriptDuncan Laurie
This is an example consumer of the register script handler. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi and see recovery screen Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175214 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4924 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11cbfstool: add struct buffer helper routinesAaron Durbin
There are some open-coded manipulation of the struct buffer innards in the elf parsing code. Add helper functions to avoid reaching into the struct itself. Change-Id: I0d5300afa1a3549f87f588f976184e880d071682 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5367 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11cbfstool: add bputs() to store a byte stream to a bufferAaron Durbin
There was already a bgets() function which operates on a buffer to copy a byte stream. Provide bputs() to store a byte stream to a buffer, thus making the API symmetrical. Change-Id: I6166f6b68eacb822da38c9da61a3e44f4c67136d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5366 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11cbfstool: add get8/put8 variants to xdr structuresAaron Durbin
In order to provide consistent usage provide the get8() and put8() callbacks to xdr operations. That way no futzing needs to be done to handle 8-bit reads and writes. Change-Id: I1233d25df67134dc5c3bbd1a84206be77f0da417 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5365 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11cbfstool: move verbose to common.cAaron Durbin
In order for multiple tools to use the common code found in common.c place the verbose variable within common.c's compilation unit. Change-Id: I71660a5fd4d186ddee81b0da8b57ce2abddf178a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5364 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11rmodule: allow rmodule header structure to be used by userlandAaron Durbin
In order for userland to create rmodules the common code should be shareable. Therefore, convert the short u<width> name types to the posix uint<width>_t types. Additionally, move the definition of the header structure to a new rmodule-defs.h header file so that userland can include that without pulling in the coreboot state. Change-Id: I54acd3bfd8c207b9efd50a3b6d89efd5fcbfc1d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5363 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-10AMD Olive Hill: add IMC fan controlWANG Siyuan
There are 3 steps to enable the IMC fan control: 1. Enable fan control related registers on Hudson using oem_fan_control(). 2. Set EcStruct. 3. Enable thermal zone using enable_imc_thermal_zone(). I have tested on Olive Hill. Change-Id: I1748e8c92fb72a82bac0506ecdf98304a5bd8239 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4301 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10AMD Parmer: add IMC fan controlWANG Siyuan
There are 3 steps to enable the IMC fan control: 1. Enable fan control related registers on Hudson using oem_fan_control(). 2. Set EcStruct. 3. Enable thermal zone using enable_imc_thermal_zone(). I have tested on Parmer. Change-Id: Id11d5c5da30346c034d155a73749e7f4c9c980eb Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4302 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10CBMEM console: Fix build for ARMKyösti Mälkki
This preprocessor guard was used to disable CBMEM console from romstage of ROMCC boards. It unintentionally disabled it for ARM too as they do not have CACHE_AS_RAM selected. Option EARLY_CBMEM_INIT implies CAR migration which is required to have CBMEM console in romstage. This change should have been done in commit f8bf5a10 already, but we missed it. Change-Id: I03e95183be0e78bc7dd439d5fef5b10e54966dc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5356 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-09intel/gma: Remove MCH register declarations.Vladimir Serbinenko
i915_reg.h re-declares some of MCH registers as seen through MCHBAR mirror. It's not currently used and we don't want any MCH registers in GFX. Change-Id: I5fa4711fee60d64316696b7ed713013de8759b54 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5318 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09smbios: Supply tag type 2 (base board information)Vladimir Serbinenko
Information really contained in it is mostly the same as in type 1 tag. However Linux uses type 2 to match hardware. Duplicate the info. Change-Id: I75e13d764464053ecab4a833fbb83836cedf26e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5322 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09lbtdump: Dump forwarded tables.Vladimir Serbinenko
Recent coreboot puts real tables in high memory and only pointer is remaining at traditional location. This patch makes lbtdump work with recent coreboot. Change-Id: I1c4945909da16c0ec81e59c2d94d9a7d27e2aba5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4830 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09mainboard/jetway/nf81-t56n-lf: Turn PS/2 driver on by default.Edward O'Callaghan
This board has a working PS/2 port for a keyboard. Thus, it makes for a good option to have on by default. Change-Id: Ifcde0474d7be26152f1b5e19fe4906e87732b9a4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5357 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.Edward O'Callaghan
The platform dependent mainboard.c was incorrectly disabling the second clock signal feeding the GPP ports. This results in spurious hangs by calling the set_pcie_dereset() SB CIMx callback many times. This also stops coreboot from finding the second NIC behind the pci 15.0 bridge. Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5355 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-03-09intel/jarrell: Apply ROMCC workaroundKyösti Mälkki
Taken from intel/xe7501devkit, maybe it had same symptoms once. The call to ich5_watchdog_on() has side-effect of exploding the requirements for ROMCC internal arrays at compile-time. The hard-coded limit in question is MAX_RHS in util/romcc.c, the default of 127 comes from the rhs field defined with 7 bits. Before this patch intel/jarrell builds were using upto MAX_RHS=102, while other ROMCC boards built even with MAX_RHS=10. This workaround brings intel/jarrell to the same level. Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5348 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-08ROMCC: Trigger internal compiler failure and apply the workaroundKyösti Mälkki
These boards first failed when attempting to change print_err() from direct function call to console_tx_XX() to a code block in the form of do { if (y) console_tx_XX(x); } while(0) Removing the label dummy_romcc_workaround_label added here will trigger the following compiler error for the two boards: Internal compiler error: no edge to block->last->next Change-Id: I997adfaf586d7fa2096401dd574b07ce676d0ac6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5349 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-08utils/romcc.c: Fix spurious unsigned integer comparisons.Edward O'Callaghan
Clang warns about comparisons of unsigned integers with being below zero. Remove spurious logic checks that are always false. Change-Id: I70c4d5331df81e48bf7ef27ff98400c4218f7edc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5275 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-08qemu-i440fx: add a prototype for main()Patrick Georgi
This probably belongs elsewhere, but I haven't found a nice place yet. Change-Id: I9ca52db33905cf4ee229d7ff44012105915271a8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4720 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-08lib/dynamic_cbmem.c: Include `cbmem_console.h`Paul Menzel
Broken with commit 1d7541fe (console: Fix includes). Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5351 Tested-by: build bot (Jenkins)
2014-03-07x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING optionAaron Durbin
Boot speeds can be sped up by mirroring the payload into main memory before doing the actual loading. Systems that would benefit from this are typically Intel ones whose SPI are memory mapped. Without the SPI being cached all accesses to the payload in SPI while being loaded result in uncacheable accesses. Instead take advantage of the on-board SPI controller which has an internal cache and prefetcher by copying 64-byte cachelines using 32-bit word copies. Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04Add a generic register script handlerDuncan Laurie
This is based on the RCBA configuration setup from haswell. It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF. I did not extend it to handle MSR yet but that would be another potential register type. There are a number of approaches to this kind of thing, but in the end they have a lot of switch statements and a mass of #defines. I'm not particularly set on any of the details so comments welcome. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175206 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4923 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04console: Use single driver entry for UARTsKyösti Mälkki
UARTs now have unified prototypes and can use a single entry in the list of drivers for ramstage. Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5308 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04usbdebug: Move Kconfig under drivers/usbKyösti Mälkki
This menu may become a bit more complicated with addition of new USB hardware so move it out of console/. Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5307 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04SMM: Only have console with DEBUG_SMIKyösti Mälkki
Existing code compiled serial communication and printk() for SMM even when DEBUG_SMI was not selected. Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5142 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-03-04uart8250: Move under drivers/uartKyösti Mälkki
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5236 Tested-by: build bot (Jenkins)
2014-03-04uart8250mem: Unify calls with generic UARTKyösti Mälkki
NOTE: UART base for SMM continues to be broken, as it does not use the address resource allocator has assigned. Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart8250io: Unify calls with generic UARTKyösti Mälkki
Change-Id: I6d56648e56f2177e1d5332497321e718df18300c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04console: Fix includesKyösti Mälkki
Do not pull in console hw-specific prototypes everywhere with console.h as those are not needed for higher levels. Move prototypes for UARTs next to other consoles. Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5232 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04pl011 UART: Move under drivers/uartKyösti Mälkki
Currently this is only a minimal stub to get console on qemu-armv7. Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5162 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04ti/am335x: Fix baudrate calculationKyösti Mälkki
UART input clock is platform dependent. Also account for possible use of get_option() where baudrate is not compile-time constant. The hardware reference on BeagleBone is from a 48 MHz oscillator input. With pre-divisor of 16 we get same register values as in table 19-25. Change-Id: I89aee27c958f8618ce79a968ae7520a867e7e8a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5290 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04allwinner/a10: Fix baudrate calculationKyösti Mälkki
UART input clock is platform dependent. Also account for possible use of get_option() where baudrate is not compile-time constant. Change-Id: Ie1c8789ef72430e43fc33bfa9ffb9f5346762439 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5289 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04samsung/exynos5: Fix baudrate calculationKyösti Mälkki
Account for possible use of get_option() when baudrate is no longer compile-time constant. Change-Id: Ib45acd98e55c5892dbce9903830665aefeda5be0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5288 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04option: Add arch-agnostic get_option()Kyösti Mälkki
We should not have pc80/ includes in console/. Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5157 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart8250: Fix and unify baudrate divisor calculationKyösti Mälkki
Divisor is a function of requested baudrate, platform-specific reference clock and amount of oversampling done on the UART reference. Calculate this parameter with divisor rounded to nearest integer. When building without option_table or when there is no entry for baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate. For OxPCIe use of 4 MHz for reference was arbitrary giving correct divisor for 115200 but somewhat inaccurate for lower baudrates. Actual hardware is 62500000 with 16 times oversampling. FIXME: Field for baudrate in lb_tables is still incorrect. Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5229 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart: Drop HAVE_UART_MEMORY_MAPPEDKyösti Mälkki
This option is used to make uart8250mem option visible in menuconfig. Showing it for these ARMs is incorrect. Change-Id: I2c28e1c3781df41c09c365355a5105c9fe4945ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart: Do not guard entire include file by config optionsKyösti Mälkki
Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or CONFIG_CONSOLE_SERIAL8250MEM or CONFIG_CONSOLE_SERIAL. Don't do indirect includes for <uart8250.h>. The config-specific options are already properly guarded, and there is no need to guard the register and bit definitions. Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4585 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04jetway/nf81-t56n-lf: Minor corrections to devicetree.cbEdward O'Callaghan
The miniPCIe ports hanging off 15.0 are infact x1, as are the two onboard NIC's on 6.0 and 15.0. Change-Id: I6247838f6b5823369543e338975a4c5c6fd00d7c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5328 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04jetway/nf81-t56n-lf: Fix PS/2 ACPI for KBC & Mouse.Edward O'Callaghan
Provide ACPI table node so that the PS/2 keyboard/mouse port works in GNU/Linux. Change-Id: If73b8d37a81bb9066cbcc650b518d25e243b84e7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5327 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04.gitignore: Don't track .ccwrap from scan-build.Edward O'Callaghan
Change-Id: I5757023b844e965d797e6b1a7e6955940f6d3363 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5317 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04nehalem: Replace video init.Vladimir Serbinenko
Old video init just replayed the sequence. This one actually computes the values. Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5270 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04drivers/intel/gma: Add EDID retrieving functions.Vladimir Serbinenko
Change-Id: I64f2fcc5ad52d6a0188d02b28769001ada718c4f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5278 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-04bd82x6x, ibexpeak, lynxpoint: Unify SPI.Vladimir Serbinenko
SPI registers didnt change since ICH8. No need to have separate files for them. Unify. Change-Id: I4e2ac3221b419c007e135c9ee615fc3b84424cbc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5254 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04ibexpeak/ehci: Set .enable_resources properly.Vladimir Serbinenko
Without this memory decoding isn't activated which, in turn, makes SeaBIOS crash. Change-Id: I3dcc721b500ab7468e1082157eeeed38044462d0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5326 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-03coreboot: don't return struct lb_memory * from write_tables()Aaron Durbin
No one is interrogating the write_tables() return value. Therefore, drop it. Change-Id: I97e707f071942239c9a0fa0914af3679ee7a9c3c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5301 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-03-03nehalem: Remove SSKPD.Vladimir Serbinenko
Not really used and conflicts with SSKPD from i915_regs.h Change-Id: I1462457f656310df99e78aee8cbfe0206f6e2a1e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5268 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-03qemu: Support textmode gfx init.Vladimir Serbinenko
Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5283 Tested-by: build bot (Jenkins) Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03devices: Allow to configure textmode in native gfx init.Vladimir Serbinenko
Usefull to select between text mode which offers best compatibility with payloads and gfx mode which makes the best-looking screen. Also right now we have an unfortunate situation when qemu is in gfx mode while most real systems use text mode. Change-Id: Ifad7ba197875edfdd06eb932afeb5800229ef055 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5282 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-03lib/selfboot: s_srcaddr is uninitialized.Edward O'Callaghan
s_srcaddr is uninitialized in the BSS section, leading to a garbage valued operand on the LHS of a '<' on line 383. Change-Id: Ie4fec91b09c70fb1d91ad3918ac3f60653fa1d83 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5314 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-03coreboot: remove unused get_lb_mem() functionAaron Durbin
The get_lb_mem() is no longer used. Therefore, remove it. Change-Id: I2d8427c460cfbb2b7a9870dfd54f4a75738cfb88 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5304 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03selfboot: use bootmem infrastructureAaron Durbin
Instead of packing and unpacking entries in lb_mem use the bootmem infrastructure for performing sanity checks during payload loading. Change-Id: Ica2bee7ebb0f6bf9ded31deac8cb700aa387bc7a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5303 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03coreboot: introduce notion of bootmem for memory map at bootAaron Durbin
The write_coreboot_table() in coreboot_table.c was already using struct memrange for managing and building up the entries that eventually go into the lb_memory table. Abstract that concept out to a bootmem memory map. The bootmem concept can then be used as a basis for loading payloads, for example. Change-Id: I7edbbca6bbd0568f658fde39ca93b126cab88367 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5302 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03intel/nehalem: Fix soft reset detection.Vladimir Serbinenko
Change-Id: I4575cddc35dc8309372beafec441d194bc145242 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5267 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-03intel/nehalem: Use non-powercycle reset.Vladimir Serbinenko
Change-Id: Ibc2421a50e272a580461e4eacec6cfcd38654fe8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5266 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-03nehalem/raminit: Don't touch clock generator in raminit.Vladimir Serbinenko
Clock generator is mobo-specific. Don't touch it in raminit. Change-Id: Ie114696b7fb13b8daee8dd1393d43bc609e149b3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5265 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-03coreboot: introduce arch_payload_run()Aaron Durbin
The selfboot() function relied on global variables within the selfboot.c compilation unit. Now that the bounce buffer is a part of struct payload use a new architecture-specific arch_payload_run() function for jumping to the payload. selfboot() can then be removed. Change-Id: Icec74942e94599542148561b3311ce5096ac5ea5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5300 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03selfboot: store bounce buffer in struct payloadAaron Durbin
In order to break the dependency on selfboot for jumping to payload the bounce buffer location needs to be communicated. Therefore, add the bounce buffer to struct payload. Change-Id: I9d9396e5c5bfba7a63940227ee0bdce6cba39578 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5299 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03coreboot: use struct payload for selfload()Aaron Durbin
In order to encapsulate more data for self loading use struct payload as the type. That way modifications to what is needed for payload loading does not introduce more global variables. Change-Id: I5b8facd7881e397ca7de1c04cec747fc1dce2d5f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5298 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03coreboot: move common code to payload_run() from selfboot()Aaron Durbin
The selfboot() routine was perfoming most of the common teardown and stack checking infrastructure. Move that code into payload_run() to prepare removal of the selfboot() function. Change-Id: I29f2a5cfcc692f7a0fe2656cb1cda18158c49c6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5297 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03coreboot: unify infrastructure for loading payloadsAaron Durbin
A payload can be loaded either from a vboot region or from cbfs. Provide a common place for choosing where the payload is loaded from. Additionally, place the logic in the 'loaders' directory similarly to the ramstage loader infrastructure. Change-Id: I6b0034ea5ebd04a3d058151819ac77a126a6bfe2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5296 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-02vendorcode/amd/agesa/f*: Improve gcccar.inc assembler compatibility.Edward O'Callaghan
A comparison with a two's complement in gcccar.inc has dubious GAS/AT&T notation. Clang miss-parses 0x-1 as an invalid hexadecimal number. Change-Id: I88baa5c2513f062ff309df05916a3832b9bd9bb1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5277 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-03-02cbfstool/lzma: Remove dead code under #ifdefsAlexandru Gagniuc
Remove a bunch of dead code which depends either on commented out #defines, or compiler definitions. Use this opportunity to remove the need for "-D_7ZIP_ST" in the compiler flags. Change-Id: Ib6629002be7bf4cee6d95d7baa724893b5e8ba32 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5083 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-01lenovo/x60: Unify volume button handling with common code.Vladimir Serbinenko
Change-Id: I45fe44a91f9f83a510b204e01dbaff9e8a9696ca Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5099 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-03-01intel/sandybridge: add PCI IDs for 6-Series PCHChris Douglass
The PCI ids are taken from: Intel® 6 Series Chipset and Intel® C200 Series Chipset Specification Update – NDA October 2013 CDI / IBP#: 440377 Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5226 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-01lenovo/x201: Move mainboard init to mainboard_init.Vladimir Serbinenko
Rather than having it inside mainboard_enable. Change-Id: Ie8bd25eb49b919b4e25c4628e3557fc66b2ba4d9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4840 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-28drivers/spi: Sort SPI flash filesChris Douglass
Change-Id: Id7e65065556ca7225969ca0afdb21eda24aeb967 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28util/ifdtool: cleanup some magic numbersChris Douglass
There are five firmware regions that are (currently) defined. This was assumed throughout the ifdtool code with many literal 4s and 5s. This patch changes them to refer to a new #define NUM_REGIONS. Change-Id: I523d3763942f875025ebc4b9ba8b2ccf1db5b2f5 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5313 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28util/ifdtool: add option to change flash layoutChris Douglass
The new option "--newlayout <file>" will read <file> in flashrom's layout format and copy flash regions from the current flash image file to a new flash image file. If a region grows, the padding is added at the beginning of the target region in the new file so that the data is "right-aligned" to the end of the region. If a region shrinks, a warning is given and the tail end of existing data is copied to the target region in the new file. Regions of zero or negative size are ignored. (In the example below 00fff000:00000fff regions are an artifact of the address encoding in the register fields.) Example Usage: Given a flash image for a board with a Sandy Bridge processor and Intel 6-Series chipset in the file vpx7654.bin ifdtool --layout layout.txt vpx7564.bin will yield the file layout.txt: 00000000:00000fff fd 00180000:003fffff bios 00001000:0017ffff me 00fff000:00000fff gbe 00fff000:00000fff pd Notice that the "bios" portion extends to the end of the 4MB flash. It may be edited to extend the bios portion to consume to the extent of an 8MB flash. like layout2.txt: 00000000:00000fff fd 00180000:007fffff bios 00001000:0017ffff me 00fff000:00000fff gbe 00fff000:00000fff pd ifdtool --newlayout layout.txt vpx7654.bin will create a file vpx7654.bin.new that is 8MB. Change-Id: I0e0925a725c40fa44d8c4b6e86552028779d0523 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5312 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28util/ifdtool: add option to dump flashrom layoutChris Douglass
Dump the Intel Flash Descriptor map in the format expected by flashrom's "layout" option. Example usage: Given a 4MB flash image vpx7654.bin that was generated by Intel's FITC tool for a 6-Series chipset... ./ifdtool --layout l.txt vpx7654.bin cat l.txt 00000000:00000fff fd 00180000:003fffff bios 00001000:0017ffff me 00fff000:00000fff gbe 00fff000:00000fff pd Change-Id: Ib740178ed6935b5f6e1dba1be674303f9f980429 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5306 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28boardstatus/towiki: Skip OVERRIDE_FANCTLVladimir Serbinenko
Change-Id: I4c5f69db198c8aa4757c82856fb04aa5ee16879f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5123 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-28boardstatus/towiki: Skip comments after options.Vladimir Serbinenko
Change-Id: Id1213f4a44cd3a7a698b761d4942707d7dc1dee6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5122 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-28boardstatus/to-wiki.sh: Accept Kconfig with non-tab separators.Vladimir Serbinenko
Change-Id: I3812c6bd6fb11d9e98ef60afb205782f2b1f0e44 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5069 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27baytrail: use common code for iosf accessorsAaron Durbin
The same sequence is used regardless of the port being read or written. Therefore, use the same implementation for reading or writing to a port. BUG=None BRANCH=None TEST=Built and booted through depthcharge. Dev and recovery screens still work. Nothing bizarre in console output. Change-Id: I1a64b54b50472fa7d601e199653eb4a76accf910 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175441 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4922 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-27baytrail: add lpss iosf functions and regsAaron Durbin
The low power subsystem devices have a lot of their configuration done in the IOSF sideband message space. Add support for these access methods. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted through depthcharge. Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636 Signed-off-by: Aaron Durbin <adurbin@chromum.org> Reviewed-on: https://chromium-review.googlesource.com/175440 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4921 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-27baytrail: Fix EHCI function number and XHCI typoDuncan Laurie
BUG=chrome-os-partner:23635 BRANCH=rambi TEST=successfully disable EHCI controller in devicetree.cb Change-Id: I8a22e25a9f7c263d2a6debf0cd1606cb0f6f7645 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175403 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4920 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-27baytrail: increment boot count for elogAaron Durbin
The elog boot counter in cmos was not being initialized nor incremented. Start doing that in romstage. Since S3 resume is not detected yet the increment is unconditional. BUG=None BRANCH=None TEST=Built and booted through depthcharge multiple times. Noted output such as 'Boot Count incremented to 4'. Change-Id: Ic585d4ad4b3af086e0067e28fe0f35c02979bbd2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174717 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4919 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-27baytrail: add GNVS to cbmem and set acpi_slp_typeAaron Durbin
The ACPI code was previously complaining about not being able to find the GNVS area: 'ACPI: Could not find CBMEM GNVS'. Fix this by adding GNVS area early in start up. This is also the appropriate place to set the acpi_slp_type variable to indicate an S3 resume or not. BUG=chrome-os-partner:22867 BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted through depthcharge. Noted cbmem has 'ACPI GNVS' entry. Change-Id: Ifbca3dd390ebe573730ee204ca4c2f19626dd6b1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174647 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4918 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-27baytrail: fix uninitialized acpi structuresAaron Durbin
The callers of the following functions assume the storage area provided by the pointers is initialized. That's not the case as these were just place holders. - void acpi_create_intel_hpet(acpi_hpet_t * hpet); - void acpi_create_serialio_ssdt(acpi_header_t *ssdt); To fix this properly initialize the hpet entry, and just remove the serialio_ssdt function entirely. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted through depthcharge on rambi. Noted no more ACPI errors relating to invalid length. Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174716 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4917 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27baytrail: Add IOSF functions for USBPHY and USHPHYDuncan Laurie
These are needed for USB2 and USB3 PHY init sequences. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Id284d882034e15eceeaa910b8b73bc0d8d895199 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4916 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27rambi: Enable internal keyboardDuncan Laurie
The EC LPC init function needs to run to enable the internal keyboard. I needed this to confirm that it is just USB keyboards that are causing all sorts of issues. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=boot to recovery screen and hit tab Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175207 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4915 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 07:26:06 +0000