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Change-Id: I94dd6b1bb81bbc38ac5f89469b3ed7c83ca2a498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I22d7e724e69b41c9fabdef785276dc428be2b400
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Commit d9ef02ce (soc/intel/apollolake: Lock down Global SMI) breaks
SMM/SMI on Apollolake (but not Geminilake), so guard it accordingly.
TEST=build/boot google/reef, verify SMM/SMI/SMMSTORE functional.
Change-Id: I00cbe046b61e6c342f7961670478d0ca8d365c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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If the coreboot code is not in a git repository, the linters switch
from using `git ls-files` to find. This requires some changes to
prevent the linters from looking at the wrong files which are
automatically excluded by git.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I81d138760c29a7c476280bb9d963f6be99c75d6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Tested on unsupported mainboard (945g-m4).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1935308cc50abd651b52d6290d66180905c6a521
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Create the gladios variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:239513596
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_gladios
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I3dc99d97d8e30d9641f56616222dd68e3a0d548d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update the SMI definitions for morgana per PPR #57396, rev 1.52
Remove references to dropped SMITYPE_XHC2_PME in xhci.c to fix compile
errors.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6a9f05bcc6a6e4c94114ccbd07628629bdfabcba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The coreboot 4.18 release has been tagged, so the release notes can
now be finalized.
Updated with known issues.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I77676ddc42488e9635f1e6f995386490dca441c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68467
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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i945.h file is not used to generate asl files.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To allow testing of code that uses CPUID calls, separate the actual
calls into a separate header file, This allows the tests to emulate
the cpuid access without replacing the rest of the cpu.h definitions.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic5ee29f1fbb6304738f2eb7999cbcfdf8f7d4932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This allows us to see which of the common code blocks have been verified
and which have not.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Icb9eba5838013de75c408c28a4a7d3afacdf0674
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I055847c9b08795683fe2e1dfd7fcde49901fc973
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Boards which use an I2C TPM and do not use vboot will not have the
I2C bus initialized/ready at the start of the device init phase.
If TPM init is called before the bus, init will fail with I2C
transfer timeouts and a significantly lengthened boot time.
Resolves: https://ticket.coreboot.org/issues/429
TEST=build/boot google/reef w/o vboot, verify successful TPM init.
Change-Id: Ic47e465db1c06d8b79a1f0a06906843149b6dacd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68550
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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We use the name of the APCB file repeatedly, so put it into a variable
so that it's easier to update.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I8684db2f7b2d68f0354e37bd8cdfc4f9cab44b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40 ms.
Boot time data
Before:
* 955:returning from FspSiliconInit 1,656,985 (274,416)
After:
* 955:returning from FspSiliconInit 1,593,036 (233,286)
BUG=b:252410202
TEST=Verified that boot time is reduced by ~40 msec.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I0d4f66940529b8d38d9658c769feba8b5c9b715e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68418
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch adds the support to enable/disable skipping MBP HOB
from the devicetree based on mainboard requirement.
Porting the feature from commit 2bc54e7c001c
("soc/intel/alderlake: Add support to skip the MBP HOB")
TEST=Build and boot to verify that the right value has been passed to
the FSP.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I360d33617b9d2626fce5600e861214b0747f57b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Now that the SoC-specific UART controller data and the common code part
are cleanly separated, move the code to the common AMD UART support
block folder. The code is identical to the UART code in Cezanne,
Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts
related to the MMIO device driver.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97860292fd3cd0330fec40edb31089cd6608906b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3deae150cd1e20fff6507a0f0ba6a375fca430e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I813483bc0421043dc67c523f0ea2016a16a29f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I80278f1a098b389d78f8e9a9fb875c4e466dc5db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cfea274f4c9e908c11429199479aec037a00097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab1aec44c55570aa8085aeaf68ec69fe6de0f2ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I474e47059eaebcf0b9b77f66ee993f1963ebee77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Initialize the two GPIOs of the SoC UART if it's used for serial console
to be sure that the I/O mux is configured correctly without having to
rely on the bootblock_mainboard_early_init call to do this. This brings
Stoneyridge more in line with the other AMD SoCs. Since this code will
be factored out to the common AMD SoC code in a follow-up patch, the
function prototype is added to southbridge.h instead of creating a new
uart.h header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4aa6734e63dad204d22ce962b983cde6e3abd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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soc/iomap.h provides the UART base address information used in the
uart_info struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7defd135dc888cfc7d6e1c106d72116425560576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Introduce and use an array of soc_uart_ctrlr_info to align Stoneyridge
with the other AMD SoCs in order to allow commonization of the AMD SoC
UART code. Since the current Stoneyridge code doesn't provide or use
UART MMIO device operations, only the base addresses of the UART
controllers from this array are used for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie868cd3e2f77b0f7253c9f6d91dd3bbc3e4b6b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The SoC's uart_info structs all use the same anonymous uart_info struct
definition, so create a named struct for this in the common AMD SoC UART
header and use it in the SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The goal of this is to be able to move most of the code over to the
common AMD blocks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib893720911114d61ee6b3fbbf1a2a3594500bcfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The goal of this is to be able to move most of the code over to the
common AMD blocks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5077681b64dd68351340bd179838a174d8df1701
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The goal of this is to be able to move most of the code over to the
common AMD blocks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e585370a0de56787340788acfecc7931820566d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The goal of this is to be able to move most of the code over to the
common AMD blocks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia496a4b29b25d4438ed8fc09bfe6f83e3fb768d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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We are required to boot with eMMC enabled in the BIOS to store modem
calibration data. Thus, it doesn't make sense to enable NVMe at boot
time since we will never boot from NVMe w/o eMMC. We may as well take
the boot time reduction (~100ms) by eliminating NVMe initialization.
BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after disabling NVMe and make sure that it still boots
Note that we are able to see a little over 100ms in boot time
savings with this change.
Before: 40:device configuration 824,021 (102,701)
After: 40:device configuration 717,402 (44)
Cq-Depend: chromium:3964185
Change-Id: I94f614ba0369c073617949285c0781aef5c6263f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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We need to boot eMMC for modem calibration, there is not need for BIOS
to initialize NVMe anymore as the kernel will do so. Removing the pci
device from the device tree as a first step.
BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after removing from the herobrine device tree.
Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Configure GPIOs based on GPIO_20221014.xlsx of frostflow.
BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I02272801c85a7c30d24c834a840e026225956fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNCP3MLYR-N6E 1 (0001)
MT62F2G32D8DR-031 WT:B 2 (0010)
H9JCNNNFA5MLYR-N6E 3 (0011)
BUG=b:250470704, b:247683159
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I34584092c938539c91d65501ebe34b00212b34d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add Hynix H9JCNNNFA5MLYR-N6E in the memory_parts.json and re-generate
the SPD.
BUG=b:250470704
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I9926a5859cf060e0bfa903f47d8a98c8d6115579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
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This reverts commit 672bd9bee5c0045694ef20fe3e2f7a003bef0edd.
Reason for revert: Gmeet resolution dropped. When system starts
Gmeet video call, it uses the hardware accelerated encoder as per
the expectation. But, as soon as another system connects to the call,
the immediate fallback observed from hardware to software encoder.
Due to this, Gmeet resolution dropped from 720p to 180p.
Currently, this issue observed on AlderLake-N SoC based fanless
platforms. This issue is not seen on fan based systems.
BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alderlake-N systems. With this revert
Gmeet resolution drop not observed.
Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Remove redundant touchscreen "ELAN6915".
BUG=b:254328657
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I8f90b071b053858cf720de5ac2a71031fe623d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Craask does not have a SAR proximity sensor.
BUG=b:253387689
TEST=Dump ACPI SSDT and verify SX9324 related entries are not present.
Change-Id: Ia0e3eb6dba82594ca27040d6ab0197da6095f510
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68564
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This README.md file specifies the expectations and agreements implied by
contributing code to the coreboot src/vendorcode directory.
Licenses, structure, formatting and the like are all the responsibility
of the contributors, however as the code is a part of the coreboot
codebase, members of the coreboot community are allowed to modify the
code to the extent deemed necessary.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7e2aedce9383158d03be342cb10ae18d85146ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Test: cbmem reports verb table loaded for codec #2
Change-Id: I4db044535c95ccd3e81a67bb5e58e6f04ee8d12f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Test: build/boot google/drallion with non-ChromeOS build, Tianocore
payload. Windows 10, Linux 5.10.x booted successfully
Change-Id: I6358b1d5c71eee065fed96b7bca31e37f30d3a8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Librem Mini has a UART (accessible with soldering), which is very
useful for work on coreboot. It can be used for coreboot/SeaBIOS/Linux
boot logs, or as a general purpose UART.
Change-Id: I38ad5f19da6af5ed286ad3583f34b824a3660916
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68551
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the Intel iGPU as primary video adapter if enabled according
to EEPROM settings. The default is to use the ASPEED BMC as primary
video adapter, which only has a VGA output and the remote KVM output.
For now, use the FSP GOP driver to light up the iGPU. There are several
issues with libgfxinit on the Hermes, probably due to the unusual setup
of the iGPU's display outputs. They are routed to a mezzanine connector
for a piggy-back sub-board, of which there are two models. The Poseidon
piggy-back has two DisplayPort outputs and an HDMI output coming from a
MegaChips LSPCON. The Avalanche piggy-back routes all three DisplayPort
outputs from the iGPU into a FPGA, which acts as a DisplayPort sink.
Note that the FSP GOP only initializes at most 2 iGPU display outputs.
However, all three outputs function properly once OS (Windows, Linux)
graphics drivers take over.
Additionally, update the config file that Prodrive uses to build
coreboot images so that the iGPU can be used as primary.
TEST=Verify that the iGPU's outputs work properly in pre-OS, Windows and
Linux, on both the Poseidon and Avalanche piggy-backs.
Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62649
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update header files for FSP for Meteor Lake platform to
version 2364_00, previous version being 2344_00.
FSPM:
1. Address offset changes
FSPS:
1. Address offset changes
BUG=b:251733481
TEST=emerge-rex intel-mtlfsp
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8e4f62890b812f68dffe215e51c433510fca018f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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On the intel/glkrvp
compressed:
- romstage: 29659
- verstage: 31303
non compressed:
- romstage: 46244
- verstage: 47012
On qemu (with some additional patch to not run XIP)
compressed:
- romstage: 11203
non compressed:
- romstage: 13924
Even with a small romstage the size improvements are substantial,
which should result in a speedup when loading the stage. On the
up/squared loading romstage is sped up by 9ms.
TESTED: successfully boot the up/squared & google/vilboz.
Change-Id: I6906c8b6df45f2433d92d2ff1d1748cc4926c73a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Some platform run early stages like romstage and verstage from CAR
instead of XIP. This allows to link them like other arch inside the
_program region. This make in place LZ4 decompression possible as it
needs a bit of extra place to extract the code which is now provided by
the .bss.
Tested on up/squared (Intel APL).
Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch drops `ufs.asl` from the local SoC directory.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I84e0b51e74e2d6a7120f1d990152bc27e37a501f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68302
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
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This patch includes UFS ASL entry from common block ACPI code.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia77ea1c915d0dec991afa5b977af78487ae6a8b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68301
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
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This patch migrates UFS ASL entry from Alder Lake SoC to common
block ACPI code to be able to be utilized across different IA SoCs.
Additionally, migrate to ASL2.0.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2e803138a20fd1fc3cdcd5c0fbbb1254663bb8dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68300
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
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|
Change-Id: I1c00322d2b22e1fafffd6ebd66f2df14bcedbd89
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set _STA to 0xB for GOOG000C/GOOG000E devices to prevent showing
as missing drivers under Windows.
Change-Id: I0887fd6e18528d2c8523e7bc66db9efaa31adf5d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68462
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add VBT data files, ensure secondary VBTs compiled in as needed,
select INTEL_GMA_HAVE_VBT.
TEST=build/boot lindar variant with FSP/GOP display init, edk2 payload
Change-Id: I81022670fabda7994e292d333c999b508e61b469
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add VBT data files, ensure secondary VBTs compiled in as needed,
select INTEL_GMA_HAVE_VBT.
TEST=build/boot drawcia, mangolor variants with FSP/GOP display
init and edk2 payload
Change-Id: I58a2ed59bd858ce772e92f6659d341036823b11a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The ISH build target used for nissa is called adl_ish_lite: CL:3925007,
and by default the binary is installed as
/lib/firmware/intel/adl_ish_lite.bin
We could change the installed name, but it's nicer to keep it consistent
with the build target, so change the name in coreboot instead.
BUG=b:234776154
TEST=Build and boot nirwen, check firmware name is updated in SSDT
Change-Id: I983a38d08e758cf5a12a3f91a601c7e57d42c0cb
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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1. Set the PL1, PL2 and PL4.
2. Set PsysPL2 and PsysPmax.
BUG=b:253380352 b:253542746
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0a7ff64689b39e7754e0aed2f6869881a682fc93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68437
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This change disables unused PCIE RP8 and CLKSRC4. Without this change
storo cannot enter into s0ix properly.
BUG=b:219376808
TEST=Built and verified in storo
Change-Id: I9867825ce53de72ef73920c153002bc3be4dbd2d
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59985f283f1694beeacb0999340111146fa3f39b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
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Move i2c SoC related code from early_fch.c to i2c.c
TEST=build boards for each SoC
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Update the GPIO definitions for morgana per PPR #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7fa4aaf81b5487f7548f430cb35630aca8be732f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Remove the ACPI ALS device from the EC configuration for newer devices,
because some do not have light sensors, and those who do have their ALS
presented through the new EC sensor interface already.
Inspired from commit ("f13e2501525f ("UPSTREAM: mainboard/google/eve: Remove ACPI ALS device")
BUG=b:253967865
BRANCH=none
TEST=Boot a device and ensure that 'acpi-als' device is not present
in /sys/bus/iio/devices.
Change-Id: Ibcfa9e8c5a4679d557150998fd255789d3f8a272
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68493
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update SoC GPIO setting of camera according to beadrix schematics.
GPP_D13 : NC -> PLTRST (EN_PP2800_CAMERA)
BRANCH=dedede
BUG=b:247178737,b:244120730
TEST=on beadrix, validated by beadrix seconds_system_resume < 500 ms.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Id00cb85cdad900c03842ad69707966aa62410efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
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SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).
TEST=build glados w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.
Change-Id: Id8abf68ed2e9720b5580f7965208dbe36460af07
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).
TEST=build reef w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.
Change-Id: I4fe3092e620bcbc33b0411ea69e55154fc118aa4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).
TEST=build sarien w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.
Change-Id: I424033e087bc37c651a922273718fc229b720448
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add two memory parts and generate the associated DRAM part ID.
1) Hynix H58G66AK6BX070
2) Micron MT62F1G32D2DS-026 WT:B
BUG=b:251363645
TEST=none
Change-Id: Iceb31576533a5b29c5957170473152014fc7e9c8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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When the GSC is ready for the next transaction, it triggers a
GSC_AP_INT_ODL (active low) pulse with 100us duration to notify the AP.
Currently the TPM IRQ is configured as EDGE_RISING. Changing it to
EDGE_FALLING would speed up each register access by 100us. On Kingler,
this saves 20ms for the boot time (0.93s -> 0.91s).
BUG=b:235185547
TEST=emerge-corsola coreboot
TEST=Kingler booted without TPM errors
BRANCH=none
Change-Id: Id282e0f35694bd151781845cbd5aa4b389a30ddc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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To help make sure that future releases are done correctly and on time,
we are setting up a team with the shared responsibility for doing the
releases and maintaining the release notes, scripts, and documentation.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5ef5b10fce9b16241de548df225fd12c9a7e199f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Allows brya boards to use coreboot-generated FMAP layout
when building for non-ChromeOS target.
TEST=build/boot brya/banshee with edk2 payload, non-ChromeOS build
Change-Id: I21c2247c034d9bdc49f66771a93abad542a1e1fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Allows dedede boards to use coreboot-generated FMAP layout
when building for non-ChromeOS target.
TEST=build/boot dedede with edk2 payload, non-ChromeOS build
Change-Id: Icb975455cde0d75a5af9130ba3e82a4fb0df5613
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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When "make symlink" is run, it looks for symlink.txt files recursively
under site-local directory, and make symbolic links accordingly.
"make clean-symlink" removes the symbolic links made.
One application is for development of support for new processors and/or
new mainboards, where new directories are added, along with some common
code changes.
Change-Id: I3fa119675ecca1626d70375a61e8a71abec6a53b
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6f0963417c7c580f903922ac88c95569c8782bdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Setting up HT resource seems to be copied from the old native family10
code. It is however not used as no device has a child device below 18.0
in any of the fam15tn board device trees.
Setting up HT resources is therefore done by AGESA and resource
allocation mostly happens to work.
Change-Id: I7edf19f71095fb38161f19d511997cdc2fe0d76c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Setting up HT resource seems to be copied from the old native family10
code. It is however not used as no device has a child device below 18.0
in any of the fam15tn board device trees.
Setting up HT resources is therefore done by AGESA and resource
allocation mostly happens to work.
Change-Id: Id95e2dec4a6f3e70234fff1df67ee61e08731400
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68411
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements upgrade function.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS processor upgrade value is correct.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I5796d31fa2d31b17afa5eddde0799b0f68d69909
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68024
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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X9SAE has a PS/2 controller for keyboard and mouse but its definition
in ACPI used to be missing, and X9SAE used to use a generic SuperIO
support initially generated by autoport, so the full NCT6776 support
is added here like x9scl.
Test result:
Log lines like
i8042: PNP: No PS/2 controller found.
i8042: Probing ports directly.
serio: i8042 KBD port at 0x60,0x64 irq 1
serio: i8042 AUX port at 0x60,0x64 irq 12
mousedev: PS/2 mouse device common for all mice
become
i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at
0x60,0x64 irq 1,12
serio: i8042 KBD port at 0x60,0x64 irq 1
serio: i8042 AUX port at 0x60,0x64 irq 12
mousedev: PS/2 mouse device common for all mice
and more sub-devices within SuperIO is handled by the PNP driver.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ie5e73e8c3fc4e57c6683d7a7ca70e96c64dd9366
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This code is identical for all non-CAR AMD SoCs, so factor it out to
soc/amd/common/block/cpu/noncar/bootblock.c to avoid code duplication.
Also integrate the bootblock.c improvement to include cpu/cpu.h which
provides cpuid_eax from commit 68eb439d8091 ("soc/amd/picasso: Clean up
includes").
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42e4aa85efd6312a3ab37f0323a35f6dd7acd8e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Rename soc/amd/common/block/cpu/smm/smi_ampc_helper.c to smi_apmc.c and
add the fch_apmc_smi_handler function.
Remove the duplicated function from picasso, cezanne, mendocino, and
morgana SoC.
The stoneyridge soc does not implement the APM_CNT_SMMINFO handler, so
give the handler a unique name that does not conflict with the common
handler name.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2e6fb59a1ee15b075ee3bbb5f95debe884b66789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68441
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If68ce4fef69a2466e76fc7fc504c00ee915e3e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iae811c97aba15dd6c9c740aedd7c802e14f53788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:244620955
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia6cb56e76bc4e245a32f29b19226fa4fae330c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
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Change-Id: I9b03ccc1100307e3c24393903600d18f6cc9abdc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68378
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
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Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie6ecb3ed97ed0581300411962c3b1bba416e0224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68242
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The 4.19 release is planned for January 2023. Please add any updates to
the coreboot code that are should go into the notes between now and
then. This helps in that you get to phrase the update the way you want,
and it lessens the load for the release managers.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib5a7ddfc6cb1a8e0a485c1e1810631c86f4083c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5cf38463e44f9abaadb4dc47dbf48ef0f0514bc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Enable PMC in devicetree so that resources are allocated properly
for it.
Tested on StarLite Mk III & IV, and both can power on correctly.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib4384b55751a9979e470dd04f6814d4ca170ff34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67409
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reset the XHCI controller prior to S5 to avoid XHCI preventing shutdown.
Linux needs to put the XHCI into D3 before shutting down but the
powerstate commands do not perform a reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3be70443eb85a7dff8055c9de0ca2fd89f4fc88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67678
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure FSP S UPDs to allow coreboot to handle the lockdown.
The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).
The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaecb83c3bc9c75dab427a3ca54da1e6a8f87cf9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This AMD reference board is called Pademelon and not Padmelon, so fix
the name in coreboot. Also update the corresponding documentation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4ed869627af11b607f910644b6f21898f7c7bba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Cezanne has two SATA controllers, but doesn't select
SOC_AMD_COMMON_BLOCK_SATA, so it's not added to the SATA devices in the
Cezanne chipset devicetree.
Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This removed the need to maintain a PCI driver.
Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This removes the need for a PCI driver.
Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This removes the need for a PCI driver.
Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If5447f9272183f83bc422520ada93d3cfd96551e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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