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2022-12-14mb/google/skyrim: Enable PCIe RTD3 supportJasonNien
Add PCIe RTD3 support for Skyrim BUG=b:245550573 TEST=Boot/Reboot cycles and Suspend_stress_test 10 times Signed-off-by: JasonNien <finaljason@gmail.com> Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/amd/morgana/Kconfig: Remove TODO after reviewFred Reitberger
Remove more TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7fd9666a69d9a2b0902fa28ab0af0187198297ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/70466 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14util/cbfstool: Fix building with clang & -WshadowArthur Heymans
Clang -Wshadow is more rigorous than GCC and picks a shadowing of the optarg global variable in /usr/include/bits/getopt_core.h . TESTED: builds with both gcc and clang. Change-Id: Ifc362c84511abb6a000671f03498e841d7747074 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70508 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-14soc/amd/common/block/espi_util: drop unneeded check in espi_get_configFelix Held
Since soc_get_common_config will either return a valid pointer or cause a linking error, this function will also return a valid pointer or cause a linking error, so no need for additional runtime checks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/*/config: drop invalid commentFelix Held
Since commit 28e61f16341f ("device: Use __pci_0_00_0_config in config_of_soc()") config_of_soc() was changed form being an actual function to a macro for the __pci_0_00_0_config struct pointer generated by util/sconfig. This change didn't only improve linker optimizations, but also turned runtime errors into link-time errors, so it's guaranteed that __pci_0_00_0_config won't be NULL and config_of_soc() won't "return" NULL. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/espi_util: make espi_set_initial_config non-fatalFelix Held
Improve the espi_set_initial_config implementation so that a failure in there due to an invalid configuration won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatalFelix Held
Improve the eSPI pin configuration setup so that a failure in there won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. This will prevent an early boot failure if the EC is missing or the eSPI interface is in a non-functional state. Also slightly shorten the function names so that the code still fits into 96 chars. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-12-14device/cpu_device.c: Zero initialize structArthur Heymans
Don't rely on this being 0. Change-Id: I7c0d16b6a265bf9c7abcfdf2f18a43706ee03ea1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69752 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14cpu/x86/mp_init.c: Improve AP entry pointArthur Heymans
Make sure that a pointer exists before dereferencing it. Change-Id: I1a9833bb9686451224249efe599346f64dc37874 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14tests/Makefile.common: Allow to disable test framework with parameterJakub Czapiga
Test framework can be used as a base for other test-like utilities - for example look at screenshoot utility in depthcharge. Sometimes CMocka is not required and even makes things problematic. Thanks to this patch one can set -no_test_framework parameter to instruct framework not to include and link selected test against CMocka library. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I01dc7c6c50e6ae2f7f71bd6752c2d5f2cc7c3cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/70107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com>
2022-12-14soc/intel/common: Add helper function to get DP modeSridhar Siricilla
The patch adds helper function to get the DP mode. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-14cpu/intel/206ax: Fix generating C state entriesArthur Heymans
The struct device passed to this function is the cpu cluster and not individual lapic. This fixes a regression introduced by cdb26fd (cpu/intel/model_206ax: Remove fake lapic device) Change-Id: I586e13a723303b8d639d526a175bd6828465a607 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-14soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macroSubrata Banik
This patch drops the redundant macro to define CPU BCLK and instead uses `CPU_BCLK_MHZ` config to calculate the `smbios_cpu_get_max_speed_mhz`. TEST=Able to see max cpu speed is correct in smbios table while trying on Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Drop NEM supportSubrata Banik
This patch drops NEM support from MTL and enables eNEM support. BUG=b:217130861 TEST=Able to build and boot Google/Rex in eNEM mode. Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Add required configs to enable eNEMSubrata Banik
This patch combines all required configs under one umbrella config named `METEORLAKE_CAR_ENHANCED_NEM`. MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not selected. BUG=b:217130861 TEST=Able to build and boot Google/Rex. Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Reorg TCSS related configsSubrata Banik
This patch moves all required TCSS related configs under one umbrella config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will help in future to deselect the TCSS support for MTL SoC SKUs. TEST=Able to build and boot Google/Rex. Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14drivers/wwan/fm: Fix typoSubrata Banik
This patch fixes a typo by adding `Arg0 = 0` to define warm reset. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I92b81697a254c9dab127b200174d32554db1b5cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/70721 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14vc/intel/fsp/mtl: Update header files from 2404_00 to 2431_80Subrata Banik
Update header files for FSP for Meteor Lake platform to version 2431_80, previous version being 2404_00. FSPM: 1. Address offset changes FSPS: 1. Address offset changes Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enableSubrata Banik
This patch calls into a helper function to fill `2nd microcode loading FSP UPD` if FSP is running CPU feature programming. This patch is backported from commit fad1cb062e29c5e3a5bcfb6b67c3ce01ed765254 (soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable). Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Remove `FIXME` as SkipMpInit UPD has deprecatedSubrata Banik
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP doesn't like to allow an option for boot firmware to perform CPU feature programming being independent of FSP. Change-Id: I6447937838ab91551d172936cbb4201ea86a614b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. This patch is backported from commit 3f980ca7be36339ad2cb5700bad0658643966cf2 (soc/intel/alderlake: Drop enable_bios_reset_cpl() function). Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Enable VMX and VTDSubrata Banik
Drops the `FIXME` comment and relevant code as this patch enables VMX and VTD. This patch also fixes the problem of additional reboot on every warm boot due to overriding the CPU soft-strap. TEST=No extra reboot seen while issuing warm reset from kernel console. without this patch: 950:calling FspMemoryInit 1,225,259 (20,537) 951:returning from FspMemoryInit 10,334,707 (9, 109,447) with this patch: 950:calling FspMemoryInit 1,225,259 (20,537) 951:returning from FspMemoryInit 1,334,707 (109,447) Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14mb/google/hatch/dratini: increase power enable to reset deassert delayEran Mitrani
With 1ms delay, reset is de-asserted too soon, before power is fully up, causing a glitch to the reset signal. The issue is resolved with 4ms delay. TEST=tested on dratini device and observed the issue is resolved. BUG=b:260253945 Change-Id: I5c3edbc6ac90d5042c2d3c5b01573d4bb1ea676d Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70666 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14mb/google/poppy: Add support for a variant finalize functionTarun Tuli
Add a hook to allow a variant finalize to be called at the end of ramstage. BUG=b:245954151 TEST=Builds successfully Change-Id: I00c091051e3499ca94b286d7fbe0a7a8bd38e635 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70319 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14sio/winbond/w83627hf/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I6858ddaa8b70194ffdd3b4edcb0ee57aec262b48 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/braswell/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I2dd154c3d4e152a14783ea82e08a7d1257abebc3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/cannonlake/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I9ddb71d93781c813a69dc72ce0589ffaea7b64c7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/icelake/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I12560d151d26186e1f4eb0165aa8cef33b7a16aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/baytrail/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ic171f3343bb35e43be5fdb50c5c926eede6a1d93 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14mb/google/cyan/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I349d1e7d3027097c5db4da96e2376831fff61b04 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/skyrim/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ib75ccc10c8086086f5db4ced1163b74c9835364b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/slippy/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I950d776a712a104f2caed614886ce2527028ead7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14sio/winbond/w83667hg-a/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I3809880312af4736407e361da53f0424280e43d4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/kahlee/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ib2ba6b5c14f6699dc6c0734724a6784e3400a467 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/jecht/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: If6c37cc2ce51780e0bae007d884d8f77b20847fb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/aopen/dxplplusu/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I04f61df6b651058060b88e5f5679a0dd5270e66d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14ec/smsc/mec1308/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I0a419c861e84cd96e8337957dc62a7ca5b981e14 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14ec/quanta/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I00a6ece73048209861221cba5f2c7381adfa54b9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14ec/google/chromeec/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I2cdb1c9ae3a33bfc72767ff60d8948054d4e151a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14ec/lenovo/h8/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I1c68816f47aa3ed0ab3bf55d4cfde71d5838d051 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14sb/intel/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I94b2e6ecb90a2616e184ae9331c397c75089e373 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/51nb/x210/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ic0ae4903546446322c2c47cab00de4c3af6c9d98 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14superio/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ibbecba97dd1628889539c2962dd31964c252c8bb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14vc/google/chromeos/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I8b2d97063ba199274c1072ba3a12613162a17ef1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14drivers/intel/gma/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ifd3a814228df6a399fe1110abf5b5bc18e6fd6d2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-13Documentation: Add wake source info to device tree documentationRaul E Rangel
The device tree documentation was promoting using a GPIO wake event and a GPE wake event. We should only ever have one. This wasn't actually causing a problem because the wake bit was set on the `irq` property, but the IO-APIC can't actually wake the system, so it was a no-op. This change fixes up the markdown so it's formatted correctly, and also adds a section explaining what the different wake configurations are. BUG=b:243700486 TEST=mdformat Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67385 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13util/release: Update gerrit_stats script to latest versionMartin Roth
This updates a number of things: - Move the cache directory under the .local directory - Reformat & clean up with perltidy. Add the perltidy command line. - Add username and email aliases to clean up duplicates and unknown email addresses. - Use full length commit IDs - Collect patch commenters - Check variables before using them as key values - Ignore patch submit time, just collect the date - Get stats about large patches - Format the output better Example output: Statistics from commit c35f2819348501579a32e870e21f5f1b062d26e8 to commit f8fbf0917c722378454b07c2e8ec1a3f87b324ae Patch, Date, Owner, Author, Submitter, Inserted lines, Deleted lines, Subject, Reviewers, Commenters "f8fbf0917c722378454b07c2e8ec1a3f87b324ae", 2022/12/10, Frank Chu, Frank Chu, Martin Roth, 22, 1, "mb/google/brya/var/marasov: Change FSP board type to Type3", "Frank Chu, Eric Lai" , "-" "5778e06771627a5541ca2b137e783f47257f05ec", 2022/12/10, Dinesh Gehlot, Dinesh Gehlot, Subrata Banik, 30, 1, "soc/intel/meteorlake: Drop casts around `soc_read_pmc_base()`", "Kapil Porwal, Elyes Haouas" , "Subrata Banik" "ed8bdefcdf6c19258febb9931d1e8eb12b958bcc", 2022/12/10, Jamie Ryu, Jamie Ryu, Felix Held, 76, 3, "mb/intel/mtlrvp: Add MTL-P RVP board ids", "Usha P, Sridhar Siricilla, Eric Lai, Subrata Banik" , "Eric Lai, Subrata Banik, Harsha B R, Angel Pons" - Total Commits: 985 - Average Commits per day: 17.85 - Total lines added: 61475 - Average lines added per commit: 62.41 - Number of patches adding more than 100 lines: 49 - Average lines added per small commit: 37.82 - Total lines removed: 758022 - Average lines removed per commit: 769.57 - Total difference between added and removed: -696547 === Authors - Number of commits === Author ,Ptchs ,Revws , Cmnts , Sbmts , Email , Prcnt, Last commit , Earliest_commit Elyes Haouas , 126 , 90 , 28 , 0 , ehaouas@noos.fr ,12.79%, 2022/12/10 , 2022/10/17 Arthur Heymans , 107 , 99 , 28 , 40 , arthur@aheymans.xyz ,10.86%, 2022/12/10 , 2022/10/17 === Authors - Lines added === Martin Roth , 10103, 16.434% Kyösti Mälkki , 6044, 9.832% Arthur Heymans , 3314, 5.391% === Authors - Lines removed === Arthur Heymans , -741944, 97.879% Felix Held , -3031, 0.400% Kyösti Mälkki , -1680, 0.222% === Reviewers - Number of patches reviewed === Angel Pons , 272, 27.614% Eric Lai , 201, 20.406% Felix Held , 106, 10.761% === Submitters - Number of patches submitted === Name , #, total%, Own, own%, Other, other% Felix Held , 482, 48.934%, 56, 11.62%, 426, 88.38% Martin Roth , 179, 18.173%, 42, 23.46%, 137, 76.54% Subrata Banik , 54, 5.482%, 31, 57.41%, 23, 42.59% Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie1694116ab36ca4db25d13935adadca10e50068f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-13soc/amd/morgana: Enable GPP clk req disablingFred Reitberger
Enable GPP clk req disabling on morgana after reviewing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13util/spd_tools: Format lp5 file to golang standardsRobert Zieba
This commit formats the lp5.go file according to goland standards. TEST=Built spd_tools Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: If102c90f732efc51a90de6cc0e18c879d56699b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-12-13soc/intel/common/block: add definition of GPIO configurationJeff Li
Add two macros: - PAD_CFG_NF_OWNERSHIP() - PAD_CFG_GPIO_OWNERSHIP() to support setting the Host Software Ownership (own) fields. Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com> Change-Id: Ia3f2ad8658b751156456b69366fa4b1badb8b595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70421 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-13mb/google/guybrush,skyrim: use gpio.h include everywhereFelix Held
Now that gpio.h will only include the defines in the IASL case, gpio.h can be included instead of soc/gpio.h in the files that will be directly or indirectly included in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13include/gpio: skip everything but soc/gpio.h include in ASM & ACPI casesFelix Held
When gpio.h gets directly or indirectly included in the DSDT ar an assembly file, everything but the preprocessor defines for the GPIOs shouldn't be included to keep IASL or the assembler happy. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I046ed87d3947ba5b1fcd0bdd4cffcda57bc13404 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70509 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13vc/eltan/security/mboot/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ie2c4a6c2bb55af56cb6e0b013b1a2ed9baa787ef Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70460 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-13mb/google/nissa/var/nivviks,yaviks: Add DmaProperty for ISHReka Norman
On nissa, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on nivviks and yaviks. BUG=b:259716145 TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA-FQ After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA Change-Id: Iaddb24580bda77df0c70ff58eb098213f8b509ad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13drivers/intel/ish: Allow adding DmaProperty to _DSDReka Norman
On nissa, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Allow adding DmaProperty to the _DSD of the ISH device. This will result in the kernel marking the device as untrusted. BUG=b:249846505 TEST=Check SSDT is correct, and kernel detects the DmaProperty and firmware-name properties. SSDT entry on yaviks with both add_acpi_dma_property and firmware_name set in devictree: Scope (\_SB.PCI0.ISHB) { Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "firmware-name", "adl_ish_lite.bin" } }, ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } Change-Id: Ie1539fc757e72e995e98c3ecf83e705e3bede8c0 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/amd/morgana: Update pci int defsFred Reitberger
Update pci int defs per preview of next ppr after rev 1.52, #57396 Update birman and mayan mainboards to remove deleted PIRQs. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13mb/google/brya/var/lisbon: Add Wifi SAR for lisbonRobert Chen
Add wifi sar for lisbon. BUG=b:260938760 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: Ia347c4cf56bec971700bb53a5804e36e0bad82fb Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70483 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13mb/google/brya/var/gladios: Add Wifi SAR for gladiosRobert Chen
Add wifi sar for gladios. BUG=b:260950906 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I4cd015f17c4ddd28414f51a873ae4afc37863708 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70605 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/intel/cmn/tcss: Skip sending CONN IPC command during S3 resumeSubrata Banik
This patch skips sending CONN IPC command to PMC if system is resuming from S3. Sending CONN IPC command as part of `tcss_configure_dp_mode()` function results into ERROR while system is resuming from S3. Additionally, skip `configure_aux_bias_pads()` during S3 resume. BUG=b:260984500 TEST=Able to test on Google/Rex. Without this patch: [ERROR] pmc_send_ipc_cmd status: fatal [ERROR] Port 1 connect request failed [SPEW ] [TCSS] TcssInit() - End With this patch: No error seen during S3 resume. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-13soc/qualcomm/sc7280: Update Skuid to support pro/non-proSudheer Kumar Amrabadi
Tranferring a bit to DC through Skuid to update the regulator node in order to support pro and non-pro BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68385 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/qualcomm/sc7280: Add API to differentiate PRO and NON_PRO SKUsSudheer Kumar Amrabadi
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To reduce the binary footprint for chipinfo structure, change its members range from uint32_t to uint16_t. Add helper functions for reading and matching jtagid. Modified socinfo_modem_supported() API to utilize helper functions. BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68384 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13util/genbuild_h: Update printf %d to %s for sh compatabilityMartin Roth
When printing a date, genbuild_h is printing it as two digits, using a leading zero if the value is below 10. The shells like bash, dash, etc don't fully import the numbers 08 and 09 when using the printf conversion specifier %d. They apparently interpret the numbers as octal and only import the leading 0, dropping the 8 or 9. This isn't an issue for 01 to 07, because those are valid octal numbers, so %d prints them without an issue. Because 08 and 09 are not valid octal, various shells return different errors: Example shell returns for 'printf "%d" 08': bash: printf: 08: invalid octal number dash: printf: 08: not completely converted fish: 008: value not completely converted yash: printf: `08' is not a valid integer sash: printf: 08: not completely converted To prevent this, just print all of the values as strings. zsh just seems to ignore the possibility of the value being octal and prints the value as a single digit 0-9. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I97b6aa74d74379f6bdc1f0fceecc8002cc36ca09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70478 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13mb/google/brya/var/marasov: Enable PIXA touchpadFrank Chu
Correct touchpad setting to make touchpad function workable. BUG=b:261393412 BRANCH=firmware-brya-14505.B TEST=Built and verified touchpad function Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I3c816ce4293ae362f0e5c18171f296d42b4307c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70440 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13mb/intel/coffeelake_rvp/Makefile.inc: Avoid link to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I178c849d07e61d7a237629f3be1b52d3b4abb513 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/xeon_sp/nb_acpi.c: Use read{16,32,64}p()Elyes Haouas
Change-Id: I89bfbab7850dd9bd29ca2097ee2efce058720ca7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/broadwell/early_init.c: Use {read,write}32p()Elyes Haouas
Change-Id: I80b1535b86c7fc05354404d628a0a527a6701498 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/baytrail/pmutil.c: Use {read,write}32p()Elyes Haouas
Change-Id: I6168be71913d00eb59d38dd4c5cf8f9c7f7ab678 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/apollolake/pmutil.c: Use {read,wrire}32p()Elyes Haouas
Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/alderlake/bootblock: Use 'false/true' macrosElyes Haouas
Change-Id: Ic40f1e935b244f39fa3c1322e5128465c57f5e26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70579 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/alderlake/bootblock: Use read32p()Elyes Haouas
Change-Id: I3062e5b8a0524059b9695dfd32254c5c53598925 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70578 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/mediatek/common: Use write32p()Elyes Haouas
Change-Id: I83707071fe1801322dffad7fc89afaef5617f3c7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-13soc/cavium/cn81xx: Use write{32,64}p()Elyes Haouas
Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12{drivers,superio}/acpi: Replace ShiftRight(a,b) with ASL 2.0 syntaxFelix Singer
Replace `ShiftRight (a, b)` with `a >> b`. Change-Id: I0751d00186e8dff38e02e7bf7d8ebf5a17514a58 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I97332e3008ed2e26a75c067baffdabfc7cfcf65f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Subtract(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b)` with `a - b`. Change-Id: I77028c17dcd7925a392d56488d34090837d660f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12{soc,superio}/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: If6455ab2c91619f884abae227f1ac2e2c2af6ba9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b)` with `a + b`. Change-Id: I0b7f22acf153fe02b471c196f8161fc0fa5a1450 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70624 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`, respectively `a += b` where possible. Change-Id: I96390f565d6c1ca0f4e06db9ad07af784051650c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70622 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12mb/google/jecht/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual (a, b)` with `a <= b`. Change-Id: I4af47fdf5bab57c6bbfe417f55de35b074753120 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70621 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12ec/lenovo/h8/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual (a, b)` with `a <= b`. Change-Id: I76855f9d4564fc08cd70456e2a0b1514cd73e35f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70620 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual (a, b)` with `a != b`. Change-Id: Ia1bd22a62ec2868324a88400e27ed52c9f169751 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70619 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/glados/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: Ic3a49828551b6da45999ff55539d5e3449d475e3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70598 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/rambi/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: Ief985f8b7b14e8879a068140cb1f9b28c7336e94 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70597 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/cyan/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I9441988c0bf6d07641595a3b501c2af5230ba131 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70596 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/slippy/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I50c1831c909163b8eb9b91d6ceb267bd8cc41e11 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70595 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/jecht/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I74a6c949fa08a6eb712c053137369242e20e78fe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70594 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/braswell/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I7b74d026d0800df647fb0c981fa7865be492d3ac Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70590 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/baytrail/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I9d50ddcb4427774681aedba945079f5d04401f07 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70589 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/icelake/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I36137cbf63a36e68480029058f4426ed80ff6e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70588 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/lenovo/s230u/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I710d9c8c767a688f423d5a7e3e2708eb6aef11fc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70587 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/aopen/dxplplusu/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I4fa3942216f1638abeafa0c562f4d6a2a499254b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70586 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/intel/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I99f34d4c03b0687b8e0c2e4aee85f196679bcf52 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12soc/intel/acpi: Replace Decrement(a) with ASL 2.0 syntaxFelix Singer
Replace `Decrement (a)` with `a--`. Change-Id: I5c9290aaa9fc969368d5934e4f48a75d915ca5ff Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12ec/clevo/it5570e/acpi: Replace Index(a, b) with ASL 2.0 syntaxFelix Singer
Replace `Index (FOO, 1337)` with `FOO[1337]`. Change-Id: If035eac6b6eb06f79eb6596364bc41069ba42f70 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12ec/purism/librem-ec/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ie29511ad0b8e24feb478152009d7f4e8ed3ad26d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2022-12-12mb/acer/aspire_vn7_572g/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ie26b623a3848b929b83aad5931b1ecd90b342d2c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2022-12-12sb/intel/common/acpi_pirq_gen.h: Fix conflicting types for ↵Elyes Haouas
'is_slot_pin_assigned' Found using 'Wenum-int-mismatch' (GCC-13: default with -Wall): src/southbridge/intel/common/acpi_pirq_gen.c:69:6: error: conflicting types for 'is_slot_pin_assigned' due to enum/integer mismatch; have 'bool(const struct slot_pin_irq_map *, unsigned int, unsigned int, enum pci_pin)' {aka '_Bool(const struct slot_pin_irq_map *, unsigned int, unsigned int, enum pci_pin)'} [-Werror=enum-int-mismatch] 69 | bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map, | ^~~~~~~~~~~~~~~~~~~~ In file included from src/southbridge/intel/common/acpi_pirq_gen.c:8: src/southbridge/intel/common/acpi_pirq_gen.h:91:6: note: previous declaration of 'is_slot_pin_assigned' with type 'bool(const struct slot_pin_irq_map *, unsigned int, unsigned int, unsigned int)' {aka '_Bool(const struct slot_pin_irq_map *, unsigned int, unsigned int, unsigned int)'} 91 | bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map, | ^~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Change-Id: Ie91947d00feaae42314ec2d1291f39d667a85346 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70387 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-12soc/apollolake: Add DPTF HIDsSean Rhodes
Add the HIDs that Windows uses for the DPTF driver. Change-Id: Ic0cb4a45b5ebaf777a09bed1e5836e8afd873657 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66013 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12cpu/x86/mtrr/mtrr: fix printk format stringsFelix Held
Commit 4c3749884d71 ("cpu/x86/mtrr: Print cpu index number when set up MTRRs for BSP/APs") added the CPU index number to some prints, but used %x as format specifier. The cpu_index() call however has a return type of unsigned long, so %lx needs to be used instead. For consistency, also change the type of the cpu_idx local variable in commit_fixed_mtrrs to unsigned long and adjust the printk format specifier accordingly. TEST=The code builds again on my computer Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b68f8355932b2b75db5f453a0a735185b24b02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70664 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>