diff options
Diffstat (limited to 'src')
51 files changed, 15 insertions, 143 deletions
diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl index c778376bf2..74193e1fa4 100644 --- a/src/acpi/acpigen_extern.asl +++ b/src/acpi/acpigen_extern.asl @@ -11,7 +11,3 @@ External (GNVS, OpRegionObj) External (DNVS, OpRegionObj) #endif - -#if CONFIG(CHROMEOS_NVS) -External (CNVS, OpRegionObj) -#endif diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index 7b9b2d823e..b8be798117 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -4,7 +4,6 @@ #if CONFIG(CHROMEOS_NVS) /* Chrome OS specific */ -#include <vendorcode/google/chromeos/acpi/gnvs.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 28c2b82fed..b646e0c13c 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -24,7 +24,7 @@ #include <timer.h> #include <timestamp.h> #include <types.h> -#include <vendorcode/google/chromeos/gnvs.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <version.h> static boot_state_t bs_pre_device(void *arg); diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c index 2dd2d57241..252763b996 100644 --- a/src/mainboard/amd/majolica/mainboard.c +++ b/src/mainboard/amd/majolica/mainboard.c @@ -7,7 +7,6 @@ #include <soc/acpi.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -95,8 +94,6 @@ static void mainboard_enable(struct device *dev) init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 12d5a68da6..f465d0775d 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "variant.h" @@ -29,7 +28,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7eba3c2c2f..b35e005405 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -4,7 +4,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" @@ -25,7 +24,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 6287d2ceb5..b07a15166f 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <ec/ec.h> #include <soc/ramstage.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <fw_config.h> static void add_fw_config_oem_string(const struct fw_config *config, void *arg) @@ -60,7 +59,6 @@ static void mainboard_dev_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->get_smbios_strings = mainboard_smbios_strings; } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 6145dc73d4..87ce61f2e1 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -14,7 +14,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <ec/quanta/ene_kb3940q/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> static unsigned int search(char *p, char *a, unsigned int lengthp, unsigned int lengtha) @@ -258,7 +257,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index b8266b31dc..1e0006ce01 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(struct device *dev) @@ -16,7 +15,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index dba4795293..700b3e368a 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -9,7 +9,6 @@ #include <security/tpm/tss.h> #include <soc/soc_chip.h> #include <vb2_api.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_update_soc_chip_config(void) { @@ -68,7 +67,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c index e1cdb96959..9812d9fea5 100644 --- a/src/mainboard/google/deltaur/mainboard.c +++ b/src/mainboard/google/deltaur/mainboard.c @@ -4,14 +4,8 @@ #include <baseboard/variants.h> #include <device/device.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; @@ -26,5 +20,4 @@ static void mainboard_chip_init(void *chip_info) struct chip_operations mainboard_ops = { .init = mainboard_chip_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index d44c7b19d3..7c34c0d5c4 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -4,7 +4,6 @@ #include <smbios.h> #include <soc/ramstage.h> #include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, @@ -32,12 +31,6 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(gpio_table, num_gpios); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index 35c0a61953..4abb91e57f 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/nhlt.h> #include "gpio.h" @@ -58,7 +57,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 307faddbe6..13bc9b70ca 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -17,7 +17,6 @@ #include <soc/nhlt.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -223,7 +222,6 @@ static void mainboard_enable(struct device *dev) mainboard_set_power_limits(soc_conf); dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 0d6a49942e..faa80b9cbb 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -7,7 +7,6 @@ #include <gpio.h> #include <soc/nhlt.h> #include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static const char *oem_id_maxim = "INTEL"; @@ -96,7 +95,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } static void mainboard_chip_init(void *chip_info) diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index c50304dd5b..cab570672d 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -10,7 +10,6 @@ #include <gpio.h> #include <soc/acpi.h> #include <variant/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> #define BACKLIGHT_GPIO GPIO_129 #define WWAN_AUX_RST_GPIO GPIO_18 @@ -197,7 +196,6 @@ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; init_tables(); diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 93864b2ad1..86065f95d3 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/ramstage.h> #include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> void mainboard_silicon_init_params(FSPS_UPD *supd) { @@ -36,7 +35,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; variant_mainboard_enable(dev); } diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index fd7e9e2493..3c255b7871 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" static void mainboard_init(struct device *dev) @@ -15,7 +14,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e54ac742bf..2cd88b87f8 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -17,7 +17,6 @@ #include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> -#include <vendorcode/google/chromeos/chromeos.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -147,7 +146,6 @@ static void mainboard_enable(struct device *dev) /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } int mainboard_get_xhci_oc_map(uint16_t *map) diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index c4b621ac7a..4c98761685 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -16,7 +16,6 @@ #include <southbridge/intel/common/gpio.h> #include <smbios.h> #include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG(VGA_ROM_RUN) static int int15_handler(void) @@ -170,7 +169,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; #if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index fbebe576fc..a614763bda 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -20,7 +20,6 @@ #include <soc/nhlt.h> #include <soc/pci_devs.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> @@ -140,7 +139,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 16695dbeb8..eeb3ce4487 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -10,7 +10,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <ec/compal/ene932/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -61,7 +60,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 0a3fe1ff0f..0e6c7b98c6 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -6,7 +6,6 @@ #include <ec/ec.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -47,7 +46,6 @@ static unsigned long mainboard_write_acpi_tables(const struct device *device, static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index ef1acbdc59..257b8fab6c 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -8,7 +8,6 @@ #include <soc/gpio.h> #include <soc/int15.h> #include <bootstate.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(struct device *dev) { @@ -54,7 +53,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; /* Install custom int15 handler for VGA OPROM */ if (CONFIG(VGA_ROM_RUN)) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index e0078805ee..8cae9592d7 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -12,7 +12,6 @@ #include <soc/gpio.h> #include <soc/nhlt.h> #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> @@ -125,7 +124,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 6287628a88..8d619db5a7 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -5,7 +5,6 @@ #include <smbios.h> #include <soc/gpio.h> #include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG(GENERATE_SMBIOS_TABLES) /* mainboard silk screen shows DIMM-A and DIMM-B */ @@ -46,12 +45,6 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 90f28e7ec2..47f071c2a4 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -6,7 +6,6 @@ #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -66,7 +65,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 7f4e29d2e8..ae68a78dcb 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -6,7 +6,6 @@ #include <acpi/acpi.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/quanta/it8518/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -42,7 +41,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 9f8e646ae1..892da5185e 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -14,7 +14,6 @@ #include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> #include <vb2_api.h> @@ -78,7 +77,6 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->get_smbios_strings = mainboard_smbios_strings; variant_ramstage_init(); diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index ea292f163e..54da830004 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -23,7 +23,6 @@ #include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <commonlib/helpers.h> #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" @@ -203,7 +202,6 @@ static void mainboard_enable(struct device *dev) /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; } diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index 904673e340..f929b10d77 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -6,7 +6,6 @@ #include <drivers/intel/gma/opregion.h> #include <ec/ec.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <smbios.h> #include <stdint.h> #include <string.h> @@ -57,8 +56,6 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; - #if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) dev->ops->get_smbios_strings = mainboard_smbios_strings; #endif diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 04803fa37b..73fa9aa65c 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -5,7 +5,6 @@ #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -18,7 +17,6 @@ void mainboard_suspend_resume(void) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index aa073bcc8c..eb9a316a34 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -6,7 +6,6 @@ #include <nhlt.h> #include <soc/gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(void *chip_info) { @@ -45,7 +44,6 @@ static unsigned long mainboard_write_acpi_tables(const struct device *device, static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 6291d60993..3b6727b057 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -4,14 +4,12 @@ #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index cfbaf0d6c8..1cfa4e06d5 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -9,7 +9,6 @@ #include <nhlt.h> #include <soc/gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> @@ -55,7 +54,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index c8e9e411ea..2440651499 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -5,7 +5,6 @@ #include <baseboard/variants.h> #include <device/device.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(void *chip_info) { @@ -16,12 +15,6 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(pads, num); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index 315d47d2b0..efba386cf9 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -7,7 +7,6 @@ #include <soc/gpio.h> #include <soc/pcr_ids.h> #include <smbios.h> -#include <vendorcode/google/chromeos/chromeos.h> #define SERIAL_IO_PCR_GPPRVRW4 0x60C @@ -23,11 +22,6 @@ static void mainboard_init(void *chip_info) pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - const char *smbios_system_sku(void) { static const char *sku_str = "sku2147483647"; /* sku{0-1} */ @@ -36,5 +30,4 @@ const char *smbios_system_sku(void) struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index e502d84632..2b09df4596 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include <variant/gpio.h> @@ -21,7 +20,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 4136c368fd..b7c61f5058 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "gpio.h" @@ -82,7 +81,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/shadowmountain/mainboard.c b/src/mainboard/intel/shadowmountain/mainboard.c index 2783b4d2ce..f035aa9b53 100644 --- a/src/mainboard/intel/shadowmountain/mainboard.c +++ b/src/mainboard/intel/shadowmountain/mainboard.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <ec/ec.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(void *chip_info) { @@ -21,12 +20,6 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 82f46294cb..447ae31355 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(struct device *dev) @@ -17,7 +16,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 82877ed28e..bbce9278df 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <ec/ec.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <smbios.h> #include <string.h> @@ -29,12 +28,6 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index e9583acbfc..d17645ff03 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -2,14 +2,12 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index d804b2b974..9bf3b96e65 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -10,7 +10,6 @@ #include "onboard.h" #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> -#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -73,7 +72,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 6291d60993..3b6727b057 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -4,14 +4,12 @@ #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 500e632858..5a54d70527 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -33,8 +33,3 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) acpigen_pop_len(); } - -void chromeos_dsdt_generator(const struct device *dev) -{ - mainboard_chromeos_acpi_generate(); -} diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 456f2d7cb3..b9f807fada 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -97,4 +97,6 @@ Device (CRHW) } } +#include <vendorcode/google/chromeos/acpi/gnvs.asl> + #include "ramoops.asl" diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index 89e7055f89..7be45862b8 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This is the ChromeOS specific ACPI information needed by - * the mainboard's chromeos.asl + * chromeos.asl */ +External (CNVS, OpRegionObj) + Field (CNVS, ByteAcc, NoLock, Preserve) { VBT0, 32, // 0x000 - Boot Reason diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 730a4bbcf9..abdd6c2a77 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -26,6 +26,7 @@ void cbmem_add_vpd_calibration_data(void); void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); void chromeos_set_ecfw_rw(void); +void chromeos_init_chromeos_acpi(void); /** * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD @@ -45,16 +46,9 @@ struct cros_gpio; void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); /* - * Common helper function and delcarations for mainboards to use to generate - * ACPI-specific Chrome OS needs. + * Declaration for mainboards to use to generate ACPI-specific Chrome OS needs. */ void mainboard_chromeos_acpi_generate(void); -#if CONFIG(CHROMEOS) -struct device; -void chromeos_dsdt_generator(const struct device *dev); -#else -#define chromeos_dsdt_generator NULL -#endif enum { CROS_GPIO_REC = 1, /* Recovery */ diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 531463b273..7236662df7 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -98,7 +98,14 @@ void acpi_fill_cnvs(void) { const struct opregion cnvs_op = OPREGION("CNVS", SYSTEMMEMORY, (uintptr_t)chromeos_acpi, sizeof(*chromeos_acpi)); + + if (!chromeos_acpi) + return; + acpigen_write_scope("\\"); acpigen_write_opregion(&cnvs_op); acpigen_pop_len(); + + /* Usually this creates OIPG package for GPIOs. */ + mainboard_chromeos_acpi_generate(); } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index a25b2b0e24..a9f93d99cd 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -32,6 +32,4 @@ struct chromeos_acpi { u8 pad[298]; // dd6-eff } __packed; -void chromeos_init_chromeos_acpi(void); - #endif |