diff options
Diffstat (limited to 'src')
37 files changed, 37 insertions, 37 deletions
diff --git a/src/arch/arm/asmlib.h b/src/arch/arm/asmlib.h index cef0e7ea1a..6398cf20af 100644 --- a/src/arch/arm/asmlib.h +++ b/src/arch/arm/asmlib.h @@ -69,4 +69,4 @@ */ #define CALGN(code...) -#endif /* __ARM_ASMLIB_H */ +#endif /* __ARM_ASMLIB_H__ */ diff --git a/src/arch/arm/include/arch/clock.h b/src/arch/arm/include/arch/clock.h index c19230eb62..77d09d8ef0 100644 --- a/src/arch/arm/include/arch/clock.h +++ b/src/arch/arm/include/arch/clock.h @@ -20,4 +20,4 @@ void set_cntfrq(uint32_t); -#endif //__ARM_CLOCK_H_ +#endif /* __ARM_CLOCK_H_ */ diff --git a/src/arch/arm64/include/arch/boot/boot.h b/src/arch/arm64/include/arch/boot/boot.h index bff7fe63cd..ae6913cc0c 100644 --- a/src/arch/arm64/include/arch/boot/boot.h +++ b/src/arch/arm64/include/arch/boot/boot.h @@ -18,4 +18,4 @@ #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_AARCH64 -#endif /* ASM_ARM_BOOT_H */ +#endif /* ASM_ARM64_BOOT_H */ diff --git a/src/arch/arm64/include/arch/clock.h b/src/arch/arm64/include/arch/clock.h index c19230eb62..77d09d8ef0 100644 --- a/src/arch/arm64/include/arch/clock.h +++ b/src/arch/arm64/include/arch/clock.h @@ -20,4 +20,4 @@ void set_cntfrq(uint32_t); -#endif //__ARM_CLOCK_H_ +#endif /* __ARM_CLOCK_H_ */ diff --git a/src/arch/arm64/include/arm_tf_temp.h b/src/arch/arm64/include/arm_tf_temp.h index c9fe8c15f9..8db5dcb49c 100644 --- a/src/arch/arm64/include/arm_tf_temp.h +++ b/src/arch/arm64/include/arm_tf_temp.h @@ -104,4 +104,4 @@ typedef struct bl31_params { image_info_t *bl33_image_info; } bl31_params_t; -#endif /* __ARM_TF_H__ */ +#endif /* __ARM_TF_TEMP_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 51a754a8af..94078e970c 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -586,4 +586,4 @@ void tlbivaa_el1(uint64_t va); #endif // __ASSEMBLY__ -#endif // __ARCH_LIB_HELPERS_H__ +#endif /* __ARCH_LIB_HELPERS_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index 3edb76c5a4..7c3b6a74d6 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -157,4 +157,4 @@ void mmu_enable(void); /* Disable the MMU (which also disables dcache but not icache). */ void mmu_disable(void); -#endif // __ARCH_ARM64_MMU_H__ +#endif /* __ARCH_ARM64_MMU_H__ */ diff --git a/src/device/oprom/yabel/pmm.h b/src/device/oprom/yabel/pmm.h index 6416c118f0..9eb61c37b1 100644 --- a/src/device/oprom/yabel/pmm.h +++ b/src/device/oprom/yabel/pmm.h @@ -43,4 +43,4 @@ void pmm_handleInt(void); void pmm_test(void); -#endif // _YABEL_PMM_H +#endif /* _YABEL_PMM_H_ */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h index 29d6a6cf7e..66c8a3c26f 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/gop.h +++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h @@ -20,4 +20,4 @@ const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); -#endif /* _FSP_GOP_H_ */ +#endif /* _FSP1_1_GOP_H_ */ diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h index 4ff2c3e375..63cdf6930a 100644 --- a/src/drivers/maxim/max77686/max77686.h +++ b/src/drivers/maxim/max77686/max77686.h @@ -127,4 +127,4 @@ int max77686_volsetting(unsigned int bus, enum max77686_regnum reg, */ int max77686_disable_backup_batt(unsigned int bus); -#endif /* __MAX77686_PMIC_H_ */ +#endif /* __MAX77686_H_ */ diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 853179564e..d7974b5a33 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -37,4 +37,4 @@ static inline void __ne2k_tx_byte(u8 data) {} static inline void __ne2k_tx_flush(void) {} #endif -#endif /* _NE2K_H */ +#endif /* _NE2K_H__ */ diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index d689ff391e..4373c78e2b 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -487,4 +487,4 @@ #define POST_INTR_SEG_JUMP (0x0F0) -#endif /* THE_ALMIGHTY_POST_CODES_H */ +#endif /* POST_CODES_H */ diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h index 08aca2fd02..648a789bd8 100644 --- a/src/include/cpu/x86/bist.h +++ b/src/include/cpu/x86/bist.h @@ -9,4 +9,4 @@ static void report_bist_failure(u32 bist) } } -#endif /* CPU_Xf86_BIST_H */ +#endif /* CPU_X86_BIST_H */ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index aaf861036b..de75aee452 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -309,4 +309,4 @@ mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr); mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd); -#endif /* DEVICE_DRAM_DDR3_H */ +#endif /* DEVICE_DRAM_DDR3L_H */ diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h index edce249767..60dc00fe2b 100644 --- a/src/northbridge/amd/amdfam10/chip.h +++ b/src/northbridge/amd/amdfam10/chip.h @@ -22,4 +22,4 @@ struct northbridge_amd_amdfam10_config { uint64_t maximum_memory_capacity; }; -#endif /* _AMD_FAM10_CHIP_H_ */
\ No newline at end of file +#endif /* _AMD_FAM10_CHIP_H_ */ diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h index 0df3527701..24f38db771 100644 --- a/src/northbridge/amd/cimx/rd890/nb_cimx.h +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -36,4 +36,4 @@ void nb_Late_Post_Init(void); void nb_Pcie_Early_Init(void); void nb_Pcie_Late_Init(void); -#endif//_RD890_EARLY_H_ +#endif /* _NB_CIMX_H_ */ diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 00a5d6018b..61931fd958 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -78,4 +78,4 @@ void northbridge_acpi_fill_ssdt_generator(device_t device); #endif /* #ifndef __ASSEMBLER__ */ #endif /* #ifndef __ACPI__ */ -#endif /* #ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ */ +#endif /* __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ */ diff --git a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h index 007a80aa48..bce52226ac 100755 --- a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h +++ b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h @@ -154,6 +154,6 @@ enum drc_reg_set { #define DRC_REG_WRITE(unit, channel, reg, rv) \ soc_reg32_set((volatile uint32*)(channel + 4 * reg), rv) -#endif /* #ifndef __SOC_BROADCOM_CYGNUS_DDR_BIST_H__*/ +#endif /* __SOC_BROADCOM_CYGNUS_DDR_BIST_H__ */ /* End of File */ diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h index e9eec9ab4c..166cc0bb86 100755 --- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h +++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h @@ -11266,6 +11266,6 @@ #define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_SHIFT 0 #define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000 -#endif /* #ifndef __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__ */ +#endif /* __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__ */ /* End of File */ diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h index 0efd3ac5e9..97fba1740c 100755 --- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h +++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h @@ -1145,6 +1145,6 @@ extern int soc_ydc_ddr_bist_run(int unit, int phy_ndx, /**************************************************************************** * Datatype Definitions. ***************************************************************************/ -#endif /* #ifndef __SOC_BROADCOM_CYGNUS_YDC_DDR_BIST_H__ */ +#endif /* __SOC_BROADCOM_CYGNUS_YDC_DDR_BIST_H__ */ /* End of File */ diff --git a/src/soc/nvidia/tegra132/include/soc/id.h b/src/soc/nvidia/tegra132/include/soc/id.h index 198e3c4fdd..907285614c 100644 --- a/src/soc/nvidia/tegra132/include/soc/id.h +++ b/src/soc/nvidia/tegra132/include/soc/id.h @@ -28,4 +28,4 @@ static inline int context_avp(void) return read32(uptag) == avp_id; } -#endif /* define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ID_H__ */ +#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ID_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h index 5e487d2d6b..0903ba98ef 100644 --- a/src/soc/nvidia/tegra210/include/soc/id.h +++ b/src/soc/nvidia/tegra210/include/soc/id.h @@ -28,4 +28,4 @@ static inline int context_avp(void) return read32(uptag) == avp_id; } -#endif /* define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ */ +#endif /* __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index ab50d3f32f..482deadfe7 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -194,4 +194,4 @@ void nand_clock_config(void); void usb_clock_config(void); int audio_clock_config(unsigned frequency); -#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */ +#endif /* __IPQ860X_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/spi.h b/src/soc/qualcomm/ipq806x/include/soc/spi.h index 6d816daf5e..3e623463cc 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/spi.h +++ b/src/soc/qualcomm/ipq806x/include/soc/spi.h @@ -276,4 +276,4 @@ static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave) return container_of(slave, struct ipq_spi_slave, slave); } -#endif /* _IPQ_SPI_H_ */ +#endif /* _IPQ806X_SPI_H_ */ diff --git a/src/soc/samsung/exynos5250/include/soc/cpu.h b/src/soc/samsung/exynos5250/include/soc/cpu.h index 3ee3d13540..24bb96ffe2 100644 --- a/src/soc/samsung/exynos5250/include/soc/cpu.h +++ b/src/soc/samsung/exynos5250/include/soc/cpu.h @@ -81,4 +81,4 @@ static inline u32 get_fb_base_kb(void) return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; } -#endif /* _EXYNOS5250_CPU_H */ +#endif /* CPU_SAMSUNG_EXYNOS5250_CPU_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/cpu.h b/src/soc/samsung/exynos5420/include/soc/cpu.h index f268a5c476..f523b4104d 100644 --- a/src/soc/samsung/exynos5420/include/soc/cpu.h +++ b/src/soc/samsung/exynos5420/include/soc/cpu.h @@ -92,4 +92,4 @@ static inline u32 get_fb_base_kb(void) /* Procedures to setup Exynos5420 CPU */ void exynos5420_config_smp(void); -#endif /* _EXYNOS5420_CPU_H */ +#endif /* CPU_SAMSUNG_EXYNOS5420_CPU_H */ diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h index 45dda17425..7562417dd7 100644 --- a/src/southbridge/amd/cimx/sb700/Platform.h +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -82,4 +82,4 @@ void TraceCode ( UINT32 Level, UINT32 Code); #define DMSG_SB_TRACE 0x02 -#endif //#ifndef _AMD_SB_CIMx_PLATFORM_H_ +#endif /* _AMD_SB_CIMx_PLATFORM_H_ */ diff --git a/src/southbridge/amd/cs5535/chip.h b/src/southbridge/amd/cs5535/chip.h index d4dde3d6ee..37e5eadddd 100644 --- a/src/southbridge/amd/cs5535/chip.h +++ b/src/southbridge/amd/cs5535/chip.h @@ -5,4 +5,4 @@ struct southbridge_amd_cs5535_config { int setupflash; }; -#endif /* _SOUTHBRIDGE_AMD_CS5536 */ +#endif /* _SOUTHBRIDGE_AMD_CS5535 */ diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h index c0f13ac06f..9a2fec5196 100644 --- a/src/southbridge/amd/rs690/rs690.h +++ b/src/southbridge/amd/rs690/rs690.h @@ -134,4 +134,4 @@ void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); void config_gpp_core(device_t nb_dev, device_t sb_dev); void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); -#endif /* RS690_H */ +#endif /* __RS690_H__ */ diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index 341de0d487..ffd0e15172 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -210,4 +210,4 @@ int cpuidFamily(void); int is_family0Fh(void); int is_family10h(void); void pcie_hide_unused_ports(device_t nb_dev); -#endif /* RS780_H */ +#endif /* __RS780_H__ */ diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h index c6db26da5a..ea7005c9ef 100644 --- a/src/southbridge/amd/sr5650/sr5650.h +++ b/src/southbridge/amd/sr5650/sr5650.h @@ -132,4 +132,4 @@ void sr5650_nb_pci_table(device_t nb_dev); void init_gen2(device_t nb_dev, device_t dev, u8 port); void sr56x0_lock_hwinitreg(void); struct resource * sr5650_retrieve_cpu_mmio_resource(void); -#endif /* SR5650_H */ +#endif /* __SR5650_H__ */ diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h index 8147c513fb..9d6a9e4dbd 100644 --- a/src/southbridge/intel/fsp_bd82x6x/chip.h +++ b/src/southbridge/intel/fsp_bd82x6x/chip.h @@ -88,4 +88,4 @@ struct southbridge_intel_fsp_bd82x6x_config { int c2_latency; }; -#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 3018455cef..045c2285af 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -582,4 +582,4 @@ void display_fd_settings(void); #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ #endif /* __ACPI__ */ -#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ +#endif /* SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H */ diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 90610acb6a..ba0fa4e8c5 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -445,4 +445,4 @@ void rangeley_sb_early_initialization(void); #endif /* __ACPI__ */ -#endif /* SOUTHBRIDGE_INTEL_RANGELEY_PCH_H */ +#endif /* SOUTHBRIDGE_INTEL_RANGELEY_SOC_H */ diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h index 69a59b3d53..f77413d671 100644 --- a/src/southbridge/intel/i82801dx/chip.h +++ b/src/southbridge/intel/i82801dx/chip.h @@ -37,4 +37,4 @@ struct southbridge_intel_i82801dx_config { uint8_t ide1_enable; }; -#endif /* I82801DBM_CHIP_H */ +#endif /* I82801DX_CHIP_H */ diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h index 931d5db06f..4b1ab420d0 100644 --- a/src/superio/ite/it8671f/it8671f.h +++ b/src/superio/ite/it8671f/it8671f.h @@ -32,4 +32,4 @@ void it8671f_48mhz_clkin(void); void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase); -#endif /* SUPERIO_ITE_IT8671F__H */ +#endif /* SUPERIO_ITE_IT8671F_H */ diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index 0b33e24dba..37ef041aec 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -27,4 +27,4 @@ void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase); -#endif /* SUPERIO_SMSC_1306_H */ +#endif /* SUPERIO_SMSC_SIO1306_H */ |