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-rw-r--r--src/soc/amd/cezanne/Kconfig10
-rw-r--r--src/soc/amd/cezanne/Makefile.inc2
2 files changed, 5 insertions, 7 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index f2fdc7fc08..620c650ba1 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -342,13 +342,11 @@ config PSP_DISABLE_POSTCODES
help
Disables the output of port80 post codes from PSP.
-config PSP_POSTCODES_ON_ESPI
- bool "Use eSPI bus for PSP post codes"
- default y
- depends on !PSP_DISABLE_POSTCODES
+config PSP_INIT_ESPI
+ bool "Initialize eSPI in PSP Stage 2 Boot Loader"
help
- Select to send PSP port80 post codes on eSPI bus.
- If not selected, PSP port80 codes will be sent on LPC bus.
+ Select to initialize the eSPI controller in the PSP Stage 2 Boot
+ Loader.
config PSP_LOAD_MP2_FW
bool
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 5fda4b0b82..5708baa0e3 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -94,7 +94,7 @@ ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
PSP_SOFTFUSE_BITS += 7
endif
-ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y)
+ifeq ($(CONFIG_PSP_INIT_ESPI),y)
PSP_SOFTFUSE_BITS += 15
endif