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-rw-r--r--src/drivers/intel/fsp1_1/car.c6
-rw-r--r--src/drivers/intel/fsp2_0/memory_init.c9
-rw-r--r--src/mainboard/google/chell/bootblock_mainboard.c4
-rw-r--r--src/mainboard/google/glados/bootblock_mainboard.c4
-rw-r--r--src/mainboard/google/lars/bootblock_mainboard.c4
-rw-r--r--src/mainboard/intel/kunimitsu/bootblock_mainboard.c4
-rw-r--r--src/vboot/vboot_loader.c21
7 files changed, 21 insertions, 31 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 7eceebf5ba..1a5f9a8333 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -15,7 +15,6 @@
#include <arch/early_variables.h>
#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
#include <fsp/car.h>
#include <fsp/util.h>
#include <program_loading.h>
@@ -62,11 +61,6 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
car_soc_post_console_init();
car_mainboard_post_console_init();
- /* Ensure the EC is in the right mode for recovery */
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
- !IS_ENABLED(CONFIG_SEPARATE_VERSTAGE))
- google_chromeec_early_init();
-
set_fih_car(car_params->fih);
/* Return new stack value in RAM back to assembly stub. */
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index e545b6d155..1957cdb952 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -17,7 +17,6 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
#include <elog.h>
#include <fsp/api.h>
#include <fsp/util.h>
@@ -296,14 +295,6 @@ void fsp_memory_init(bool s3wake)
if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake)
boot_count_increment();
- /*
- * Before doing any memory init/training, ensure that the EC is in the
- * right mode. This saves an additional memory training when in recovery
- * mode.
- */
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- google_chromeec_early_init();
-
if (cbfs_boot_locate(&file_desc, name, NULL)) {
printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name);
die("FSPM not available!\n");
diff --git a/src/mainboard/google/chell/bootblock_mainboard.c b/src/mainboard/google/chell/bootblock_mainboard.c
index d514622442..627b4e8b08 100644
--- a/src/mainboard/google/chell/bootblock_mainboard.c
+++ b/src/mainboard/google/chell/bootblock_mainboard.c
@@ -14,7 +14,6 @@
*/
#include <bootblock_common.h>
-#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include "gpio.h"
@@ -28,8 +27,5 @@ static void early_config_gpio(void)
void bootblock_mainboard_init(void)
{
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
early_config_gpio();
}
diff --git a/src/mainboard/google/glados/bootblock_mainboard.c b/src/mainboard/google/glados/bootblock_mainboard.c
index d514622442..627b4e8b08 100644
--- a/src/mainboard/google/glados/bootblock_mainboard.c
+++ b/src/mainboard/google/glados/bootblock_mainboard.c
@@ -14,7 +14,6 @@
*/
#include <bootblock_common.h>
-#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include "gpio.h"
@@ -28,8 +27,5 @@ static void early_config_gpio(void)
void bootblock_mainboard_init(void)
{
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
early_config_gpio();
}
diff --git a/src/mainboard/google/lars/bootblock_mainboard.c b/src/mainboard/google/lars/bootblock_mainboard.c
index d514622442..627b4e8b08 100644
--- a/src/mainboard/google/lars/bootblock_mainboard.c
+++ b/src/mainboard/google/lars/bootblock_mainboard.c
@@ -14,7 +14,6 @@
*/
#include <bootblock_common.h>
-#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include "gpio.h"
@@ -28,8 +27,5 @@ static void early_config_gpio(void)
void bootblock_mainboard_init(void)
{
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
early_config_gpio();
}
diff --git a/src/mainboard/intel/kunimitsu/bootblock_mainboard.c b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c
index d514622442..627b4e8b08 100644
--- a/src/mainboard/intel/kunimitsu/bootblock_mainboard.c
+++ b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c
@@ -14,7 +14,6 @@
*/
#include <bootblock_common.h>
-#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include "gpio.h"
@@ -28,8 +27,5 @@ static void early_config_gpio(void)
void bootblock_mainboard_init(void)
{
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
early_config_gpio();
}
diff --git a/src/vboot/vboot_loader.c b/src/vboot/vboot_loader.c
index 7395fd7d92..207aadaac7 100644
--- a/src/vboot/vboot_loader.c
+++ b/src/vboot/vboot_loader.c
@@ -17,6 +17,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
#include <rmodule.h>
#include <rules.h>
#include <string.h>
@@ -89,9 +90,29 @@ int vb2_logic_executed(void)
static void vboot_prepare(void)
{
if (verification_should_run()) {
+ /*
+ * Note that this path isn't taken when
+ * CONFIG_RETURN_FROM_VERSTAGE is employed.
+ */
verstage_main();
car_set_var(vboot_executed, 1);
vb2_save_recovery_reason_vbnv();
+
+ /*
+ * Avoid double memory retrain when the EC is running RW code
+ * and a recovery request came in through an EC host event. The
+ * double retrain happens because the EC won't be rebooted
+ * until kernel verification notices the EC isn't running RO
+ * code which is after memory training. Therefore, reboot the
+ * EC after we've saved the potential recovery request so it's
+ * not lost. Lastly, only perform this sequence on x86
+ * platforms since those are the ones that currently do a
+ * costly memory training in recovery mode.
+ */
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
+ IS_ENABLED(CONFIG_ARCH_X86))
+ google_chromeec_early_init();
+
} else if (verstage_should_load()) {
struct cbfsf file;
struct prog verstage =