diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/protectli/vault_adl_p/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/system76/mtl/devicetree.cb | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb index f11dc6aba2..0089a5fb46 100644 --- a/src/mainboard/protectli/vault_adl_p/devicetree.cb +++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 145dbc22c5..5a6424ec14 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -13,7 +13,7 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" # FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true" register "cnvi_bt_core" = "true" register "cnvi_bt_audio_offload" = "true" diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb index 9a4cfb4215..0bd6721808 100644 --- a/src/mainboard/system76/mtl/devicetree.cb +++ b/src/mainboard/system76/mtl/devicetree.cb @@ -11,7 +11,7 @@ chip soc/intel/meteorlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Thermal register "tcc_offset" = "8" |