3 files changed, 50 insertions, 0 deletions
diff --git a/src/mainboard/google/urara/devicetree.cb b/src/mainboard/google/urara/devicetree.cb
index a328b9d1cf..e3eb091027 100644
--- a/src/mainboard/google/urara/devicetree.cb
+++ b/src/mainboard/google/urara/devicetree.cb
@@ -20,6 +20,7 @@
 #
 
 chip soc/imgtec/pistachio
+	device cpu_cluster 0 on end
 	chip drivers/generic/generic # I2C0 controller
 		device i2c 6 on end # Fake component for testing
 	end
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index f7a0848e86..fdeba0cc01 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -34,6 +34,7 @@ bootblock-y += monotonic_timer.c
 
 ramstage-y += cbmem.c
 ramstage-y += monotonic_timer.c
+ramstage-y += soc.c
 
 romstage-y += cbmem.c
 romstage-y += romstage.c
diff --git a/src/soc/imgtec/pistachio/soc.c b/src/soc/imgtec/pistachio/soc.c
new file mode 100644
index 0000000000..7c2884f0a6
--- /dev/null
+++ b/src/soc/imgtec/pistachio/soc.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 The Chromium OS Authors.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <symbols.h>
+
+static void soc_read_resources(device_t dev)
+{
+	ram_resource(dev, 0, (uintptr_t)_dram / KiB,
+		     (CONFIG_DRAM_SIZE_MB * MiB) / KiB);
+}
+
+static void soc_init(device_t dev)
+{
+	printk(BIOS_INFO, "CPU: Imgtec Pistachio\n");
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.init		= soc_init,
+};
+
+static void enable_soc_dev(device_t dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_imgtec_pistachio_ops = {
+	CHIP_NAME("SOC: Imgtec Pistachio")
+	.enable_dev = enable_soc_dev,
+};