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-rw-r--r--src/northbridge/intel/pineview/raminit.c36
-rw-r--r--src/southbridge/intel/common/Kconfig3
-rw-r--r--src/southbridge/intel/common/Makefile.inc2
-rw-r--r--src/southbridge/intel/common/hpet.c43
-rw-r--r--src/southbridge/intel/common/hpet.h11
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c16
7 files changed, 62 insertions, 50 deletions
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 2248d03c89..dd728e8a47 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -8,6 +8,7 @@
#include <console/console.h>
#include <delay.h>
#include <lib.h>
+#include <southbridge/intel/common/hpet.h>
#include "pineview.h"
#include "raminit.h"
#include <spd.h>
@@ -529,20 +530,6 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
}
}
-#define HPET_BASE 0xfed00000
-#define HPET32(x) *((volatile u32 *)(HPET_BASE + x))
-static void enable_hpet(void)
-{
- u32 reg32;
- reg32 = RCBA32(HPTC);
- reg32 &= ~0x03;
- reg32 |= (1 << 7);
- RCBA32(HPTC) = reg32;
- /* On NM10 this only works if read back */
- RCBA32(HPTC);
- HPET32(0x10) = HPET32(0x10) | 1;
-}
-
static void sdram_clk_crossing(struct sysinfo *s)
{
u8 ddr_freq, fsb_freq;
@@ -1595,27 +1582,6 @@ static void sdram_mmap(struct sysinfo *s)
pci_write_config32(HOST_BRIDGE, 0xac, tsegmb[s->dimm_config[0]]);
}
-static void hpet_udelay(u32 del)
-{
- u32 start, finish, now;
-
- del *= 15; /* now in usec */
-
- start = HPET32(0xf0);
- finish = start + del;
- while (1) {
- now = HPET32(0xf0);
- if (finish > start) {
- if (now >= finish)
- break;
- } else {
- if ((now < start) && (now >= finish)) {
- break;
- }
- }
- }
-}
-
static u8 sdram_checkrcompoverride(void)
{
u32 xcomp;
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 3030d25757..a14513dead 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE
config SOUTHBRIDGE_INTEL_COMMON_GPIO
def_bool n
+config SOUTHBRIDGE_INTEL_COMMON_HPET
+ def_bool n
+
config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
def_bool n
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 6c57481e55..f11ffa6aef 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -5,6 +5,8 @@ subdirs-y += firmware
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c
+
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
diff --git a/src/southbridge/intel/common/hpet.c b/src/southbridge/intel/common/hpet.c
new file mode 100644
index 0000000000..c48edae59d
--- /dev/null
+++ b/src/southbridge/intel/common/hpet.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/rcba.h>
+#include <stdint.h>
+
+#include "hpet.h"
+
+#define HPTC 0x3404
+
+#define HPET_BASE 0xfed00000
+#define HPET32(x) (*((volatile u32 *)(HPET_BASE + (x))))
+
+void enable_hpet(void)
+{
+ u32 reg32;
+ reg32 = RCBA32(HPTC);
+ reg32 &= ~0x03;
+ reg32 |= (1 << 7);
+ RCBA32(HPTC) = reg32;
+ /* Read back for posted write to take effect */
+ RCBA32(HPTC);
+ HPET32(0x10) = HPET32(0x10) | 1;
+}
+
+void hpet_udelay(u32 delay)
+{
+ u32 start, finish, now;
+
+ delay *= 15; /* now in usec */
+
+ start = HPET32(0xf0);
+ finish = start + delay;
+ while (1) {
+ now = HPET32(0xf0);
+ if (finish > start) {
+ if (now >= finish)
+ break;
+ } else {
+ if ((now < start) && (now >= finish))
+ break;
+ }
+ }
+}
diff --git a/src/southbridge/intel/common/hpet.h b/src/southbridge/intel/common/hpet.h
new file mode 100644
index 0000000000..1a69178e2e
--- /dev/null
+++ b/src/southbridge/intel/common/hpet.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOUTHBRIDGE_INTEL_COMMON_HPET_H
+#define SOUTHBRIDGE_INTEL_COMMON_HPET_H
+
+#include <stdint.h>
+
+void enable_hpet(void);
+void hpet_udelay(u32 delay);
+
+#endif /* SOUTHBRIDGE_INTEL_COMMON_HPET_H */
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 2d3bf24b3e..2cd56e95ff 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -21,6 +21,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
+ select SOUTHBRIDGE_INTEL_COMMON_HPET
if SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 712624c619..74cadc8df4 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -18,6 +18,7 @@
#include <arch/smp/mpspec.h>
#include <string.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
+#include <southbridge/intel/common/hpet.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/spi.h>
@@ -268,21 +269,6 @@ static void i82801gx_rtc_init(struct device *dev)
cmos_init(rtc_failed);
}
-static void enable_hpet(void)
-{
- u32 reg32;
-
- /* Move HPET to default address 0xfed00000 and enable it */
- reg32 = RCBA32(HPTC);
- reg32 |= (1 << 7); // HPET Address Enable
- reg32 &= ~(3 << 0);
- RCBA32(HPTC) = reg32;
- /* On NM10 this only works if read back */
- RCBA32(HPTC);
-
- write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);
-}
-
static void enable_clock_gating(void)
{
u32 reg32;