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-rw-r--r--src/southbridge/intel/bd82x6x/pch.h9
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h9
2 files changed, 10 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 8155479ebf..8face0649e 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -64,10 +64,6 @@ extern const struct southbridge_usb_port mainboard_usb_ports[14];
void early_usb_init(const struct southbridge_usb_port *portmap);
-/* PM I/O Space */
-#define UPRWC 0x3c
-#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
-
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
@@ -459,6 +455,11 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define SMI_STS 0x34
#define ALT_GP_SMI_EN 0x38
#define ALT_GP_SMI_STS 0x3a
+
+/* PM I/O Space */
+#define UPRWC 0x3c
+#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
+
#define GPE_CNTL 0x42
#define DEVACT_STS 0x44
#define PM2_CNT 0x50 // mobile only
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 5371641b6e..c447746eea 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -66,10 +66,6 @@ void pch_enable(struct device *dev);
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-/* PM I/O Space */
-#define UPRWC 0x3c
-#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
-
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
@@ -440,6 +436,11 @@ void pch_enable(struct device *dev);
#define SMI_STS 0x34
#define ALT_GP_SMI_EN 0x38
#define ALT_GP_SMI_STS 0x3a
+
+/* PM I/O Space */
+#define UPRWC 0x3c
+#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
+
#define GPE_CNTL 0x42
#define DEVACT_STS 0x44
#define PM2_CNT 0x50 // mobile only