summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/soc/mediatek/mt8192/include/soc/pll.h3
-rw-r--r--src/soc/mediatek/mt8192/pll.c6
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 170196b035..52bf3c2f38 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -306,6 +306,9 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
+DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24)
+DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12)
+
enum {
INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18),
INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18),
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index afa7c85e02..6d61fb4d5a 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -10,6 +10,7 @@
#include <soc/infracfg.h>
#include <soc/mcucfg.h>
#include <soc/pll.h>
+#include <soc/wdt.h>
enum mux_id {
TOP_AXI_SEL,
@@ -467,6 +468,11 @@ void mt_pll_init(void)
/* enable [14] dramc_pll104m_ck */
setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
+
+ /* reset CONNSYS MCU */
+ SET32_BITFIELDS(&mtk_wdt->wdt_swsysrst,
+ WDT_SWSYSRST_KEY, 0x88,
+ WDT_SWSYSRST_CONN_MCU, 0x1);
}
void mt_pll_raise_little_cpu_freq(u32 freq)