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-rw-r--r--src/northbridge/intel/gm45/acpi/gm45.asl28
1 files changed, 0 insertions, 28 deletions
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index 7d64200ddb..af58e0e712 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -12,16 +12,6 @@ Device (PDRC)
// This does not seem to work correctly yet - set values statically for
// now.
-
- //Name (PDRS, ResourceTemplate() {
- // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
- // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
- // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
- // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
- // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
- // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
- //})
-
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
@@ -36,24 +26,6 @@ Device (PDRC)
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
- //CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
- //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
-
- //CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
- //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
-
- //CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
- //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
-
- //CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
- //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
-
- //CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
- //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
-
- //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
- //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
-
Return(PDRS)
}
}