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-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h3
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio.h3
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h2
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h2
4 files changed, 3 insertions, 7 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index de96355942..157ad4ec3c 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -52,9 +52,6 @@
#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29)
-#define PM_RST_CTRL1 0xbe
-#define SLPTYPE_CONTROL_EN BIT(5)
-#define KBRSTEN BIT(4)
#define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1)
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 7891bfddb1..2e1da882c0 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -26,6 +26,9 @@
#define LEGACY_DMA_IO_EN (1 << 2)
#define CF9_IO_EN (1 << 1)
#define LEGACY_IO_EN (1 << 0)
+#define PM_RST_CTRL1 0xbe
+#define SLPTYPE_CONTROL_EN (1 << 5)
+#define KBRSTEN (1 << 4)
#define PM_RST_STATUS 0xc0
/*
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 49e4948495..ede210852c 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -68,8 +68,6 @@
#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29)
-#define PM_RST_CTRL1 0xbe
-#define SLPTYPE_CONTROL_EN BIT(5)
#define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1)
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 8aa881bb34..74f2937c1c 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -70,8 +70,6 @@
#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29)
-#define PM_RST_CTRL1 0xbe
-#define SLPTYPE_CONTROL_EN BIT(5)
#define PM_PCIB_CFG 0xea
#define PM_GENINT_DISABLE BIT(0)
#define PM_LPC_GATING 0xec