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-rw-r--r--src/cpu/intel/socket_mPGA604_533Mhz/Config.lb4
-rw-r--r--src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c1
-rw-r--r--src/mainboard/tyan/s2735/Config.lb21
-rw-r--r--src/mainboard/tyan/s2735/Options.lb6
-rw-r--r--src/mainboard/tyan/s2735/mainboard.c1
-rw-r--r--src/northbridge/intel/e7501/northbridge.c1
-rw-r--r--src/northbridge/intel/e7501/raminit.c393
-rw-r--r--src/southbridge/intel/i82801er/i82801er.c1
8 files changed, 37 insertions, 391 deletions
diff --git a/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb b/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb
index 0538143469..fde9b9c165 100644
--- a/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb
+++ b/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb
@@ -1,4 +1,4 @@
-config chip.h
-object socket_mPGA604_533Mhz.o
+#config chip.h
+#object socket_mPGA604_533Mhz.o
dir /cpu/intel/model_f2x
diff --git a/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c b/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c
index 0831ac09c0..b98a280a2b 100644
--- a/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c
+++ b/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c
@@ -3,5 +3,4 @@
struct chip_operations cpu_intel_socket_mPGA604_533Mhz_ops = {
- .name = "socket mPGA604_533Mhz",
};
diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb
index eb1bb5c934..52c1ccde4f 100644
--- a/src/mainboard/tyan/s2735/Config.lb
+++ b/src/mainboard/tyan/s2735/Config.lb
@@ -43,26 +43,27 @@ if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
+
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h "
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
-makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb
index be05b56b27..655ba4323d 100644
--- a/src/mainboard/tyan/s2735/Options.lb
+++ b/src/mainboard/tyan/s2735/Options.lb
@@ -46,6 +46,7 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_GDB_STUB
###
### Build options
@@ -172,6 +173,11 @@ default CC="gcc"
default HOSTCC="gcc"
##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
## The Serial Console
##
diff --git a/src/mainboard/tyan/s2735/mainboard.c b/src/mainboard/tyan/s2735/mainboard.c
index ccc3a93b27..7898d2e7e4 100644
--- a/src/mainboard/tyan/s2735/mainboard.c
+++ b/src/mainboard/tyan/s2735/mainboard.c
@@ -144,6 +144,5 @@ static void enable_dev(device_t dev)
struct chip_operations mainboard_tyan_s2735_ops = {
.enable_dev = enable_dev,
- .name = "Tyan s2735 mainboard ",
};
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 065ea54f8a..43c354cfc1 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -186,6 +186,5 @@ static void enable_dev(struct device *dev)
}
}
struct chip_operations northbridge_intel_e7501_ops = {
- .name = "intel E7501 Northbridge",
.enable_dev = enable_dev,
};
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index ef231666e3..020585a30b 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -12,7 +12,7 @@
/* converted to C 6/2004 yhlu */
-#define DEBUG_RAM_CONFIG 0
+#define DEBUG_RAM_CONFIG 1
#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0))
@@ -535,27 +535,6 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x1c0);
write_8dwords((uint32_t)ddr_rcomp_3, RCOMP_MMIO + 0x180);
-#if 0 /* Print the RCOMP registers */
- movl $RCOMP_MMIO, %ecx
-1: movl %ecx, %eax
- andb $0x0f, %al
- jnz 2f
- CONSOLE_INFO_TX_CHAR($'\r')
- CONSOLE_INFO_TX_CHAR($'\n')
- CONSOLE_INFO_TX_HEX32(%ecx)
- CONSOLE_INFO_TX_CHAR($' ')
- CONSOLE_INFO_TX_CHAR($'-')
- CONSOLE_INFO_TX_CHAR($' ')
-2: movl (%ecx), %eax
- CONSOLE_INFO_TX_HEX32(%eax)
- CONSOLE_INFO_TX_CHAR($' ')
- addl $4, %ecx
- cmpl $(RCOMP_MMIO + 0x1e0), %ecx
- jnz 1b
- CONSOLE_INFO_TX_CHAR($'\r')
- CONSOLE_INFO_TX_CHAR($'\n')
-#endif
-
dword = read32(RCOMP_MMIO + 0x20);
dword &= ~(3);
dword |= 1;
@@ -584,7 +563,7 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
}
static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG >= 2
dumpnorth();
#endif
int i;
@@ -592,7 +571,7 @@ static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
max = sizeof(register_values)/sizeof(register_values[0]);
for(i = 0; i < max; i += 3) {
uint32_t reg;
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG >= 2
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
@@ -605,7 +584,7 @@ static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
}
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG >= 2
dumpnorth();
#endif
}
@@ -896,7 +875,7 @@ static long spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_
/* Test to see if I have ecc sdram */
struct dimm_page_size sz;
sz = sdram_spd_get_page_size(ctrl->channel0[i]); /* SDRAM type */
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG>=2
print_debug("page size =");
print_debug_hex32(sz.side1);
print_debug(" ");
@@ -975,241 +954,6 @@ static long spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_
return dimm_mask;
}
-#if 0
- /*
- * Routine: sdram_read_paired_byte
- * Arguments: %esp return address
- * %bl device on the smbus to read from
- * %bh address on the smbus to read
- * Results:
- * zf clear
- * byte read in %al
- * On Error:
- * zf set
- * %eax trashed
- *
- * Preserved: %ebx, %esi, %edi
- *
- * Trashed: %eax, %ecx, %edx, %ebp, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %esp, %eflags
- *
- * Effects: Reads two spd bytes from both ram channesl
- * and errors if they are not equal.
- * It then returns the equal result.
- */
-static spd_read_paired_byte () {
- movl %esp, %ebp
- CALLSP(smbus_read_byte)
- setnz %cl
- movb %al, %ch
- addb $(SMBUS_MEM_CHANNEL_OFF), %bl
- CALLSP(smbus_read_byte)
- movb %ch, %ah
- setnz %ch
- subb $(SMBUS_MEM_CHANNEL_OFF), %bl
-
- /* See if dimms on both sides are equally present */
- cmp %cl, %ch
- jne sdram_presence_mismatch
-
- /* Leave if I have no data */
- testb %cl, %cl
- jz spd_verify_byte_out
-
- /* Verify the data is identical */
- cmp %ah, %al
- jne sdram_value_mismatch
-
- /* Clear the zero flag */
- testb %cl, %cl
-spd_verify_byte_out:
- movl %ebp, %esp
- RETSP
-}
-
- /*
- * Routine: spd_verify_dimms
- * Arguments: none
- * Results: none
- * Preserved: none
- * Trashed: %eax, %ebx, %ecx, %edx, %ebp, %esi, %edi, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %ebp, %esi, %edi, %esp, %eflags
- *
- * Effects:
- * - Verify all interesting spd information
- * matches for both dimm channels.
- * - Additional error checks that can be easily done
- * here are computed as well, so I don't need to
- * worry about them later.
- */
-static spd_verify_dimms() {
- movl $(SMBUS_MEM_DEVICE_START), %ebx
-spd_verify_dimm:
- /* Verify this is DDR SDRAM */
- movb $2, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_verify_next_dimm
- cmpb $7, %al
- jne invalid_dimm_type
-
- /* Verify the row addresses */
- movb $3, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0x0f, %al
- jz spd_invalid_data
-
- /* Column addresses */
- movb $4, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xf, %al
- jz spd_invalid_data
-
- /* Physical Banks */
- movb $5, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmp $1, %al
- jb spd_invalid_data
- cmp $2, %al
- ja spd_invalid_data
-
- /* Module Data Width */
- movb $7, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmpb $0, %al
- jne spd_invalid_data
-
- movb $6, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmpb $64, %al
- je 1f
- cmpb $72, %al
- je 1f
- jmp spd_unsupported_data
-1:
-
- /* Cycle time at highest CAS latency CL=X */
- movb $9, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* SDRAM type */
- movb $11, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* Refresh Interval */
- movb $12, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* SDRAM Width */
- movb $13, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- andb $0x7f, %al
- cmpb $4, %al
- je 1f
- cmpb $8, %al
- je 1f
- jmp spd_unsupported_data
-1:
-
- /* Back-to-Back Random Column Accesses */
- movb $15, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
- cmpb $4, %al
- ja spd_unsupported_data
-
- /* Burst Lengths */
- movb $16, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1<<2), %al
- jz spd_unsupported_data
-
- /* Logical Banks */
- movb $17, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
-
- /* Supported CAS Latencies */
- movb $18, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1 << 1), %al /* CL 1.5 */
- jnz 1f
- testb $(1 << 2), %al /* CL 2.0 */
- jnz 1f
- testb $(1 << 3), %al /* CL 2.5 */
- jnz 1f
- jmp spd_unsupported_data
-1:
-
- /* Cycle time at Cas Latency (CLX - 0.5) */
- movb $23, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* Cycle time at Cas Latency (CLX - 1.0) */
- movb $26, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* tRP Row precharge time */
- movb $27, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xfc, %al
- jz spd_invalid_data
-
-
- /* tRCD RAS to CAS */
- movb $29, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xfc, %al
- jz spd_invalid_data
-
- /* tRAS Activate to Precharge */
- movb $30, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
-
- /* Module Bank Density */
- movb $31, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1<<2), %al /* 16MB */
- jnz spd_unsupported_data
- testb $(1<<3), %al
- jnz spd_unsupported_data /* 32MB */
-
- /* Address and Command Hold Time After Clock */
- movb $33, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
-spd_verify_next_dimm:
- /* go to the next DIMM */
- addb $(SMBUS_MEM_DEVICE_INC), %bl /* increment the smbus device */
- cmpb $SMBUS_MEM_DEVICE_END, %bl
- jbe spd_verify_dimm
-spd_verify_dimms_out:
- RET_LABEL(spd_verify_dimms)
-}
-#endif
#define spd_pre_init "Reading SPD data...\r\n"
#define spd_pre_set "setting based on SPD data...\r\n"
#define spd_post_init "done\r\n"
@@ -1248,17 +992,17 @@ static long spd_set_dram_controller_mode (const struct mem_controller *ctrl, lon
/* Read the inititial state */
dword = pci_read_config32(ctrl->d0, 0x7c);
-#if 0
- /* Test if ECC cmos option is enabled */
+/*
+ // Test if ECC cmos option is enabled
movb $RTC_BOOT_BYTE, %al
outb %al, $0x70
inb $0x71, %al
testb $(1<<2), %al
jnz 1f
- /* Clear the ecc enable */
+ // Clear the ecc enable
andl $~(3 << 20), %esi
1:
-#endif
+*/
/* Walk through all dimms and find the interesection of the support
@@ -1323,11 +1067,11 @@ static long spd_enable_clocks(const struct mem_controller *ctrl, long dimm_mask)
/* Read the inititial state */
dword = pci_read_config32(ctrl->d0, 0x8c);
-#if 0
+/*
# Intel clears top bit here, should we?
# No the default is on and for normal timming it should be on. Tom Z
andl $0x7f, %esi
-#endif
+*/
for(i = 0; i < DIMM_SOCKETS; i++) {
@@ -1506,11 +1250,11 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, long dimm_mas
/* Read the inititial state */
dword = pci_read_config32(ctrl->d0, 0x78);
-#if 0
+/*
# Intel clears top bit here, should we?
# No the default is on and for normal timming it should be on. Tom Z
andl $0x7f, %esi
-#endif
+*/
for(i = 0; i < DIMM_SOCKETS; i++) {
@@ -1604,13 +1348,13 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
unsigned dimm_mask;
int i;
dimm_mask = 0;
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG
print_debug("spd_detect_dimms:\r\n");
#endif
for(i = 0; i < DIMM_SOCKETS; i++) {
int byte;
unsigned device;
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG
print_debug_hex32(i);
print_debug("\r\n");
#endif
@@ -1795,71 +1539,6 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
}
- /* I have finally seen ram bad enough to cause LinuxBIOS
- * to die in mysterious ways, before booting up far
- * enough to run a memory tester. This code attempts
- * to catch this blatantly bad ram, with a spot check.
- * For most cases you should boot all of the way up
- * and run a memory tester.
- */
- /* Ensure I read/write each stick of bank of memory &&
- * that I do more than 1000 bytes to avoid the northbridge cache.
- * Only 64M of each side of each DIMM is currently mapped,
- * so we can handle > 4GB of ram here.
- */
-#if 0
-#define bank_msg "Bank "
-#define side_msg " Side "
-static void verify_ram() {
- xorl %ecx, %ecx
- /* Check to see if the RAM is present,
- * in the specified bank and side.
- */
-1: movl %ecx, %ebx
- shrl $1, %ebx
- addl $((5<<8) | SMBUS_MEM_DEVICE_START), %ebx
- CALLSP(smbus_read_byte)
- jz 5f
- testl $1, %ecx
- jz 2f
- cmpb $2, %al
- jne 5f
-
- /* Display the bank and side we are spot checking.
- */
-2: CONSOLE_INFO_TX_STRING($bank_msg)
- movl %ecx, %ebx
- shrl $1, %ebx
- incl %ebx
- CONSOLE_INFO_TX_HEX8(%bl)
- CONSOLE_INFO_TX_STRING($side_msg)
- movl %ecx, %ebx
- andl $1, %ebx
- CONSOLE_INFO_TX_HEX8(%bl)
-
- /* Compute the memory address to spot check. */
- movl %ecx, %ebx
- xorl %eax, %eax
-3: testl %ebx, %ebx
- jz 4f
- addl $0x04000000, %eax
- decl %ebx
- jmp 3b
-4:
- /* Spot check 512K of RAM */
- movl %eax, %ebx
- addl $0x0007ffff, %ebx
- CALLSP(spot_check)
-5:
- /* Now find the next bank and side to spot check */
- incl %ecx
- cmpl $((SMBUS_MEM_DEVICE_END - SMBUS_MEM_DEVICE_START)<<1), %ecx
- jb 1b
- RET_LABEL(verify_ram)
-
-}
-#endif
-
#if 0
static void ram_postinit(const struct mem_controller *ctrl) {
#if DEBUG_RAM_CONFIG
@@ -1890,7 +1569,7 @@ static void dram_finish(const struct mem_controller *ctrl)
dword &=3;
if(dword == 2) {
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG
print_debug(ecc_pre_init);
#endif
/* Initialize ECC bits , use ECC zero mode (new to 7501)*/
@@ -1902,7 +1581,7 @@ static void dram_finish(const struct mem_controller *ctrl)
} while ( (byte & 0x08 ) == 0);
pci_write_config8(ctrl->d0, 0x52, byte & 0xfc);
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG
print_debug(ecc_post_init);
#endif
@@ -1921,48 +1600,12 @@ static void dram_finish(const struct mem_controller *ctrl)
pci_write_config32(ctrl->d0, 0x7c, dword);
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG >= 2
dumpnorth();
#endif
// verify_ram();
}
-#if 0
-#define ERRFUNC(x, str) mem_err(x, str)
-
-
-ERRFUNC(invalid_dimm_type, "Invalid dimm type")
-ERRFUNC(spd_missing_data, "Missing sdram spd data")
-ERRFUNC(spd_invalid_data, "Invalid sdram spd data")
-ERRFUNC(spd_unsupported_data, "Unsupported sdram spd value")
-ERRFUNC(unsupported_page_size, "Unsupported page size")
-ERRFUNC(sdram_presence_mismatch, "DIMM presence mismatch")
-ERRFUNC(sdram_value_mismatch, "spd data does not match")
-ERRFUNC(unsupported_refresh_rate, "Unsuported spd refresh rate")
-ERRFUNC(inconsistent_cas_latencies, "No cas latency supported by all dimms")
-ERRFUNC(unsupported_rcd, "Unsupported ras to cas delay")
-#undef ERRFUNC
-
-#define mem_err_err "ERROR: "
-#define mem_err_pair " on dimm pair "
-#define mem_err_byte " spd byte "
-static void mem_err {
- movl %ebx, %edi
- CONSOLE_ERR_TX_STRING($mem_err_err)
- CONSOLE_ERR_TX_STRING(%esi)
- CONSOLE_ERR_TX_STRING($mem_err_pair)
- movl %edi, %ebx
- subb $(SMBUS_MEM_DEVICE_START), %bl
- CONSOLE_ERR_TX_HEX8(%bl)
- CONSOLE_ERR_TX_STRING($mem_err_byte)
- movl %edi, %ebx
- CONSOLE_ERR_TX_HEX8(%bh)
- jmp mem_stop
-
-}
-
-#endif
-
#if ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG
#define ram_enable_1 "Ram Enable 1\r\n"
diff --git a/src/southbridge/intel/i82801er/i82801er.c b/src/southbridge/intel/i82801er/i82801er.c
index 39bbc9f404..c721a29983 100644
--- a/src/southbridge/intel/i82801er/i82801er.c
+++ b/src/southbridge/intel/i82801er/i82801er.c
@@ -51,6 +51,5 @@ void i82801er_enable(device_t dev)
}
struct chip_operations southbridge_intel_i82801er_ops = {
- .name = "Intel 82801er Southbridge",
.enable_dev = i82801er_enable,
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 19:07:32 +0000