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-rw-r--r--src/soc/intel/xeon_sp/cpx/chip.c2
-rw-r--r--src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h27
-rw-r--r--src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h2
-rw-r--r--src/soc/intel/xeon_sp/cpx/soc_util.c139
4 files changed, 170 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index c2d448c21c..c3159feec3 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -585,6 +585,8 @@ static void chip_enable_dev(struct device *dev)
static void chip_final(void *data)
{
p2sb_hide();
+
+ set_bios_init_completion();
}
static void chip_init(void *data)
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index d660d8964a..71c68cf885 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -4,6 +4,7 @@
#define _SOC_PCI_DEVS_H_
#include <device/pci_def.h>
+#include <types.h>
#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
@@ -23,6 +24,32 @@
#define SAD_ALL_PAM0123_CSR 0x40
#define SAD_ALL_PAM456_CSR 0x44
+#define PCU_IIO_STACK 1
+#define PCU_DEV 30
+#define PCU_CR1_FUN 1
+
+#define PCU_CR1_BIOS_MB_DATA_REG 0x8c
+
+#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90
+#define BIOS_MB_RUN_BUSY_MASK BIT(31)
+#define BIOS_MB_CMD_MASK 0xff
+#define BIOS_CMD_READ_PCU_MISC_CFG 0x5
+#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6
+#define BIOS_ERR_INVALID_CMD 0x01
+
+#define PCU_CR1_BIOS_RESET_CPL_REG 0x94
+#define RST_CPL1_MASK BIT(1)
+#define RST_CPL2_MASK BIT(2)
+#define RST_CPL3_MASK BIT(3)
+#define RST_CPL4_MASK BIT(4)
+#define PCODE_INIT_DONE1_MASK BIT(9)
+#define PCODE_INIT_DONE2_MASK BIT(10)
+#define PCODE_INIT_DONE3_MASK BIT(11)
+#define PCODE_INIT_DONE4_MASK BIT(12)
+
+#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0
+#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
+
#define UBOX_DECS_BUS 0
#define UBOX_DECS_DEV 8
#define UBOX_DECS_FUNC 2
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
index 1c3ca66c52..2d33d0e355 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
@@ -40,4 +40,6 @@ int get_platform_thread_count(void);
int get_threads_per_package(void);
const struct SystemMemoryMapHob *get_system_memory_map(void);
+void set_bios_init_completion(void);
+
#endif /* _SOC_UTIL_H_ */
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index 2e183ef062..6919fc21aa 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -2,12 +2,16 @@
#include <assert.h>
#include <commonlib/sort.h>
+#include <delay.h>
#include <device/device.h>
+#include <device/pci.h>
#include <intelblocks/cpulib.h>
#include <soc/cpu.h>
+#include <soc/pci_devs.h>
#include <soc/soc_util.h>
#include <stdlib.h>
#include <string.h>
+#include <timer.h>
int get_threads_per_package(void)
{
@@ -179,3 +183,138 @@ uint8_t get_iiostack_info(struct iiostack_resource *info)
return hob->PlatformData.Pci64BitResourceAllocation;
}
+
+/* return true if command timed out else false */
+static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask,
+ uint32_t target)
+{
+ const uint32_t max_delay = 5000; /* 5 seconds max */
+ const uint32_t step_delay = 50; /* 50 us */
+ struct stopwatch sw;
+
+ stopwatch_init_msecs_expire(&sw, max_delay);
+ while ((pci_s_read_config32(dev, reg) & mask) != target) {
+ udelay(step_delay);
+ if (stopwatch_expired(&sw)) {
+ printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, "
+ "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target);
+ return true; /* timedout */
+ }
+ }
+ return false; /* successful */
+}
+
+/* return true if command timed out else false */
+static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data)
+{
+ /* verify bios is not in busy state */
+ if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0))
+ return true; /* timed out */
+
+ /* write data to data register */
+ printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
+ PCU_CR1_BIOS_MB_DATA_REG, data);
+ pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data);
+
+ /* write the command */
+ printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__,
+ PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK);
+ pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
+ command | BIOS_MB_RUN_BUSY_MASK);
+
+ /* wait for completion or time out*/
+ return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
+ BIOS_MB_RUN_BUSY_MASK, 0);
+}
+
+static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
+{
+ const IIO_UDS *hob = get_iio_uds();
+
+ assert(socket < hob->SystemStatus.numCpus && stack < MAX_LOGIC_IIO_STACK);
+
+ return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase;
+}
+
+/* return true if command timed out else false */
+static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
+ uint32_t pcode_init_mask, uint32_t val)
+{
+ const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
+ const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
+
+ uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
+ reg &= (uint32_t) ~rst_cpl_mask;
+ reg |= val;
+
+ /* update BIOS RESET completion bit */
+ pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
+
+ /* wait for PCU ack */
+ return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
+ pcode_init_mask);
+}
+
+static void set_bios_init_completion_for_package(uint32_t socket)
+{
+ uint32_t data;
+ bool timedout;
+ const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
+ const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
+
+ /* read PCU config */
+ timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
+ if (timedout) {
+ /* 2nd try */
+ timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
+ if (timedout)
+ die("BIOS PCU Misc Config Read timed out.\n");
+
+ /* Since the 1st try failed, we need to make sure PCU is in stable state */
+ data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG);
+ printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n",
+ __func__, PCU_CR1_BIOS_MB_DATA_REG, data);
+ timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data);
+ if (timedout)
+ die("BIOS PCU Misc Config Write timed out.\n");
+ }
+
+ /* update RST_CPL3, PCODE_INIT_DONE3 */
+ timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK,
+ PCODE_INIT_DONE3_MASK, RST_CPL3_MASK);
+ if (timedout)
+ die("BIOS RESET CPL3 timed out.\n");
+
+ /* update RST_CPL4, PCODE_INIT_DONE4 */
+ timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK,
+ PCODE_INIT_DONE4_MASK, RST_CPL4_MASK);
+ if (timedout)
+ die("BIOS RESET CPL4 timed out.\n");
+
+ /* set CSR_DESIRED_CORES_CFG2 lock bit */
+ data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG);
+ data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK;
+ printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n",
+ __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
+ pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
+}
+
+void set_bios_init_completion(void)
+{
+ /* FIXME: This may need to be changed for multi-socket platforms */
+ uint32_t sbsp_socket_id = 0;
+
+ /*
+ * According to the BIOS Writer's Guide, the SBSP must be the last socket
+ * to receive the BIOS init completion message. So, we send it to all non-SBSP
+ * sockets first.
+ */
+ for (uint32_t socket = 0; socket < xeon_sp_get_cpu_count(); ++socket) {
+ if (socket == sbsp_socket_id)
+ continue;
+ set_bios_init_completion_for_package(socket);
+ }
+
+ /* And finally, take care of the SBSP */
+ set_bios_init_completion_for_package(sbsp_socket_id);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 09:58:57 +0000