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-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/finalize.c5
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index b90fdefe76..31e733cba9 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -63,6 +63,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_HDA
+ select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 733f037975..50215954b9 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -9,6 +9,7 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <intelblocks/cpulib.h>
+#include <intelblocks/cse.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
@@ -30,7 +31,7 @@
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
-static void pch_disable_heci(void)
+void soc_disable_heci1_using_pcr(void)
{
/* unhide p2sb device */
p2sb_unhide();
@@ -60,7 +61,7 @@ static void pch_finalize_script(struct device *dev)
/* we should disable Heci1 based on the config */
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
- pch_disable_heci();
+ heci1_disable();
/* Hide p2sb device as the OS must not change BAR0. */
p2sb_hide();