diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pmc.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/lockdown.c | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index ca11ae933a..d1e63bc5cf 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -76,6 +76,10 @@ extern struct device_operations pmc_ops; #define PRSTS 0x1810 +#define PM_CFG 0x1818 +#define PM_CFG_DBG_MODE_LOCK (1 << 27) +#define PM_CFG_XRAM_READ_DISABLE (1 << 22) + #define S3_PWRGATE_POL 0x1828 #define S3DC_GATE_SUS (1 << 1) #define S3AC_GATE_SUS (1 << 0) diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index f018dbd28d..4b260da1af 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -27,6 +27,8 @@ static void pmc_lockdown_cfg(int chipset_lockdown) if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); setbits32(pmcbase + SSML, SSML_SSL_EN); + setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | + PM_CFG_XRAM_READ_DISABLE); } } |