diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/glinda/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/glinda/fch.c | 41 | ||||
| -rw-r--r-- | src/soc/amd/glinda/include/soc/southbridge.h | 13 |
3 files changed, 2 insertions, 53 deletions
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 8a6649a169..d52900208a 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -46,6 +46,7 @@ config SOC_AMD_GLINDA select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_GPP_CLK select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index bb03ad455f..2218ce3e9d 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -132,46 +132,7 @@ static void fch_init_acpi_ports(void) static void gpp_clk_setup(void) { struct soc_amd_glinda_config *cfg = config_of_soc(); - - /* look-up table to be able to iterate over the PCIe clock output settings */ - const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { - GPP_CLK0_REQ_SHIFT, - GPP_CLK1_REQ_SHIFT, - GPP_CLK2_REQ_SHIFT, - GPP_CLK3_REQ_SHIFT, - GPP_CLK4_REQ_SHIFT, - GPP_CLK5_REQ_SHIFT, - GPP_CLK6_REQ_SHIFT, - }; - - uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - - pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], - ARRAY_SIZE(cfg->gpp_clk_config)); - for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { - gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); - /* - * The remapping of values is done so that the default of the enum used for the - * devicetree settings is the clock being enabled, so that a missing devicetree - * configuration for this will result in an always active clock and not an - * inactive PCIe clock output. Only the configuration for the clock outputs - * available on the package is provided via the devicetree; the rest is - * switched off unconditionally. - */ - switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) { - case GPP_CLK_REQ: - gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); - break; - case GPP_CLK_OFF: - gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); - break; - case GPP_CLK_ON: - default: - gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); - } - } - - misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); + gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config)); } static void cgpll_clock_gate_init(void) diff --git a/src/soc/amd/glinda/include/soc/southbridge.h b/src/soc/amd/glinda/include/soc/southbridge.h index 32945e88ff..9cd835b21a 100644 --- a/src/soc/amd/glinda/include/soc/southbridge.h +++ b/src/soc/amd/glinda/include/soc/southbridge.h @@ -87,20 +87,7 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ /* FCH MISC Registers 0xfed80e00 */ -#define GPP_CLK_CNTRL 0x00 -#define GPP_CLK0_REQ_SHIFT 0 -#define GPP_CLK1_REQ_SHIFT 2 -#define GPP_CLK4_REQ_SHIFT 4 -#define GPP_CLK2_REQ_SHIFT 6 -#define GPP_CLK3_REQ_SHIFT 8 -#define GPP_CLK5_REQ_SHIFT 10 -#define GPP_CLK6_REQ_SHIFT 12 -#define GPP_CLK_OUTPUT_COUNT 7 #define GPP_CLK_OUTPUT_AVAILABLE 4 -#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) -#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) -#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) -#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift)) #define MISC_CLKGATEDCNTL 0x2c #define ALINKCLK_GATEOFFEN BIT(16) |