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-rw-r--r--src/southbridge/intel/common/gpio.c11
-rw-r--r--src/southbridge/intel/common/pmbase.c11
2 files changed, 4 insertions, 18 deletions
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index bfe6ef3b77..20071af68e 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -13,25 +13,18 @@
/* LPC GPIO Base Address Register */
#define GPIO_BASE 0x48
-/* PCI Configuration Space (D31:F0): LPC */
-#if defined(__SIMPLE_DEVICE__)
-#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
-#else
-#define PCH_LPC_DEV pcidev_on_root(0x1f, 0)
-#endif
-
static u16 get_gpio_base(void)
{
#ifdef __SIMPLE_DEVICE__
/* Don't assume GPIO_BASE is still the same */
- return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
+ return pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIO_BASE) & 0xfffe;
#else
static u16 gpiobase;
if (gpiobase)
return gpiobase;
- gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
+ gpiobase = pci_read_config16(pcidev_on_root(0x1f, 0), GPIO_BASE) & 0xfffe;
return gpiobase;
#endif
diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c
index a637d000cd..265588230f 100644
--- a/src/southbridge/intel/common/pmbase.c
+++ b/src/southbridge/intel/common/pmbase.c
@@ -16,25 +16,18 @@
#define PMBASE 0x40
#define PMSIZE 0x80
-/* PCI Configuration Space (D31:F0): LPC */
-#if defined(__SIMPLE_DEVICE__)
-#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
-#else
-#define PCH_LPC_DEV pcidev_on_root(0x1f, 0)
-#endif
-
u16 lpc_get_pmbase(void)
{
#ifdef __SIMPLE_DEVICE__
/* Don't assume PMBASE is still the same */
- return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
+ return pci_read_config16(PCI_DEV(0, 0x1f, 0), PMBASE) & 0xfffc;
#else
static u16 pmbase;
if (pmbase)
return pmbase;
- pmbase = pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
+ pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), PMBASE) & 0xfffc;
return pmbase;
#endif